DE102006004796B4 - A method of fabricating a BiCMOS device comprising a first bipolar device and a second bipolar device of the same doping type - Google Patents
A method of fabricating a BiCMOS device comprising a first bipolar device and a second bipolar device of the same doping type Download PDFInfo
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- DE102006004796B4 DE102006004796B4 DE200610004796 DE102006004796A DE102006004796B4 DE 102006004796 B4 DE102006004796 B4 DE 102006004796B4 DE 200610004796 DE200610004796 DE 200610004796 DE 102006004796 A DE102006004796 A DE 102006004796A DE 102006004796 B4 DE102006004796 B4 DE 102006004796B4
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1203—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body the substrate comprising an insulating body on a semiconductor body, e.g. SOI
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8222—Bipolar technology
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8248—Combination of bipolar and field-effect technology
- H01L21/8249—Bipolar and MOS technology
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/84—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being other than a semiconductor body, e.g. being an insulating body
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
- H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
- H01L27/0611—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region
- H01L27/0617—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region comprising components of the field-effect type
- H01L27/0623—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region comprising components of the field-effect type in combination with bipolar transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
- H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind
- H01L27/082—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including bipolar components only
- H01L27/0823—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including bipolar components only including vertical bipolar transistors only
- H01L27/0825—Combination of vertical direct transistors of the same conductivity type having different characteristics,(e.g. Darlington transistors)
Abstract
Verfahren
zur Herstellung eines BiCMOS-Bauelements, umfassend ein erstes bipolares
Bauelement und ein zweites bipolares Bauelement desselben Dotierungstyps,
wobei das Verfahren die folgenden Schritte umfasst:
– Abscheidung
einer dielektrischen Schicht (24) über einer Halbleiterschicht
(14);
– Abscheidung
einer Gate-Leiterschicht (26) über
der dielektrischen Schicht (24);
– Definition von Basiszonen
(28, 30) des ersten und des zweiten bipolaren Bauelements;
– Entfernen
der Gate-Leiterschicht (26) und der dielektrischen Schicht (24)
in den Basiszonen (28, 30) des ersten und des zweiten bipolaren
Bauelements;
– Abscheidung
einer Basisschicht (32) auf der Gate-Leiterschicht (26) und auf
der freigelegten Halbleiterschicht (14) in den Basiszonen (28, 30)
des ersten und des zweiten bipolaren Bauelements;
– Abscheidung
einer Isolierschicht (36) über
der Basisschicht (32);
– Bildung
einer Photoresistschicht (38) und Definition von Emitterzonen (40,
42) des ersten und des zweiten bipolaren Bauelements;
– Entfernen
der Photoresistschicht (38) in den Emitterzonen...A method of fabricating a BiCMOS device comprising a first bipolar device and a second bipolar device of the same doping type, the method comprising the steps of:
Depositing a dielectric layer (24) over a semiconductor layer (14);
Depositing a gate conductor layer (26) over the dielectric layer (24);
- Definition of base zones (28, 30) of the first and the second bipolar device;
Removing the gate conductor layer (26) and the dielectric layer (24) in the base regions (28, 30) of the first and second bipolar devices;
Depositing a base layer (32) on the gate conductor layer (26) and on the exposed semiconductor layer (14) in the base regions (28, 30) of the first and second bipolar devices;
- depositing an insulating layer (36) over the base layer (32);
- forming a photoresist layer (38) and defining emitter regions (40, 42) of the first and second bipolar devices;
Removing the photoresist layer (38) in the emitter zones ...
Description
Die vorliegende Erfindung betrifft ein Verfahren zur Herstellung eines BiCMOS-Bauelements, umfassend ein erstes bipolares Bauelement und ein zweites bipolares Bauelement desselben Dotierungstyps.The The present invention relates to a process for producing a BiCMOS device comprising a first bipolar device and a second bipolar device of the same doping type.
In rauschempfindlichen analogen Anwendungen für hohe Qualitätsansprüche werden typischerweise bipolare Transistoren mit einem Verstärkungsfaktor nahe 1000 benötigt, um bei einem bestimmten Kollektorstrom den Basisstrom und somit das Rauschen zu verringern. Eigenständige monolithische, bipolare Transistoren mit einem Verstärkungsfaktor nahe 1000 sind aus dem Stand der Technik bekannt. Die Komplexität der Integration eines solchen bipolaren Super-Beta-Transistors in einen herkömmlichen BiCMOS-Fertigungsfluss ist prohibitiv, und die Herstellungskosten würden dadurch übermäßig steigen.In noise-sensitive analog applications for high quality standards typically bipolar transistors with a gain factor needed near 1000, at a certain collector current the base current and thus the Reduce noise. independent monolithic, bipolar transistors with a gain factor near 1000 are known in the art. The complexity of integration such a bipolar super-beta transistor in a conventional BiCMOS manufacturing flow is prohibitive, and manufacturing costs would thereby increase excessively.
Aus
der
Aus
der
In
der
In dem Artikel „SiGe BiCMOS Technology for Communication Products" (Racanelli, Kempf; Proceedings of the 2003 Custom Integrated Circuits Conference, 2003, S. 331-334) ist ein BiCMOS-Bauelement mit einem 200 GHz SiGe-Bipolartransistor und einem 0,13 μm CMOS-Transistor gezeigt. Das Verfahren zur Herstellung dieses BiCMOS-Bauelements ist im Prozeßablauf und in der Architektur gleich einem bekannten Verfahren zur Herstellung eines BiCMOS-Bauelements mit SiGe-Bipolartransistor und einem 0,35 μm, 0,25 μm oder 0,18 μm CMOS-Transistor, es wurde lediglich die Abscheidetemperatur von SiGe begrenzt und die Implantationsparameter wurden optimiert.In the article "SiGe BiCMOS Technology for Communication Products "(Racanelli, Kempf; Proceedings of the 2003 Custom Integrated Circuits Conference, 2003, pp. 331-334) a BiCMOS device with a 200 GHz SiGe bipolar transistor and a 0.13 μm CMOS transistor shown. The method of making this BiCMOS device is in the process flow and in architecture similar to a known method of manufacture a BiCMOS device with SiGe bipolar transistor and a 0.35 μm, 0.25 μm or 0.18 μm CMOS transistor, only the deposition temperature of SiGe was limited and the implantation parameters were optimized.
Die vorliegende Erfindung stellt ein Verfahren zur Integration eines bipolaren Super-Beta-Transistors in einen bestehenden BiCMOS-Fertigungsfluss mit minimal höherer Komplexität bereit.The The present invention provides a method for integrating a bipolar super-beta transistor into an existing BiCMOS manufacturing flow with slightly higher complexity ready.
Das Verfahren gemäß der vorliegenden Erfindung umfaßt die Schritte der Abscheidung einer dielektrischen Schicht über einer Halbleiterschicht, der Abscheidung einer Gate-Leiterschicht über der dielektrischen Schicht, der Definition von Basiszonen des ersten und des zweiten bipolaren Bauelements, des Entfernens der Gate-Leiterschicht und der dielektrischen Schicht in den Basiszonen des ersten und des zweiten bipolaren Bauelements, der Abscheidung einer Basisschicht auf der Gate-Leiterschicht und auf der freigelegten Halbleiterschicht in den Basiszonen des ersten und des zweiten bipolaren Bauelements, der Abscheidung einer Isolierschicht über der Basisschicht, der Bildung einer Photoresistschicht und der Definition von Emitterzonen des ersten und des zweiten bipolaren Bauelements, des Entfernens der Photoresistschicht in den Emitterzonen des ersten und des zweiten bipolaren Bauelements, wodurch zwei Emitterfenster gebildet werden, der Maskierung des Emitterfensters des ersten bipolaren Bauelements und der Behandlung der Basisschicht in der Basiszone des zweiten bipolaren Bauelements mit einem zusätzlichen Emitterimplantat durch das zugehörige Emitterfenster. Da die Basisstrukturierung und die Basisabscheidung des ersten und des zweiten bipolaren Bauelements in demselben Prozessschritt stattfinden, erfordert das Verfahren gemäß der vorliegenden Erfindung lediglich einen zusätzlichen Maskierungsschritt für die selektive Implantation der Basiszone des zweiten bipolaren Transistors durch das zugehörige Emitterfenster. Die zusätzliche Implantation verursacht, dass der Emitter-Basis-Übergang tiefer in die SiGe-Zone verschoben wird, so dass die Ge-Konzentration an dem Emitter-Basis-Übergang im Vergleich zu der Ge-Konzentration an dem Emitter-Basis-Übergang ohne zusätzliche Implantation erhöht wird. Die Konzentration von Ge an dem Emitter-Basis-Übergang ist entscheidend für den Verstärkungsfaktor des bipolaren Transistors. Eine Erhöhung der Ge-Konzentration an dem Übergang durch die zusätzliche Implantation führt zu einem bipolaren Transistor mit erhöhtem Verstärkungsfaktor. Des Weiteren hat die zusätzliche Implantation den Effekt, dass der Basisdotierstoff nahe seiner Höchstkonzentration durch den implantierten Dotierstoff kompensiert wird, wodurch die Gummelzahl, die ungefähr gleich der Anzahl von Majoritätsladungsträgern pro Einheitsfläche in der Basis ist, verringert wird. Eine verringerte Gummelzahl führt ebenfalls zu einem erhöhten Verstärkungsfaktor. Auf diese Weise kann man bipolare Transistoren mit einem Mindestverstärkungsfaktor von 1000 erhalten.The Method according to the present invention Invention the steps of depositing a dielectric layer over one Semiconductor layer, the deposition of a gate conductor layer over the dielectric layer, the definition of base zones of the first and the second bipolar device, removing the gate conductor layer and the dielectric layer in the base zones of the first and the second second bipolar device, the deposition of a base layer on the gate conductor layer and on the exposed semiconductor layer in the base zones of the first and second bipolar devices, the deposition of an insulating layer over the base layer, the formation a photoresist layer and the definition of emitter zones of the first and second bipolar device, removing the Photoresist layer in the emitter zones of the first and second bipolar device, whereby two emitter windows are formed, the masking of the emitter window of the first bipolar device and the treatment of the base layer in the base zone of the second bipolar device with an additional emitter implant through the associated Emitter window. Because the basic structuring and the base separation of the first and second bipolar devices in the same process step take place, requires the method according to the present invention just an extra Masking step for the selective implantation of the base region of the second bipolar transistor through the associated Emitter window. The additional Implantation causes the emitter-base junction deeper into the SiGe zone is shifted so that the Ge concentration at the emitter-base junction compared to the Ge concentration at the emitter-base junction without additional Implantation increased becomes. The concentration of Ge at the emitter-base junction is crucial for the amplification factor of the bipolar transistor. An increase in the Ge concentration the transition through the additional Implantation leads to a bipolar transistor with increased gain. Furthermore has the extra Implantation the effect that the basic dopant near its maximum concentration is compensated by the implanted dopant, whereby the Gummelzahl, about equal to the number of majority carriers per unit area in the base is reduced. A reduced Gummelzahl leads as well to an increased Gain. In this way one can use bipolar transistors with a minimum amplification factor received from 1000.
Ein nicht zur Erfindung gehörendes Verfahren umfaßt die Schritte der Abscheidung einer dielektrischen Schicht über einer Halbleiterschicht, der Abscheidung einer Gate-Leiterschicht über der dielektrischen Schicht, der Definition einer Basiszone des ersten bipolaren Bauelements, des Entfernens der Gate-Leiterschicht und der dielektrischen Schicht in der Basiszone des ersten bipolaren Bauelements, der Abscheidung einer Basisschicht auf der Gate-Leiterschicht und auf der Halbleiterschicht in der Basiszone des ersten bipolaren Bauelements, der Definition einer Basiszone des zweiten bipolaren Bauelements, des Entfernens der Basisschicht, der Gate-Leiterschicht und der dielektrischen Schicht in der Basiszone des zweiten bipolaren Bauelements, der Abscheidung einer Basisschicht in der Basiszone des zweiten bipolaren Bauelements, wobei die Basisschichten des ersten und des zweiten bipolaren Bauelements in situ während der Abscheidung dotiert werden, um verschiedene Dotierungsprofile zu erhalten. Da die Basisschichten des ersten und des zweiten bipolaren Bauelements separat abgeschieden werden, können die Dotierungsprofile der beiden bipolaren Bauelemente unabhängig voneinander gebildet werden. In dieser Variante erfordert die Integration eines bipolaren Super-Beta-Transistors in den gegenwärtigen BiCMOS-Fertigungsfluss eine separate Basisstrukturierung und -abscheidung und einen zusätzlichen selektiv implantierten Kollektor (SIC).A method not belonging to the invention comprises the steps of depositing a dielectric layer over a semiconductor layer, the Ab depositing a gate conductor layer over the dielectric layer, defining a base region of the first bipolar device, removing the gate conductor layer and the dielectric layer in the base region of the first bipolar device, depositing a base layer on the gate conductor layer, and on the semiconductor layer in the base region of the first bipolar device, defining a base region of the second bipolar device, removing the base layer, the gate conductor layer and the dielectric layer in the base region of the second bipolar device, depositing a base layer in the base region of the second bipolar device, wherein the base layers of the first and second bipolar devices are doped in situ during deposition to obtain different doping profiles. Since the base layers of the first and second bipolar devices are deposited separately, the doping profiles of the two bipolar devices can be formed independently of each other. In this variant, the integration of a bipolar super-beta transistor into the current BiCMOS manufacturing flow requires separate base patterning and deposition and an additional selectively implanted collector (SIC).
In der bevorzugten Ausführungsform sind die Basisschichten Silizium-Germanium-Schichten. Um ein bipolares Bauelement mit erhöhtem Verstärkungsfaktor zu erhalten, wird die Basisschicht des zweiten bipolaren Transistors in situ dotiert, um an dem Emitter-Basis-Übergang eine höhere Germaniumkonzentration zu erhalten als die Basisschicht des ersten bipolaren Transistors an ihrem Emitter-Basis-Übergang aufweist.In the preferred embodiment the base layers are silicon germanium layers. To obtain a bipolar device with increased gain, is the base layer of the second bipolar transistor is doped in situ, around at the emitter-base junction a higher one Germanium concentration to be obtained as the base layer of the first bipolar transistor has at its emitter-base junction.
Weitere Merkmale und Vorteile der Erfindung ergeben sich aus der folgenden Beschreibung bevorzugter Ausführungsformen in Übereinstimmung mit der vorliegenden Erfindung und unter Bezugnahme auf die Zeichnungen, in denen:Further Features and advantages of the invention will become apparent from the following Description of preferred embodiments in accordance with the present invention and with reference to the drawings, in which:
Eine
dünne dielektrische
Schicht
Während der
Abscheidung wird die Basisschicht
Über der
Grenzflächen-Oxidschicht
Nach
der zusätzlichen
Implantation wird das Emitterfenster
Erst
nach der Bildung der Basisschicht
In
der bevorzugten Ausführungsform
der Variante ist die Basisschicht
Während sich die obigen Ausführungsformen hauptsächlich auf NPN-Transistoren beziehen, sollte angemerkt werden, dass ähnliche Techniken verwendet werden können, um wahlweise den Verstärkungsfaktor eines PNP-Transistors zu erhöhen, da ein höherer Ge-Gehalt an dem Emitter-Basis-Übergang ebenfalls zu einem höheren Kollektorstrom in einem PNP-Transistor führt.While the above embodiments mainly on NPN transistors It should be noted that similar techniques are used can be to optionally the amplification factor a PNP transistor to raise, there a higher one Ge content at the emitter-base junction also to a higher one Collector current in a PNP transistor leads.
Claims (8)
Priority Applications (2)
Application Number | Priority Date | Filing Date | Title |
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DE200610004796 DE102006004796B4 (en) | 2006-02-02 | 2006-02-02 | A method of fabricating a BiCMOS device comprising a first bipolar device and a second bipolar device of the same doping type |
US11/670,729 US8450179B2 (en) | 2006-02-02 | 2007-02-02 | Semiconductor device having a first bipolar device and a second bipolar device and method for fabrication |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
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DE200610004796 DE102006004796B4 (en) | 2006-02-02 | 2006-02-02 | A method of fabricating a BiCMOS device comprising a first bipolar device and a second bipolar device of the same doping type |
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DE102006004796A1 DE102006004796A1 (en) | 2007-08-16 |
DE102006004796B4 true DE102006004796B4 (en) | 2008-01-03 |
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Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5856695A (en) * | 1991-10-30 | 1999-01-05 | Harris Corporation | BiCMOS devices |
US6472288B2 (en) * | 2000-12-08 | 2002-10-29 | International Business Machines Corporation | Method of fabricating bipolar transistors with independent impurity profile on the same chip |
US6531369B1 (en) * | 2000-03-01 | 2003-03-11 | Applied Micro Circuits Corporation | Heterojunction bipolar transistor (HBT) fabrication using a selectively deposited silicon germanium (SiGe) |
-
2006
- 2006-02-02 DE DE200610004796 patent/DE102006004796B4/en not_active Expired - Fee Related
Patent Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5856695A (en) * | 1991-10-30 | 1999-01-05 | Harris Corporation | BiCMOS devices |
US6531369B1 (en) * | 2000-03-01 | 2003-03-11 | Applied Micro Circuits Corporation | Heterojunction bipolar transistor (HBT) fabrication using a selectively deposited silicon germanium (SiGe) |
US6472288B2 (en) * | 2000-12-08 | 2002-10-29 | International Business Machines Corporation | Method of fabricating bipolar transistors with independent impurity profile on the same chip |
Non-Patent Citations (1)
Title |
---|
RACANELLI, M., KEMPF, P.: SiGe BiCMOS Technology for Communication Products, In: Proceedings of the 2003 Custom Integrated Circuits Conference, 2003, S. 331-334 * |
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