DE19845790A1 - Wet chemically thinning silicon layers in an active emitter region, especially of a high speed bipolar transistor, using an etch stop layer formed by atomic layer doping of a cover layer - Google Patents
Wet chemically thinning silicon layers in an active emitter region, especially of a high speed bipolar transistor, using an etch stop layer formed by atomic layer doping of a cover layerInfo
- Publication number
- DE19845790A1 DE19845790A1 DE1998145790 DE19845790A DE19845790A1 DE 19845790 A1 DE19845790 A1 DE 19845790A1 DE 1998145790 DE1998145790 DE 1998145790 DE 19845790 A DE19845790 A DE 19845790A DE 19845790 A1 DE19845790 A1 DE 19845790A1
- Authority
- DE
- Germany
- Prior art keywords
- layer
- etch stop
- bipolar transistor
- emitter region
- doping
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 title claims abstract description 12
- 229910052710 silicon Inorganic materials 0.000 title claims abstract description 12
- 239000010703 silicon Substances 0.000 title claims abstract description 12
- 239000000126 substance Substances 0.000 claims abstract description 14
- 238000000034 method Methods 0.000 claims abstract description 11
- 239000010410 layer Substances 0.000 claims description 70
- 239000002019 doping agent Substances 0.000 claims description 12
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 5
- 239000002356 single layer Substances 0.000 claims description 4
- 238000005530 etching Methods 0.000 claims description 3
- 229910021419 crystalline silicon Inorganic materials 0.000 claims description 2
- 229910021421 monocrystalline silicon Inorganic materials 0.000 claims 1
- 238000011065 in-situ storage Methods 0.000 description 5
- 238000004519 manufacturing process Methods 0.000 description 4
- 238000009413 insulation Methods 0.000 description 3
- 229920005591 polysilicon Polymers 0.000 description 3
- 238000003631 wet chemical etching Methods 0.000 description 3
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 2
- 229910052796 boron Inorganic materials 0.000 description 2
- 239000003795 chemical substances by application Substances 0.000 description 2
- 239000013078 crystal Substances 0.000 description 2
- 238000000151 deposition Methods 0.000 description 2
- 230000008021 deposition Effects 0.000 description 2
- 238000000407 epitaxy Methods 0.000 description 2
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 description 1
- 238000005299 abrasion Methods 0.000 description 1
- 230000003321 amplification Effects 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 229910052799 carbon Inorganic materials 0.000 description 1
- 229910052729 chemical element Inorganic materials 0.000 description 1
- 230000002349 favourable effect Effects 0.000 description 1
- 229910052732 germanium Inorganic materials 0.000 description 1
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000003199 nucleic acid amplification method Methods 0.000 description 1
- 230000001681 protective effect Effects 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 125000006850 spacer group Chemical group 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66234—Bipolar junction transistors [BJT]
- H01L29/66242—Heterojunction transistors [HBT]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
- H01L21/30604—Chemical etching
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Chemical & Material Sciences (AREA)
- General Chemical & Material Sciences (AREA)
- Chemical Kinetics & Catalysis (AREA)
- Ceramic Engineering (AREA)
- Bipolar Transistors (AREA)
Abstract
Description
Die Erfindung bezieht sich auf ein Verfahren zur naßchemischen Abdünnung von Si-Schichten im aktiven Emittergebiet eines Bipolartransistors.The invention relates to a method for the wet chemical thinning of Si layers in the active emitter region of a bipolar transistor.
Mit Hilfe epitaktischer Prozesse zur Erzeugung der Basis und des Basisanschlusses lassen sich die Hochgeschwindigkeitseigenschaften von Bipolartransistoren weiter verbessern. Dabei wird die Möglichkeit der insitu-Dotierung genutzt, um geringere Basisweiten und -schichtwiderstände zu realisieren. Günstig auf die Einstellung von Basisschichtwiderstand und Stromverstärkung wirkt sich bekanntermaßen die Abscheidung von Heteroschichten aus.Leave with the help of epitaxial processes to create the base and the base connection the high-speed properties of bipolar transistors continue to improve. Here the possibility of in situ doping is used to reduce the base width and realizing film resistors. Favorable on the setting of base layer resistance and current amplification is known to affect the deposition of heterolayers.
In einer speziellen Einfach-Polysilizium-Technologie mit Ätzstoppschicht wurde das Verfahren der differentiellen Epitaxie zur Erzeugung epitaktischer Basisschichten verwendet. Differentielle Epitaxie bedeutet, daß epitaktisches Wachstum sowohl auf Halbleiter- als auch auf Isolatorgebieten stattfindet. So können gleichzeitig die innere Basis und der Basisanschluß auf dem Isolatorgebiet entstehen. Nachteilig dabei ist, daß die Dicke der Epitaxieschicht der inneren Basis nicht unabhängig von der des Basisanschlusses auf dem Isolatorgebiet eingestellt werden kann. In Bezug auf Hochgeschwindigkeitsanwendungen wäre es von Vorteil, im Bereich des aktiven Basis-Emitter-Überganges eine hinreichend geringe Epitaxieschichtdicke zwischen Emitter und Basis, im äußeren Basisgebiet zur Realisierung von möglichst geringen Basisanschluß-Widerständen eine dickere Epitaxieschicht zu realisieren.This was done in a special single polysilicon technology with an etch stop layer Differential epitaxy method is used to create epitaxial base layers. Differential epitaxy means that epitaxial growth on both semiconductor and takes place in isolator areas. So the inner base and the base connection can be used at the same time arise in the isolator area. The disadvantage here is that the thickness of the epitaxial layer inner base is not independent of that of the base connection in the isolator area can be adjusted. In terms of high speed applications, it would be of Advantage, a sufficiently low one in the area of the active base-emitter junction Epitaxial layer thickness between emitter and base, in the outer base area for realization a thicker epitaxial layer from the lowest possible base connection resistances realize.
Aufgabe der Erfindung ist es, ein Verfahren zur naßchemischen Abdünnung der epitaktischen Siliziumschicht im aktiven Emittergebiet eines Bipolartransistors vorzuschlagen, das die Hochgeschwindigkeitseigenschaften des Bipolartransisors verbessert und insbesondere im Bereich des aktiven Basis-Emitter-Übergangs eine hinreichend geringe Epitaxieschichtdicke zwischen Emitter und Basis und im äußeren Basisgebiet zur Realisierung von möglichst geringen Basisanschluß-Widerständen eine dickere Epitaxieschicht ermöglicht.The object of the invention is to provide a method for wet chemical thinning of the epitaxial Propose silicon layer in the active emitter region of a bipolar transistor that the High-speed properties of the bipolar transistor improved and especially in A sufficiently small epitaxial layer thickness in the area of the active base-emitter junction between emitter and base and in the outer base area to realize as possible low base connection resistances allows a thicker epitaxial layer.
Zur Realisierung dieser gegensätzlichen Anforderungen an die Epitaxieschichtdicke wird die Epitaxieschichtdicke über der Basis, bekannt als Deckeldicke, generell erhöht und innerhalb des aktiven Emitterbereiches nachträglich mittels geeigneter Verfahren, wie z. B. naßchemischem Rückätzen, reduziert.To meet these conflicting requirements for the epitaxial layer thickness, the Epitaxial layer thickness above the base, known as the lid thickness, generally increased and within the active emitter region subsequently using suitable methods, such as. B. wet chemical etching, reduced.
Erfindungsgemäß wird diese Aufgabe durch eine naßchemische Oberflächenrelief-Erzeugung im Bereich des aktiven Emitters gelöst.According to the invention, this object is achieved by generating a wet chemical surface relief solved in the area of the active emitter.
Um definierte Silizium-Abträge im Bereich des aktiven Emitters zu erzielen, ist es zweckmäßig, eine zusätzliche in-situ Dotierung epitaktisch in der Deckelschicht über der abgeschiedenen Basis zu realisieren. Diese in-situ Dotierungen dienen als Ätzstoppschichten, die es ermöglichen, gut reproduzierbar mit bekannten naßchemischen Ätzmitteln definiert Silizium abzutragen.It is to achieve defined silicon abrasion in the area of the active emitter expedient, an additional in-situ doping epitaxially in the cover layer over the to realize secluded base. These in-situ dopings serve as etch stop layers which allow defined, reproducible with known wet chemical etchants Remove silicon.
Als Dotanden werden verschiedene chemische Elemente wie Bor, Germanium oder Kohlenstoff eingesetzt, die einen Ätzstopp bewirken. Various chemical elements such as boron, germanium or Carbon used, which cause an etch stop.
Bei Verwendung von Bor als Ätzstopp- bzw. Dotandenschicht liegt es im Bereich der Erfindung, zwischen hochdotierter Ätzstopp- bzw. Dotandenschicht und Deckelschicht einerseits und der Emitterdotierung andererseits einen Inside-Poly-Silizium-Spacer zu bilden, um einen ausreichenden seitlichen Abstand zwischen diesen unterschiedlichen Dotierungen zu realisieren.When using boron as an etch stop or dopant layer, it is in the range of Invention, between highly doped etch stop or dopant layer and cover layer on the one hand and the emitter doping on the other to form an inside poly silicon spacer, to a sufficient lateral distance between these different dopings realize.
Als Verfahren zur Erzeugung der Ätzstoppschicht wurde das "Atomic Layer Doping", im folgenden als ALD bezeichnet, angewandt. Beim Atomic Layer Doping wird die Dosierung und die vertikale Positionierung der Dotierstoffschicht mit Atomlagengenauigkeit eingestellt.The "Atomic Layer Doping", in hereinafter referred to as ALD applied. With atomic layer doping, the dosage and the vertical positioning of the dopant layer is adjusted with atomic position accuracy.
Diese Atomlagengenauigkeit der Einbringung der Dotierung als Ätzstoppschicht bietet den Vorteil, die Dicke der zu ätzenden Emitterschicht mit Atomlagengenauigkeit einzustellen. Erfindungsgemäß wird die Atomlagendotierung während der Abscheidung der Emitterschicht eingebracht.This atomic position accuracy of the introduction of the doping as an etch stop layer offers the Advantage to set the thickness of the emitter layer to be etched with atomic position accuracy. According to the invention, the atomic layer doping during the deposition of the emitter layer brought in.
Die Merkmale der Erfindung gehen außer aus den Ansprüchen auch aus der Beschreibung und aus den Zeichnungen hervor, wobei die einzelnen Merkmale jeweils für sich allein oder zu mehreren in Form von Unterkombinationen schutzfähige Ausführungen darstellen, für die hier Schutz beansprucht wird. Ausführungsbeispiele der Erfindung sind in den Zeichnungen dargestellt und werden im folgenden näher erläutert.The features of the invention go beyond the claims also from the description and from the drawings, the individual features each individually or to represent several protective designs in the form of sub-combinations, for the here Protection is claimed. Embodiments of the invention are in the drawings shown and are explained in more detail below.
Die Zeichnungen zeigen:The drawings show:
Fig. 1 Schematische Darstellung eines Bipolartransistors während der Herstellung Vers. a, Fig. 1 shows a schematic representation of a bipolar transistor during manufacture Vers. A,
Fig. 2 Schematische Darstellung eines Bipolartransistors während der Herstellung Vers. b. Fig. 2 Schematic representation of a bipolar transistor during the manufacture Vers. B.
Die Erfindung wird nun am Beispiel der Herstellung eines Bipolartransistors beschrieben.The invention will now be described using the example of the production of a bipolar transistor.
Fig. 1 zeigt die Realisierung der naßchemischen Abdünnung der Silizium-Deckelschicht 3 + 9 im aktiven Emittergebiet 7 eines Bipolartransistors mit Basisanschluß auf dem Feldisolationsgebiet. Fig. 1 shows the implementation of the wet chemical thinning of the silicon cover layer 3 + 9 in the active emitter region 7 of a bipolar transistor base terminal in the field isolation region.
Eine Epitaxieschichtfolge, bestehend aus Pufferschicht 1, in-situ dotierter Basisschicht 2 und Deckelschicht 3 + 9, in der sich eine Ätzstoppschicht 5 befindet, bedeckt das Gebiet des zukünftigen Emitters als einkristalliner Schichtstapel 1; 2; 3; 5; 9 und einen Teil des Feldisolationsgebietes 6 als polykristalliner Schichtstapel 1/1; 2/1; 3/1; 5/1; 9/1. Die strukturierte Epitaxieschicht ist mit einem Dielektrikum 4 bedeckt, das nur im Bereich des aktiven Emittergebietes 7 entfernt wurde. Die Dotierungsdosis der Ätzstoppschicht 5 im Deckel, erzeugt mittels ALD, ist kleiner als eine Monolage des jeweiligen Dotanden, so daß die darüberliegende Deckelschicht 9 einkristallin gewachsen ist.An epitaxial layer sequence, consisting of buffer layer 1 , in-situ doped base layer 2 and cover layer 3 + 9 , in which there is an etch stop layer 5 , covers the area of the future emitter as a single-crystal layer stack 1 ; 2 ; 3 ; 5 ; 9 and a portion of the field insulation region 6 a polycrystalline layer stack 1/1; 2/1; 3/1; 5/1; 9/1. The structured epitaxial layer is covered with a dielectric 4 , which was only removed in the area of the active emitter region 7 . The doping dose of the etch stop layer 5 in the cover, generated by means of ALD, is smaller than a monolayer of the respective dopant, so that the cover layer 9 lying above it has grown single-crystal.
Mit Hilfe bekannter naßchemischer Ätzmittel, die Silizium hochselektiv zum Dielektrikum 4 und zur Ätzstoppschicht 5 abtragen, wird im aktiven Emittergebiet die Deckelschicht teilweise entfernt. Mittels ebenfalls bekannter naßchemischer Ätzmittel kann die Ätzstoppschicht 5 entfernt werden.With the help of known wet chemical etchants, which remove silicon highly selectively with respect to the dielectric 4 and the etch stop layer 5 , the cover layer is partially removed in the active emitter region. The etching stop layer 5 can be removed by means of likewise known wet chemical etching agents.
Fig. 2 zeigt eine weitere Variante der naßchemischen Abdünnung der Silizium- Deckelschicht 3 + 8 im aktiven Emittergebiet 7 eines Bipolartransistors mit Basisanschluß auf dem Feldisolationsgebiet 6. Fig. 2 shows a further variant of the wet-chemical thinning of the silicon cover layer 3 + 8 in the active emitter region 7 of a bipolar transistor base terminal in the field insulation region 6.
Eine Epitaxieschichtfolge, bestehend aus Pufferschicht 1, in-situ dotierter Basisschicht 2 und Deckelschicht 3, in der sich eine Dotandenschicht 10 befindet, die aufgrund der Art ihrer Erzeugung bewirkt, daß die Deckelschicht 8 nach Bildung der Dotandenschicht 10 polykristallin weiterwächst, bedeckt das Gebiet des zukünftigen Emitters und einen Teil des Feldisolationsgebietes 6 als polykristalliner Schichtstapel 1/1; 2/1; 3/1; 10/1; 8/1. Die strukturierte Epitaxieschicht ist mit einem Dielektrikum 4 bedeckt, das nur im Bereich des aktiven Emittergebietes 7 entfernt wurde. Die Dotierungsdosis der Dotandenschicht 10 im Deckel, erzeugt mittels ALD, ist größer als eine Monolage des jeweiligen Dotanden mit einer Dicke kleiner als 3 nm, so daß die darüberliegende Deckelschicht 8 polykristallin wächst.An epitaxial layer sequence, consisting of buffer layer 1 , in-situ doped base layer 2 and cover layer 3 , in which there is a dopant layer 10 which, due to the nature of its production, causes the cover layer 8 to continue growing polycrystalline after the formation of the dopant layer 10 , covers the area of future emitter and a portion of the field insulation region 6 a polycrystalline layer stack 1/1; 2/1; 3/1; 10/1; 8/1. The structured epitaxial layer is covered with a dielectric 4 , which was only removed in the area of the active emitter region 7 . The doping dose of the dopant layer 10 in the cover, produced by means of ALD, is greater than a monolayer of the respective dopant with a thickness of less than 3 nm, so that the cover layer 8 lying above it grows polycrystalline.
Mit Hilfe bekannter naßchemischer Ätzmittel, die Poly-Silizium hochselektiv zum Dielektrikum 4 und zum kristallinen Silizium 3 abtragen, wird im aktiven Emittergebiet 7 der polykristalline Teil der Deckelschicht 8 inklusive Dotandenschicht 10 entfernt.The polycrystalline part of the cover layer 8, including the dopant layer 10 , is removed in the active emitter region 7 with the aid of known wet chemical etching agents which remove polysilicon highly selectively with respect to the dielectric 4 and the crystalline silicon 3 .
In der vorliegenden Erfindung wurde anhand konkreter Ausführungsbeispiele ein Verfahren zur naßchemischen Abdünnung von Si-Schichten im aktiven Emittergebiet eines Bipolartransistors erläutert. Es sei aber vermerkt, daß die vorliegende Erfindung nicht auf die Einzelheiten der Beschreibung in den Ausführungsbeispielen eingeschränkt ist, da im Rahmen der Patentansprüche Änderungen und Abwandlungen beansprucht werden.In the present invention, a method was based on specific exemplary embodiments for wet chemical thinning of Si layers in the active emitter region of a Bipolar transistor explained. However, it should be noted that the present invention is not limited to Details of the description in the exemplary embodiments are limited, since within the scope changes and modifications are claimed.
Claims (4)
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| DE1998145790 DE19845790B4 (en) | 1998-09-21 | 1998-09-21 | Process for the wet-chemical thinning of Si layers in the active emitter region of a bipolar transistor |
| PCT/DE1999/003068 WO2000017922A1 (en) | 1998-09-21 | 1999-09-20 | METHOD FOR THE WET-CHEMICAL THINNING OF Si-LAYERS IN THE ACTIVE EMITTER REGION OF A BIPOLAR TRANSISTOR |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| DE1998145790 DE19845790B4 (en) | 1998-09-21 | 1998-09-21 | Process for the wet-chemical thinning of Si layers in the active emitter region of a bipolar transistor |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| DE19845790A1 true DE19845790A1 (en) | 2000-03-23 |
| DE19845790B4 DE19845790B4 (en) | 2008-12-04 |
Family
ID=7883442
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| DE1998145790 Expired - Fee Related DE19845790B4 (en) | 1998-09-21 | 1998-09-21 | Process for the wet-chemical thinning of Si layers in the active emitter region of a bipolar transistor |
Country Status (2)
| Country | Link |
|---|---|
| DE (1) | DE19845790B4 (en) |
| WO (1) | WO2000017922A1 (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP1657745A1 (en) * | 2004-11-16 | 2006-05-17 | ATMEL Germany GmbH | Integrated circuit and method of manufacturing an integrated circuit on a semiconductive substrate |
| DE102004053393B4 (en) * | 2004-11-05 | 2007-01-11 | Atmel Germany Gmbh | Method for producing a vertically integrated cascode structure and vertically integrated cascode structure |
| US7601584B2 (en) | 2004-11-05 | 2009-10-13 | Atmel Germany Gmbh | Semiconductor array and method for manufacturing a semiconductor array |
Citations (14)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0372476A2 (en) * | 1988-12-05 | 1990-06-13 | Nec Corporation | Semiconductor device having a reduced parasitic capacitance and manufacturing method thereof |
| EP0382947A1 (en) * | 1989-02-13 | 1990-08-22 | International Business Machines Corporation | Bipolar transistor and method of fabricating same |
| US5198372A (en) * | 1986-01-30 | 1993-03-30 | Texas Instruments Incorporated | Method for making a shallow junction bipolar transistor and transistor formed thereby |
| US5296389A (en) * | 1990-02-19 | 1994-03-22 | Nec Corporation | Method of fabricating a heterojunction bipolar transistor |
| US5362658A (en) * | 1992-10-14 | 1994-11-08 | Mitsubishi Denki Kabushiki Kaisha | Method for producing semiconductor device |
| US5569944A (en) * | 1992-05-29 | 1996-10-29 | Texas Instruments Incorporated | Compound semiconductor heterojunction bipolar transistor |
| US5593905A (en) * | 1995-02-23 | 1997-01-14 | Texas Instruments Incorporated | Method of forming stacked barrier-diffusion source and etch stop for double polysilicon BJT with patterned base link |
| EP0762489A2 (en) * | 1995-09-12 | 1997-03-12 | Daimler-Benz Aktiengesellschaft | Method for fabricating a heterojunction bipolar transistor |
| US5640025A (en) * | 1995-12-01 | 1997-06-17 | Motorola | High frequency semiconductor transistor |
| WO1997024757A1 (en) * | 1995-12-28 | 1997-07-10 | Philips Electronics N.V. | A method of manufacturing a self-aligned vertical bipolar transistor on an soi |
| US5648294A (en) * | 1989-11-29 | 1997-07-15 | Texas Instruments Incorp. | Integrated circuit and method |
| DE3915634C2 (en) * | 1988-05-16 | 1997-09-11 | Toshiba Kawasaki Kk | Method for producing a bipolar transistor with a miniaturized emitter layer |
| EP0795899A1 (en) * | 1996-03-14 | 1997-09-17 | Daimler-Benz Aktiengesellschaft | Method for fabricating a heterojunction bipolar transistor |
| US5773350A (en) * | 1997-01-28 | 1998-06-30 | National Semiconductor Corporation | Method for forming a self-aligned bipolar junction transistor with silicide extrinsic base contacts and selective epitaxial grown intrinsic base |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| DE69107779T2 (en) * | 1990-10-31 | 1995-09-21 | Ibm | Transistor with self-adjusting epitaxial base and its manufacturing process. |
-
1998
- 1998-09-21 DE DE1998145790 patent/DE19845790B4/en not_active Expired - Fee Related
-
1999
- 1999-09-20 WO PCT/DE1999/003068 patent/WO2000017922A1/en active Application Filing
Patent Citations (14)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5198372A (en) * | 1986-01-30 | 1993-03-30 | Texas Instruments Incorporated | Method for making a shallow junction bipolar transistor and transistor formed thereby |
| DE3915634C2 (en) * | 1988-05-16 | 1997-09-11 | Toshiba Kawasaki Kk | Method for producing a bipolar transistor with a miniaturized emitter layer |
| EP0372476A2 (en) * | 1988-12-05 | 1990-06-13 | Nec Corporation | Semiconductor device having a reduced parasitic capacitance and manufacturing method thereof |
| EP0382947A1 (en) * | 1989-02-13 | 1990-08-22 | International Business Machines Corporation | Bipolar transistor and method of fabricating same |
| US5648294A (en) * | 1989-11-29 | 1997-07-15 | Texas Instruments Incorp. | Integrated circuit and method |
| US5296389A (en) * | 1990-02-19 | 1994-03-22 | Nec Corporation | Method of fabricating a heterojunction bipolar transistor |
| US5569944A (en) * | 1992-05-29 | 1996-10-29 | Texas Instruments Incorporated | Compound semiconductor heterojunction bipolar transistor |
| US5362658A (en) * | 1992-10-14 | 1994-11-08 | Mitsubishi Denki Kabushiki Kaisha | Method for producing semiconductor device |
| US5593905A (en) * | 1995-02-23 | 1997-01-14 | Texas Instruments Incorporated | Method of forming stacked barrier-diffusion source and etch stop for double polysilicon BJT with patterned base link |
| EP0762489A2 (en) * | 1995-09-12 | 1997-03-12 | Daimler-Benz Aktiengesellschaft | Method for fabricating a heterojunction bipolar transistor |
| US5640025A (en) * | 1995-12-01 | 1997-06-17 | Motorola | High frequency semiconductor transistor |
| WO1997024757A1 (en) * | 1995-12-28 | 1997-07-10 | Philips Electronics N.V. | A method of manufacturing a self-aligned vertical bipolar transistor on an soi |
| EP0795899A1 (en) * | 1996-03-14 | 1997-09-17 | Daimler-Benz Aktiengesellschaft | Method for fabricating a heterojunction bipolar transistor |
| US5773350A (en) * | 1997-01-28 | 1998-06-30 | National Semiconductor Corporation | Method for forming a self-aligned bipolar junction transistor with silicide extrinsic base contacts and selective epitaxial grown intrinsic base |
Non-Patent Citations (5)
| Title |
|---|
| ENQUIST,Paul M., et.al.: Self-Aligned A1GaAs/ GaAs HBT with Selectively Regrown OMVPE Emitter. In: IEEE Electron Device Letters, Vol.14, No.6, * |
| LEE,J.W., et.al.: Investigation Of Wet Etching Solutions For In¶0.5¶Ga¶0.5¶P. In: Solid-State Electronics, Vol.11, 1995, S.1871-1874 * |
| NGUYEN,Cuong T., et.al.: Application of Selective Epitaxial Silicon and Chemo-Mechanical Polishing to Bipolar Transistors. In: IEEE Transactions On Electron Devices, Vol.41, No.12, Dec. 1994, S.2343-3460 * |
| SATO,Fumihiko, et.al.: A Super Self-Aligned Selectively Grown SiGe Base (SSSB) Bipolar Transistor Fabricated by Cold-Wall Type UHV/CVD Technology. In: IEEE Transactions On Electron Devices, Vol.41, No.8, Aug. 1994, S.1373-1378 * |
| WANG,Feng, et.al.: Highly Selective Chemical Etching of Si vs. Si¶1-x¶Ge¶x¶ Using NH¶4¶OH Solution. In: J. Electrochem. Soc., Vol.144, No.3, March 1997, S.L37 - L39 * |
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| DE19845790B4 (en) | 2008-12-04 |
| WO2000017922A1 (en) | 2000-03-30 |
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