WO2000016407A3 - Geschaltetes netzteil mit reduzierten schaltverlusten - Google Patents

Geschaltetes netzteil mit reduzierten schaltverlusten Download PDF

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Publication number
WO2000016407A3
WO2000016407A3 PCT/DE1999/002874 DE9902874W WO0016407A3 WO 2000016407 A3 WO2000016407 A3 WO 2000016407A3 DE 9902874 W DE9902874 W DE 9902874W WO 0016407 A3 WO0016407 A3 WO 0016407A3
Authority
WO
WIPO (PCT)
Prior art keywords
switching
losses
transistor
switching transistor
reduced
Prior art date
Application number
PCT/DE1999/002874
Other languages
English (en)
French (fr)
Other versions
WO2000016407A2 (de
Inventor
Gerald Deboy
Martin Maerz
Franz Hirler
Hans Weber
Original Assignee
Siemens Ag
Gerald Deboy
Martin Maerz
Franz Hirler
Hans Weber
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Siemens Ag, Gerald Deboy, Martin Maerz, Franz Hirler, Hans Weber filed Critical Siemens Ag
Priority to EP99969183A priority Critical patent/EP1119876A2/de
Priority to JP2000570842A priority patent/JP2002525853A/ja
Publication of WO2000016407A2 publication Critical patent/WO2000016407A2/de
Publication of WO2000016407A3 publication Critical patent/WO2000016407A3/de
Priority to US09/804,325 priority patent/US6388287B2/en
Priority to US10/846,998 priority patent/USRE40352E1/en

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/08Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/0843Source or drain regions of field-effect devices
    • H01L29/0847Source or drain regions of field-effect devices of field-effect transistors with insulated gate
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0607Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
    • H01L29/0611Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
    • H01L29/0615Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
    • H01L29/063Reduced surface field [RESURF] pn-junction structures
    • H01L29/0634Multiple reduced surface field (multi-RESURF) structures, e.g. double RESURF, charge compensation, cool, superjunction (SJ), 3D-RESURF, composite buffer (CB) structures
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/1095Body region, i.e. base region, of DMOS transistors or IGBTs
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76Unipolar devices, e.g. field effect transistors
    • H01L29/772Field effect transistors
    • H01L29/78Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7802Vertical DMOS transistors, i.e. VDMOS transistors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76Unipolar devices, e.g. field effect transistors
    • H01L29/772Field effect transistors
    • H01L29/78Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7816Lateral DMOS transistors, i.e. LDMOS transistors
    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03KPULSE TECHNIQUE
    • H03K17/00Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/08Modifications for protecting switching circuit against overcurrent or overvoltage
    • H03K17/081Modifications for protecting switching circuit against overcurrent or overvoltage without feedback from the output circuit to the control circuit
    • H03K17/0814Modifications for protecting switching circuit against overcurrent or overvoltage without feedback from the output circuit to the control circuit by measures taken in the output circuit
    • H03K17/08142Modifications for protecting switching circuit against overcurrent or overvoltage without feedback from the output circuit to the control circuit by measures taken in the output circuit in field-effect transistor switches

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • General Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Chemical & Material Sciences (AREA)
  • Composite Materials (AREA)
  • Electronic Switches (AREA)
  • Dc-Dc Converters (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)

Abstract

Die Erfindung betrifft einen Schalttransistor mit reduzierten Schaltverlusten. Bei diesem Schalttransistor hat die Ausgangskapazität bei kleinen Drain-Source-Spannungen sehr hohe Werte, wobei diese Kapazität mit steigender Drain-Source-Spannung auf so kleine Werte abfällt, daß die im Transistor gespeicherte Energie sehr niedrige Werte annimmt.
PCT/DE1999/002874 1998-09-11 1999-09-10 Geschaltetes netzteil mit reduzierten schaltverlusten WO2000016407A2 (de)

Priority Applications (4)

Application Number Priority Date Filing Date Title
EP99969183A EP1119876A2 (de) 1998-09-11 1999-09-10 Geschaltetes netzteil mit reduzierten schaltverlusten
JP2000570842A JP2002525853A (ja) 1998-09-11 1999-09-10 低減されたスイッチング損失を有する接続されたパワーパック
US09/804,325 US6388287B2 (en) 1998-09-11 2001-03-12 Switch mode power supply with reduced switching losses
US10/846,998 USRE40352E1 (en) 1998-09-11 2004-05-14 Switch mode power supply with reduced switching losses

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
DE19841754A DE19841754A1 (de) 1998-09-11 1998-09-11 Schalttransistor mit reduzierten Schaltverlusten
DE19841754.3 1998-09-11

Related Child Applications (1)

Application Number Title Priority Date Filing Date
US09/804,325 Continuation US6388287B2 (en) 1998-09-11 2001-03-12 Switch mode power supply with reduced switching losses

Publications (2)

Publication Number Publication Date
WO2000016407A2 WO2000016407A2 (de) 2000-03-23
WO2000016407A3 true WO2000016407A3 (de) 2000-11-09

Family

ID=7880725

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/DE1999/002874 WO2000016407A2 (de) 1998-09-11 1999-09-10 Geschaltetes netzteil mit reduzierten schaltverlusten

Country Status (5)

Country Link
US (2) US6388287B2 (de)
EP (1) EP1119876A2 (de)
JP (1) JP2002525853A (de)
DE (1) DE19841754A1 (de)
WO (1) WO2000016407A2 (de)

Families Citing this family (30)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE19840032C1 (de) * 1998-09-02 1999-11-18 Siemens Ag Halbleiterbauelement und Herstellungsverfahren dazu
US7745289B2 (en) 2000-08-16 2010-06-29 Fairchild Semiconductor Corporation Method of forming a FET having ultra-low on-resistance and low gate charge
US6710403B2 (en) * 2002-07-30 2004-03-23 Fairchild Semiconductor Corporation Dual trench power MOSFET
US6916745B2 (en) 2003-05-20 2005-07-12 Fairchild Semiconductor Corporation Structure and method for forming a trench MOSFET having self-aligned features
US6818513B2 (en) * 2001-01-30 2004-11-16 Fairchild Semiconductor Corporation Method of forming a field effect transistor having a lateral depletion structure
US6713813B2 (en) 2001-01-30 2004-03-30 Fairchild Semiconductor Corporation Field effect transistor having a lateral depletion structure
US6803626B2 (en) 2002-07-18 2004-10-12 Fairchild Semiconductor Corporation Vertical charge control semiconductor device
US6825514B2 (en) * 2001-11-09 2004-11-30 Infineon Technologies Ag High-voltage semiconductor component
US6819089B2 (en) 2001-11-09 2004-11-16 Infineon Technologies Ag Power factor correction circuit with high-voltage semiconductor component
US7576388B1 (en) 2002-10-03 2009-08-18 Fairchild Semiconductor Corporation Trench-gate LDMOS structures
US7033891B2 (en) * 2002-10-03 2006-04-25 Fairchild Semiconductor Corporation Trench gate laterally diffused MOSFET devices and methods for making such devices
US6710418B1 (en) 2002-10-11 2004-03-23 Fairchild Semiconductor Corporation Schottky rectifier with insulation-filled trenches and method of forming the same
US7638841B2 (en) 2003-05-20 2009-12-29 Fairchild Semiconductor Corporation Power semiconductor devices and methods of manufacture
KR100994719B1 (ko) 2003-11-28 2010-11-16 페어차일드코리아반도체 주식회사 슈퍼정션 반도체장치
US7368777B2 (en) 2003-12-30 2008-05-06 Fairchild Semiconductor Corporation Accumulation device with charge balance structure and method of forming the same
JP4832731B2 (ja) 2004-07-07 2011-12-07 株式会社東芝 電力用半導体装置
US7352036B2 (en) 2004-08-03 2008-04-01 Fairchild Semiconductor Corporation Semiconductor power device having a top-side drain using a sinker trench
AT504998A2 (de) 2005-04-06 2008-09-15 Fairchild Semiconductor Trenched-gate-feldeffekttransistoren und verfahren zum bilden derselben
US7319256B1 (en) 2006-06-19 2008-01-15 Fairchild Semiconductor Corporation Shielded gate trench FET with the shield and gate electrodes being connected together
WO2009039441A1 (en) 2007-09-21 2009-03-26 Fairchild Semiconductor Corporation Superjunction structures for power devices and methods of manufacture
US7772668B2 (en) * 2007-12-26 2010-08-10 Fairchild Semiconductor Corporation Shielded gate trench FET with multiple channels
DE102008032876B4 (de) 2008-07-14 2010-04-08 Sew-Eurodrive Gmbh & Co. Kg Verfahren, Schaltungsanordnung und Brückenschaltung
US20120273916A1 (en) 2011-04-27 2012-11-01 Yedinak Joseph A Superjunction Structures for Power Devices and Methods of Manufacture
US8319290B2 (en) 2010-06-18 2012-11-27 Fairchild Semiconductor Corporation Trench MOS barrier schottky rectifier with a planar surface using CMP techniques
US8836028B2 (en) 2011-04-27 2014-09-16 Fairchild Semiconductor Corporation Superjunction structures for power devices and methods of manufacture
US8673700B2 (en) 2011-04-27 2014-03-18 Fairchild Semiconductor Corporation Superjunction structures for power devices and methods of manufacture
US8786010B2 (en) 2011-04-27 2014-07-22 Fairchild Semiconductor Corporation Superjunction structures for power devices and methods of manufacture
US8772868B2 (en) 2011-04-27 2014-07-08 Fairchild Semiconductor Corporation Superjunction structures for power devices and methods of manufacture
US8860136B2 (en) * 2012-12-03 2014-10-14 Infineon Technologies Ag Semiconductor device and method of manufacturing a semiconductor device
US9698768B2 (en) 2015-07-14 2017-07-04 Infineon Technologies Austria Ag System and method for operating a switching transistor

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5216275A (en) * 1991-03-19 1993-06-01 University Of Electronic Science And Technology Of China Semiconductor power devices with alternating conductivity type high-voltage breakdown regions
US5438215A (en) * 1993-03-25 1995-08-01 Siemens Aktiengesellschaft Power MOSFET
DE19702102A1 (de) * 1996-01-22 1997-07-24 Fuji Electric Co Ltd Halbleitervorrichtung und Verfahren zur Herstellung der Halbleitervorrichtung
WO1997029518A1 (de) * 1996-02-05 1997-08-14 Siemens Aktiengesellschaft Durch feldeffekt steuerbares halbleiterbauelement

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS56129423A (en) 1980-03-14 1981-10-09 Sony Corp Triangle wave generating circuit
GB2257830B (en) 1991-07-12 1995-04-05 Matsushita Electric Works Ltd Low output-capacity, double-diffused field effect transistor
IT1272567B (it) * 1992-09-15 1997-06-23 Int Rectifier Corp Dispositivo transistore di potenza, dotato di una regione ultraprofonda a concentrazione maggiorata
JP3808116B2 (ja) * 1995-04-12 2006-08-09 富士電機デバイステクノロジー株式会社 高耐圧ic
US6057558A (en) * 1997-03-05 2000-05-02 Denson Corporation Silicon carbide semiconductor device and manufacturing method thereof
US6239466B1 (en) * 1998-12-04 2001-05-29 General Electric Company Insulated gate bipolar transistor for zero-voltage switching
US6380569B1 (en) * 1999-08-10 2002-04-30 Rockwell Science Center, Llc High power unipolar FET switch
US6870220B2 (en) * 2002-08-23 2005-03-22 Fairchild Semiconductor Corporation Method and apparatus for improved MOS gating to reduce miller capacitance and switching losses

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5216275A (en) * 1991-03-19 1993-06-01 University Of Electronic Science And Technology Of China Semiconductor power devices with alternating conductivity type high-voltage breakdown regions
US5438215A (en) * 1993-03-25 1995-08-01 Siemens Aktiengesellschaft Power MOSFET
DE19702102A1 (de) * 1996-01-22 1997-07-24 Fuji Electric Co Ltd Halbleitervorrichtung und Verfahren zur Herstellung der Halbleitervorrichtung
WO1997029518A1 (de) * 1996-02-05 1997-08-14 Siemens Aktiengesellschaft Durch feldeffekt steuerbares halbleiterbauelement

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
ZHANG M T ET AL: "DESIGN CONSIDERATIONS AND PERFORMANCE EVALUATIONS OF SYNCHRONOUS RECTIFICATION IN FLYBACK CONVERTERS", APEC. ANNUAL APPLIED POWER ELECTRONICS CONFERENCE AND EXPOSITION,US,NEW YORK, IEEE, vol. CONF. 12, 23 February 1997 (1997-02-23), pages 623 - 630, XP000731009, ISBN: 0-7803-3705-0 *

Also Published As

Publication number Publication date
EP1119876A2 (de) 2001-08-01
US6388287B2 (en) 2002-05-14
WO2000016407A2 (de) 2000-03-23
USRE40352E1 (en) 2008-06-03
US20010050549A1 (en) 2001-12-13
DE19841754A1 (de) 2000-03-30
JP2002525853A (ja) 2002-08-13

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