WO2000012785A1 - Procede basse temperature permettant de former une couche epitaxiale sur un substrat semiconducteur - Google Patents

Procede basse temperature permettant de former une couche epitaxiale sur un substrat semiconducteur Download PDF

Info

Publication number
WO2000012785A1
WO2000012785A1 PCT/US1999/019684 US9919684W WO0012785A1 WO 2000012785 A1 WO2000012785 A1 WO 2000012785A1 US 9919684 W US9919684 W US 9919684W WO 0012785 A1 WO0012785 A1 WO 0012785A1
Authority
WO
WIPO (PCT)
Prior art keywords
temperature
processing chamber
control
controller
value
Prior art date
Application number
PCT/US1999/019684
Other languages
English (en)
Inventor
Georg M. Ritter
Bernd Tillack
Thomas Morgenstern
Dirk Wolansky
Paul R. Mchugh
Kevin Stoddard
Konstantinos Tsakalis
Original Assignee
Semitool, Inc.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Semitool, Inc. filed Critical Semitool, Inc.
Priority to JP2000567765A priority Critical patent/JP2002523908A/ja
Priority to EP99945264A priority patent/EP1114210A4/fr
Publication of WO2000012785A1 publication Critical patent/WO2000012785A1/fr

Links

Classifications

    • C—CHEMISTRY; METALLURGY
    • C30—CRYSTAL GROWTH
    • C30B—SINGLE-CRYSTAL GROWTH; UNIDIRECTIONAL SOLIDIFICATION OF EUTECTIC MATERIAL OR UNIDIRECTIONAL DEMIXING OF EUTECTOID MATERIAL; REFINING BY ZONE-MELTING OF MATERIAL; PRODUCTION OF A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; SINGLE CRYSTALS OR HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; AFTER-TREATMENT OF SINGLE CRYSTALS OR A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; APPARATUS THEREFOR
    • C30B29/00—Single crystals or homogeneous polycrystalline material with defined structure characterised by the material or by their shape
    • C30B29/02—Elements
    • C30B29/06—Silicon
    • C—CHEMISTRY; METALLURGY
    • C30—CRYSTAL GROWTH
    • C30B—SINGLE-CRYSTAL GROWTH; UNIDIRECTIONAL SOLIDIFICATION OF EUTECTIC MATERIAL OR UNIDIRECTIONAL DEMIXING OF EUTECTOID MATERIAL; REFINING BY ZONE-MELTING OF MATERIAL; PRODUCTION OF A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; SINGLE CRYSTALS OR HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; AFTER-TREATMENT OF SINGLE CRYSTALS OR A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; APPARATUS THEREFOR
    • C30B25/00—Single-crystal growth by chemical reaction of reactive gases, e.g. chemical vapour-deposition growth
    • C30B25/02—Epitaxial-layer growth
    • C30B25/16—Controlling or regulating

Definitions

  • Epitaxial la ⁇ ers are comprised of mono crystalline semiconductor layers that are grown er the semiconductor substrate Such layers have been known and used for many years in the production of for example, bipolar junction devices, and, more recently, in the manufacture of CMOS devices Silicon epitaxial layers (a k a , homoepitaxial lavers) are the principal epitaxial layers used in connection with silicon substrates In adv anced applications, heteroepitaxial layers comp ⁇ sed of, for example, SiGe or SiGeC, are employed
  • semiconductor substrates with epitaxial layers provide for uniform doping and accurate control of crystalline quality Such features make them particularly advantageous when large semiconductor wafers are used to manufacture the desired integrated circuit devices
  • CVD chemical vapor deposition
  • the reaction rate is very high and epitaxial layer deposition is primarily controlled by mass transport at such temperatures
  • the deposition process is not very sensitive to temperature deviations, but is very sensitive to mass transport uniformity (gas flow) at such higher temperatures
  • the reaction rate decreases exponentially with decreasing temperature Therefore, epitaxial layer deposition is reaction controlled at such temperatures
  • the deposition process is very sensitive to temperature uniformity, but is not very sensitive to mass transport Since it is often easier to control mass transport of the reactants through a processing furnace than it is to control processing temperature, the semiconductor industry has generally preferred and practiced high temperature epitaxy in which temperatures greater than about 1100 degrees Celsius are employed
  • single wafer reactors with radiation heating are commonly used.
  • Such single wafer reactors are used rather than batch reactors because the required uniformity of gas transport cannot be realized in batch reactors at such high temperatures
  • the throughput of such reactors is relatively low ( ⁇ 25 wafers/hr)
  • the processing costs are high and the price difference between epitaxial and polished wafers is very great
  • the high processing temperatures may have various undesirable effects on the wafer including, for example, creation of slip lines, undesired out-diffusion of dopants from the substrate, and corresponding incorporation of the dopants in the epitaxial layer as it is grown (autodoping)
  • a method for forming an epitaxial layer on a workpiece surface is set forth.
  • the method composes the steps of providing one or more workpieces into a processing chamber, exhausting gases from the processing chamber, replacing at least a portion of the exhausted gases with dry reaction or purging gases, adjusting the pressure in the processing chamber to sub-atmospheric levels and the temperature to no higher than approximately 1000 degrees C, removing native oxides from the workpiece. further adjusting the pressure in the processing chamber to within the range of approximately 0 1 Torr and 100 Torr, and the temperature to no higher than approximately 850 degrees C, and introducing a precursor gas into the processing chamber for forming an epitaxial layer
  • Fig 1 is a perspective view of one embodiment of a thermal reactor system in which the batch, low-temperature epitaxy process of the present invention may be executed
  • Fig 2 is a side, cross-sectional view of the exemplary thermal reactor system illustrated in Fig 1
  • Fig 3 is a table illustrating one embodiment of the process of the present invention as implemented in the exemplary thermal reactor system of Fig 1
  • Fig 4 is a side elevational view, partially in section, of a thermal reactor system that may be controlled using the temperature control system of the present invention
  • Fig 5 is a side elevational view, partially in section, of the thermal reactor system of Fig 1 A during modeling and charactenzation using thermocouple instrumented wafers
  • Fig 6 is a block diagram illustrating a preferred architecture for an overall control system that includes the temperature control system of the present invention
  • Fig 7 is a schematic block diagram illustrating one embodiment of a process sequencing system and gas interface that may be used in conjunction with the control system of Fig 2
  • Fig 8 is a logic flow diagram illustrating operation of a temperature control system constructed in accordance with one embodiment of the present invention
  • Fig 9 is a logic flow diagram illustrating operation of a controller employing Hoo control logic wherein the controller may be used to construct the system of Fig 8
  • Fig 10 is a graph of reactor temperature-versus-time illustrating the temperature overshoot that commonly occurs using p ⁇ or art temperature control systems
  • Fig 11 is a logic flow diagram illustrating operation of a temperature control system constructed in accordance with one embodiment of the present invention
  • Fig 12 is a graph illustrating one embodiment of a modified ramp function that may be applied to the input of the controller of the temperature control system to limit temperature overshoot during a ramp-up temperature phase
  • Fig 13 is a graph illustrating a further embodiment of a modified ramp function that may be applied to the input of the controller of the temperature control system to limit temperature overshoot during a ramp-up temperature phase
  • Fig 14 is a graph illustrating a still further embodiment of a modified ramp function that mav be applied to the input of the controller of the temperature control system to limit temperature overshoot dunng a ramp-up temperature phase
  • Fig 15 is a graph illustrating the effects of minimum ramp values on the shape of the curve shown in Fig 14
  • FIG 1 illustrates one embodiment of a vertically oriented thermal reactor system 10 for applying epitaxial layers to semiconductor wafers or substrates in accordance with the low-temperature epitaxy process of the present invention
  • the thermal reactor system 10 is fully disclosed in U S Patent Number 4,738,618, titled 'Nertical Thermal Processor", and issued Apnl 19, 1988
  • the teachings of the '618 patent are hereby incorporated by reference
  • the thermal reactor system 10 includes a pneumatically vertically positionable bell jar-like quartz process tube 12 and a pneumatically vertically positionable furnace 14, both of which fit coaxially in various independent vertical configurations with respect to each other to facilitate loading, processing, cooling and cleaning of the thermal reactor system 10
  • the quartz process tube 12 and the furnace 14 are positioned within a configured framework 16 and are supported on a multi-channel overhead slide mechanism 18, similar to a drawer slide, so that the quartz process tube 12 and the furnace 14 may be independently lifted and transported bv the overhead slide mechanism 18 for routine maintenance and cleaning external to the cabinet enclosures as
  • a plurality of actuator cylinders 22a-22n are axially disposed about a canister shield 24 of the furnace 14 to vertically position the furnace 14. the canister shield 24, a contained ceramic furnace heater element 26 (Fig 2), and a bell-jar shaped furnace liner tube element 28 at desired positions during operation of the reactor 10
  • Another plurality of pneumatic actuator cylinders 30a-30n are positioned about the canister shield 24 of the furnace 14 to vertically position an outer process tube lift ⁇ ng 32 and an inner process tube lift ring 33 containing the quartz process tube 12
  • a water- cooled base plate 34 and a firing pedestal 36 is positioned centrally in a load cavity shroud 38
  • An electronic control panel 40 is positioned on the upper front panel 44
  • a pneumatically sealed load door 42 is positioned on the lower cabinet front panel 45
  • Pressu ⁇ zed gas is supplied through supply line 46 for a pneumatic cylinder operation and purging of the processor Process gases are supplied through supply lines 48 and 50, respectively for axial flow through the process tube 12
  • FIG. 1 illustrates a side view in cross section of the furnace engaged over the quartz process tube where all numerals correspond to those elements previously desc ⁇ bed
  • the quartz bell jar process chamber 12 is positioned on a circular quartz ⁇ ng 68
  • the quartz ⁇ ng 68 is positioned on an inner process tube lift ⁇ ng 33, which is correspondingly positioned within an outer process tube lift ⁇ ng 32 concentric to the quartz ring 68 and quartz process tube 12
  • a quartz ⁇ ng keeper ⁇ ng 37 is positioned on the mner process tube lift ⁇ ng 33 to secure the process tube quartz ⁇ ng 68 and process tube 12 to the inner process tube lift ⁇ ng 33
  • a plurality of removable pins 70 -70n secure the outer process tube lift ⁇ ng 32 to the inner process lift ⁇ ng 33 to facilitate removal and cleansing of the quartz process tube 12 external to the vertical thermal processor housing as desc ⁇ bed later in detail
  • the outer and inner process tube lift ⁇ ngs 32 and 33 are positioned on O- ⁇ ng seals 72 and 74
  • the verticallv positionable furnace 14 includes, but is not limited to, a bell shaped element tube or furnace liner 28, a ceramic heater 26 positioned on and secured to the element tube quartz ring 78, a heater element lift ⁇ ng 80, canister flange ⁇ ng 35 and a heater element positioning ring 82.
  • the element tube quartz ⁇ ng 78 positions w ithin element lift ring 80 with an O- ⁇ ng seal 84 therewithin Canister flange ⁇ ng 35 is positioned over the heater element lift ring 80 to facilitate securement of the canister shield 24 to the heater element lift ring 80
  • O- ⁇ ng seal 84 also seals with flange ring 35, as well as with the element tube quartz ⁇ ng 78 and element lift ring 80
  • An O-ring seal 77 is positioned between the heater element lift ⁇ ng 80 and the quartz ring keeper ring 37
  • the heater element positioning ⁇ ng 82 is positioned over the flange ring 35 for centering and containment of the ceramic heater element 26 along the vertical axis of the furnace 14
  • the other end affixes to the flange ⁇ ng 35 while the actuating rods position in an overhead yoke 86 in the overhead sliding track mechanism 18, as illustrated in Fig. 1, to vertically position the canister 24 and the furnace 14 with respect to the quartz process tube 12 and the water-cooled base plate 34
  • the cyhndncal load cavity shroud 38 including a front loading cutout 88 and rear loading cutout 89, position over and about the cylinders 22a-22n, 30a-30n, the canister shield 24, the vertically positionable furnace 14. and the quartz bell jar like process tube 12, as illustrated in Fig 1
  • An inflatable seal 90 is positioned at the upper portion of the load cavity shroud 38 expands radially to engage with the canister shield 24 during loading and unloading of the silicon or gallium arsenide wafers or substrates, thus providing for a contamination free center portion of the vertical thermal reactor system 10
  • a plurality of resistance wire heaters 92a-92n and a plurality of thermocouple elements 94a-94n position m the ceramic heater element 26 are used to sense and control the temperature of the ceramic heater
  • the heater element is surrounded by a stainless steel shroud 95
  • the interior is lined with a heat resistant and resilient protective layer 97 of zirconia oxide to impede metallic contaminant immigration.
  • a water-cooled base plate 34 includes a bottom portion 34 ⁇ , a top portion 34b, and a water chamber 96 therebetween
  • a quartz heat shield plate ⁇ ng 98 is positioned over and above the upper base plate 34b. and below the process tube quartz ⁇ ng 68.
  • An additional circular quartz heat shield plate 100 is positioned over and above the central region of the upper water-cooled base plate 346 and provides a central atmospheric chamber 102
  • a pedestal bottom quartz heat shield 110 fits over the pedestal bottom 106 and is retained by a ⁇ ng 112.
  • a wafer load shown schematically at 114, is positioned within the process tube 12 for application of respective epitaxial layers
  • Process gases enter the quartz process tube 12 via fittings 118 and 120, and through supply tubes 122 and 124. to plumb together in a common port 126 where the process gases are injected into the upper portion of the interior of the process tube 12 for axial supply and/or flow along the length of the process tube
  • An exhaust tube 128 is disposed axially at a lower region of process tube 12, as illustrated, and passes outwardly via a through fitting 130 and to a vacuum source whereby an axial flow of processing gases may be established through the tube 12
  • a gas purge inlet port 132 and a fitting 134 are positioned in the base plate 34 to provide for purging of the quartz process tube 12
  • An additional purge inlet 136 and fitting 138 are positioned in the base plate in conjunction with a purge outlet 140 and fitting 142 for purging of the area 144 between the process tube 12 and the element tube 28
  • a low-temperature epitaxy process may be implemented using the exemplary thermal reactor desc ⁇ bed above Fig 3 is a table illustrating one embodiment of such a low-temperature epitaxy process
  • the specific parameters set forth in Fig 3 are for a silicon epitaxy process on a batch of 200 wafers to produce a 2 micrometer epitaxial layer on each wafer
  • the wafers are prepared using, for example, a wet cleaning process, so that the wafers are only coated with a native silicon dioxide layer that is preferably no thicker than about 2 nanometers
  • the batch of wafers, shown generally at 1 14. are then loaded into the thermal reactor 10 with the furnace 14 and process tube 12 in the raised position.
  • the temperature control system is set to an initial temperature of 550 degrees Celsius and remains in this state for proximally 20 minutes while the wafers are inserted into the processing area (about 0.1 minutes/wafer) Du ⁇ ng that time, the wafers are at atmospheric pressure with a nitrogen gas flow provided at 2 slm
  • the process tube 12 is lowered over the batch of wafers 1 14 and the resulting processing chamber is subject to a pump and purge process to eliminate contaminants in the wafer processing environment at the interior of the process tube 12 Du ⁇ ng this pump and purge process, the foregoing nitrogen flow is maintained
  • the furnace element 14 is then lowered over the process tube 12 after which the process tube 12 may be subject to a vacuum leak test
  • the pump and purge process and the lowenng of the furnace element 14 are performed twice The vacuum leak test ensures that leaks in the process tube 12 do not cause the pressure therein to increase beyond a predetermined rate
  • Removal of the native oxide in this manner preserves the thermal budget of the wafers This is due to the fact that the removal takes place at a temperature lower than about 1000 degrees Celsius Normally, special etching gases and/or much higher temperatures are required to remove such contamination
  • the wafers are ready for deposition of the epitaxial layer
  • the conditions for the deposition of the epitaxial layer within the thermal reactor system 10 are chosen so that the deposition process is controlled by surface reactions
  • the deposition temperatures are chosen to not exceed a temperature of about 850 degrees Celsius, and pressures within the process tube 12 are maintained in the range between about 0 1 Torr and 100 Torr
  • the temperature is rapidly ramped down, for example, to about 800 degrees Celsius using, for example, the ramp rates set forth in Fig 3 Using these ramp rates, it takes approximateh 15 minutes to go from the oxide removal temperature of 950 degrees Celsius to the desired low-temperature epitaxy deposition set-point of 800 degrees Celsius
  • the thermal reactor 10 is allowed to stabilize at the desired deposition set-point temperature for a predetermined pe ⁇ od of time, such as five minutes in the illustrated embodiment Du ⁇ ng the ramp-down and stabilization portions of the exemplary epitaxy process
  • the pressure within the processing tube 12 is preferably maintained at about 1 Torr and the hydrogen gas flow is mamtamed at about 2 slm
  • a flow of a precursor gas is introduced into the process tube 12 to generate the desired epitaxial layer on the wafers
  • a silicon epitaxial layer is desired, silane or disilane are the preferred precursors
  • Such precursors provide a higher deposition rate and effectively replace the mixtures of HC1 and S1CI 4 or S1HCI3 typically used in higher temperature processes
  • an additional germanium precursor such as GeHj, may be concurrently introduced into the process tube 12 along with the silicon gas precursor
  • a flow of silane is introduced into the process tube 12 for approximately 2 minutes as the set-point temperature is maintained at about 800 degrees Celsius
  • the duration of this portion of the process is dependent on the desired thickness of the epitaxial layer
  • the thermal reactor system 10 is controlled to execute a rapid temperature ramp down to a resting temperature of, for example, about 550 degrees Celsius Concurrent with the ramp-down process, the process tube 12 is purged using, for example, a flow of nitrogen gas
  • the rapid temperature ramp-down preferably proceeds using the ramp rates set forth in Fig 3 Using such ramp rates, the ramp-down/purge process takes approximately 10 minutes to complete
  • the ramp-down/purge cycle is followed by one or more pump and purge cycles During the pump and purge cvcles, the furnace 14 is in the raised position and is not engaged with the process tube 12
  • the process tube 12 is raised and the wafers are allowed to cool Once they have had the opportunity to cool down, the wafers are removed from the thermal reactor system 10, for example, for subsequent processing
  • the low process temperatures used in the process of the present invention allow for deposition of very thin epitaxial layers on heavily doped substrates with large doping profiles This is due to the significant reduction m auto-doping effects as compared to high-temperature epitaxy processes
  • the process of the present invention can be integrated into a state-of-the-art CMOS process
  • the low process temperature and the m-situ cleaning method that are employed do not disturb the device structures already introduced p ⁇ or to deposition of the epitaxial layer At higher temperatures, these structures would be affected by diffusion processes and crystal defects created at those high-temperature conditions
  • the cleaning methods used for high-temperature epitaxv mainly dry etching methods or annealing at very high temperatures
  • the inventive process may be integrated into state of the art CMOS processes in addition to being used for front-end substrate preparation
  • Implementation of the foregoing epitaxv process requires a thermal reactor system 10 that is capable of executing rapid temperature ramp-up and ramp-down processes that are substantially (at least two orders of magnitude) greater than the 3 degrees Celsius/mm ramp rates used in conventional thermal reactor systems
  • the thermal reactor used in the foregoing epitaxy process can execute controllable ramp rates between 10 degrees Celsius/minute and 100 degrees Celsius/minute
  • accurate control of the temperature of the wafers within the process tube 12 is desired to generate suitable epitaxial films on the wafers at such low temperatures
  • the contiol system provides accurate control over the entire temperature range used in the epitaxy process
  • temperature overshoot is preferably minimized
  • the thermal reactor 10 is capable of maintaining wafer temperature uniformity across the wafer and from wafer-to-wafer all of better than about 0 5 degrees Celsius in the temperature region between 500 degrees Celsius and 850 degrees Celsius
  • Such c ⁇ te ⁇ on can be met using, for example, the thermal reactor and control systems set forth in provisional patent applications U.
  • Fig 4 is a schematic illustration of one embodiment of the thermal reactor svstem 10 that may be controlled using a programmable temperature control system that is suitable for attaining the foregoing attributes
  • the temperature control systems disclosed hereinafter correspond to those set forth in the foregoing provisional applications
  • the thermal reactor system 10 includes a thermal reactor 212
  • the thermal reactor 212 includes the process tube 12, which, as noted above, defines a reactor chamber
  • the thermal reactor system 10 further includes a boat loader or paddle 218, which inserts or removes a wafer load 220 into or from the process tube 12.
  • the wafer load 114 preferably includes a plurality of boats 226 that, for example, are formed of quartz or silicon carbide
  • the wafer load 114 further includes a plurality of silicon wafers 228. and each boat 226 supports a plurality of the wafers 228
  • wafers on each boat 226 are equally spaced and the boats of wafers generally form a wafer or other semiconductor workpiece processing array.
  • the thermal reactor 212 also includes one or more heating elements 230 that surround the process tube 12
  • the heating element 230 is an electncal resistance heating coil or coils extending along the length of the processing chamber parallel to the length of the process tube 12
  • the heating element 230 is preferably subdivided into a plurality of separately controllable heating zones 232 by, for example, providing connections along the coil to divide the coil or coils into separately controllable zones The zones are then separately controllable by supplying power to opposite ends of each zone associated coil or portion of a larger coil
  • the thermal reactor system 1 includes high cu ⁇ ent voltage transformers and silicon controlled rectifiers (SCRs) for controllably applying power to each of the heating zones 232
  • Ceramic insulation 235 encases the heating element 230 The insulation serves to reflect and otherwise direct heat toward the wafer array and, further, serves to provide a more uniform layer to minimize heat flux va ⁇ ations away from the processing array
  • Temperature feedback and/or inputs for use in controlling the processing temperatures are de ⁇ ved from at least two sources a plurality of spike thermocouples 236 and a plurality of profile thermocouples 242
  • Thermocouples as the term is used herein encompasses a va ⁇ ety of temperature sensors, including the more specific meaning of thermocouples
  • Alternative temperature sensor constructions are also intended by the use of the term thermocouples
  • the spike thermocouples 236 are placed at a suitable location, such as between the heating element 230 and the process tube 12, to measure the temperature of the heaung element at a respective zone
  • the spike thermocouples 236 are thus spaced apart along the length of the heating element 230, at least one spike thermocouple 236 being located in each of the heating zones 232
  • the spike thermocouples 236 provide the most specific and responsive indications of the temperature at or of the heating elements in each of the heating zones
  • the profile thermocouples 242 are disposed along an elongated profile rod 240 and are supported in a sheath 238 that extends inside the process tube 12
  • the sheath 238 is preferably form of quartz or silicon carbide
  • the profile rod 240 has a length parallel to the length of the process tube 12
  • At least one thermocouple 242 is located in each of the heating zones 232
  • the profile thermocouples 242, however, are not necessanly aligned with the spike thermocouples 236
  • the profile thermocouples 242 measure temperature inside the process tube 12 and provide an indication of the temperature of the wafer load 114 in each of the respective heating zones
  • thermocouple instrumented wafers 244 are optionally employed during modeling of the thermal reactor Fig 5 shows the thermal reactor 12 of Fig 4 receiving the thermocouple instrumented wafers 244 during modeling These thermocouple instrumented wafers 244 are uniformly spaced across the wafer load 114 to provide an accurate measurement of the actual temperature of the wafers 228
  • Each of the exemplary thermocouple instrumented wafers 244 includes a silicon wafer, and two thermocouples 246 bonded to the silicon wafer one on the edge of the wafer, and one on the center of the wafer The thermocouples 246 of each instrumented wafer 244 are bonded to the silicon wafer, such as with a ceramic adhesive, to provide accurate temperature measurements
  • the thermal reactor system 10 include a gas delivery system or gas panel 248 for controllably injecting process gases from selectable gas supplies 250 into the process tube 12 to grow or clean matenal on the surface of the silicon wafers 228 during the epitaxy process desc ⁇ bed above
  • the gas panel 248, as shown m Fig 7, includes valves 252 and mass flow controllers 254
  • the mass flow controllers 252 are used to measure and control flows of process gasses into the process tube 12
  • the process tube 12 is pressu ⁇ zed for low pressure chemical vapor deposition epitaxv processes
  • the thermal reactor system 10 preferably includes a pressure controller 256 and a baratron or other suitable pressure sensing device 258 which measures the pressure in the process tube and communicates the measured pressure to the pressure controller 256
  • the thermal reactor system 10 includes pumps and valves 60, in communication with the pressure controller 56, that are used to achieve the desired pressure in the process tube 12 for the disclosed epitaxy process
  • the thermal reactor system 10 includes a control system 264 for controlling the temperature and other processes in the thermal reactor 12
  • the control system 264 is preferably divided into two subsystems a process sequencing subsystem 266 for accepting and executing a process sequence, and a temperature subsystem 268 for temperature control in accordance with the process sequence
  • Both the process sequencing subsystem 266 and temperature control subsystem 268 follow user defined process recipes that, for example, are entered through user interface 282
  • the process sequencing subsystem includes a microprocessor that interfaces with random access memory 272, a programmable EPROM 274 that stores controller logic, a plurality of digital input and output channels 276, a plurality of analog input and output channels 278, and a user interface 282.
  • a plurality of se ⁇ al input and output channels 80 for external (remote) communication may be included, if external communication is desired
  • the user interface 82 of the disclosed embodiment comprises a touch screen terminal interface with which a user can enter a user defined process recipe
  • the user can define, on a per step basis, step time, gas flows, chamber pressure, temperature set-points, and ramp rates
  • Parameters necessary for temperature control are communicated to the temperature control subsystem 68 as input parameters that are used b ⁇ the temperature control subsystem to implement the temperature control aspects of the recipe
  • This communication capability is illustrated by line 87
  • such parameters comp ⁇ se at least the temperature set-points entered by the user for the recipe
  • the thermal reactor system 10 includes a gas delivery system and pressure control system
  • a gas delivery system and pressure control system may include the control system interface illustrated in Fig 7 that provides an interface between the process sequencing subsystem 266 and the hardware of the gas delivery system and/or pressure control system
  • a gas panel interface 304 is connected between the gas panel 148 and the process sequencing subsystem 168
  • the gas panel interface 304 provides the control system 264 with an interface to communicate with the mass flow controllers 254, the gas valves 252, the pressure controller 256. the boat loader 218, etc
  • the gas panel interface 304 may include a plurality of hardware safety interlocks for the thermal reactor (e g , to ensure hydrogen flow with a proper oxygen to hydrogen ratio, to detect a flame from the torch 62, etc )
  • the temperature control system 268 controls the temperature within the thermal reactor 12 in accordance with a user programmed recipe Temperature control is preferably based on dynamic modeling of the thermal reactor 12 in which desired temperature states are modeled based on measurable system parameters In operation, the recipe comp ⁇ ses temperature set-point values that are used by one or more dynamic models to d ⁇ ve the thermal reactor 12 to the desired temperature state
  • the temperature control subsystem 268 receives at least two input signals for each predefined heating zone a profile thermocouple input from which the temperature at the profile thermocouple for the respective heating zone may be determined, and a spike thermocouple input from which the temperature at the spike thermocouple for the respective heating zone may be determined
  • profile and spike temperature are provided through a thermocouple interface 330 as illustrated by line 415 and are used in conjunction with the temperature set-point input at line 335 to provide one or more heating element output control values at lines 340
  • the output control values at lines 340 are supplied to the input of a heating elements control interface 345 and are used to control the electncal power that is supplied at lines 350 to respective heating zone elements
  • Fig 8 illustrates one manner of implementing the temperature control subsystem 268
  • a plurality of multiva ⁇ able controllers 296, 298, and 300 are employed
  • Each of the controllers 296, 298, and 300 is designed, preferably based on one or more dynamic models denved from empincal test data, for optimum control accuracy over a predetermined temperature range that is generally exclusive of the temperature range of the other controllers
  • controller 296 is designed for optimal temperature control over a low-level temperature range
  • controller 298 is designed for optimal temperature control over a mid-level temperature range
  • controller 300 is designed for optimal temperature control over a high-level temperature range
  • the temperature ranges for which the controllers are designed are generally unique, it will be recognized that some overlap of the temperature ranges mav be desired
  • the low level temperature range may be centered about 500 degrees Celsius
  • the mid-level temperature range may be centered about 800 degrees Celsius
  • the high-level temperature range may be centered about 1050 degrees Celsius
  • the range over which each controller operates thus extends roughly +
  • each of the controllers 296, 298, and 300 is constructed using robust optimal control theory with empincallv denved models of the furnace and workpieces that are to be heated More particularly, in the illustrated embodiment, the multivanable controllers 296, 298, and 300 are preferably constructed using H-Infinity control theory One manner of denvmg the models used in the controllers 296, 298, and 300 is set forth in the application U S S N 08/791 ,024, titled "Model Based Temperature Controller For Semiconductor Thermal Processors", filed January 27, 1997 As disclosed in that application, each controller design preferably employs two dynamic models One of the dynamic models relates power inputs to spike outputs and the second model relates spike inputs to profile outputs. However, it wall be recognized that other multi-variable control logic designs may also be used
  • control logic flow illustrated in Fig 8 is generally independent of the particular control theory used to design the controllers 296, 298, and 300. The only general requirement is that each controller 296, 298, and 300 is capable of generating an accurate control output based on one or more measured vanable inputs.
  • the vanable inputs to each controller comprise the set- point input and one or more of the temperature data inputs indicative of the temperature detected by the thermocouples 236 and 242
  • the set-point input shown generally in logic block form at 155, holds the set-point temperature value that is to be attained. This value is determined by the particular recipe that is being implemented by the system 10, and is concurrently supplied to the input of each of the controllers 296, 298, and 300.
  • each of the controllers 296, 298, and 300 concurrently receives a plurality of data values indicative of the temperature values sensed by the thermocouples 236 and 242
  • the set-point temperature value and the thermocouple data values are applied to a dynamic model respectively associated with each of the controllers 296, 298, and 300, to generate respective output control values, generally illustrated at lines 360, 365, and 370.
  • the dynamic model used by each controller is optimized for use over a temperature range that is generally exclusive of the temperature range for which the dynamic models of the other controllers are designed
  • the output control values at lines 360, 365, and 370 provide three potential solutions that may be used to drive the reactor 12 to the desired set-point temperature. Only one of the three potential solutions, however, may be optimal for a given reactor condition because the models used by the controllers differ from one another and are optimized only over a predetermined temperature range
  • the temperature subsystem 268 must therefore select which set of control values is to be provided to the heating element firing interface 345 to control the heating elements and. thus, the reactor temperature
  • control output selection switch logic shown generally in logic block form at 375
  • the control values at lines 360, 365, and 370 are provided to the input of the control output selection switch 375 which, in turn, switches one set of control values to a control value output, shown generally by line 340, based on predetermined selection c ⁇ te ⁇ a
  • the selection c ⁇ te ⁇ a are preferably based on measurable input values that indicate which of the dynamic models used in denying the controllers 296 298. and 300 is optimal under the given conditions
  • One of the c ⁇ te ⁇ on that may be used by the control output selection switch 375 as a basis for selecting which of the control values is to be provided to the heating element firing interface 345 is the set-point input value at 335 As shown by line 335, the set-point input value mav be provided as an input to the control output selection switch 375 Which set of control values illustrated at lines 360, 365, and 370 is provided at the output of the control output selection switch 375 thus depends on the particular temperature set-point input value provided at line 335
  • switching logic dependent on the value of the temperature set-point input value may involve allocating upper and/or lower set-point temperature threshold values to each of the controllers 296, 298, and 300
  • the output value 360 of the low-level temperature controller 296 may be switched to the output 340 whenever the set-point temperature value is below a given threshold value, T OW
  • Tm gh a further threshold value
  • the set of control values at 365 of the mid-level temperature controller 298 may be switched to the output 340
  • the set of control values at 170 of the high-level temperature controller 300 may be switched to the output 340
  • the value of T OW IS preferably chosen to be close to the upper temperature value for which the dynamic model used b> the low-level temperature controller 296 is accurate and/or optimal
  • T w may be chosen to be close to the lower temperature value for
  • thermocouple temperature input value As detected by one or more of the thermocouples 236 and 242 As shown by line 380, the thermocouple temperature input value may be provided as an input to the control output selection switch 375 Which set of control values illustrated at lines 360, 365, and 370 is provided at the output of the control output selection switch 375 thus depends on the particular thermocouple temperature input value provided at line 380
  • a thermocouple such as a spike thermocouple 236a of Fig 5, disposed proximate a mid-portion of the reactor chamber is used to provide the thermocouple temperature input value. Thermocouples disposed proximate the mid-portion of the reactor chamber tend to provide temperature input values that are more indicative of the average temperature across the entire chamber
  • thermocouple temperature input value may involve allocating temperature ranges over which each of the controllers 296, 298, and 300 is to be selected for output
  • T OW a given threshold value
  • the set of control values available at 360 of the low-level temperature controller 296 may be switched to the output 340 W enever the thermocouple input value indicates a temperature lying in a range above T LO but below a further threshold value, T ⁇ i gh
  • the set of control values illustrated at line 365 of the mid-level temperature controller 298 may be switched to the output 340
  • the thermocouple input value indicates a temperature that is in a range above Tmg h
  • the set of control values illustrated at line 370 of the high-level temperature controller 300 may be switched to the output 340
  • the value of T OW IS again preferably chosen to be close to the upper temperature value for which the dynamic model used by the low-level temperature controller 296 is
  • the present inventors have found that it is desirable to have all of the controllers 296. 298, and 300, calculating control values based on their respective dynamic model even when the control value of a particular controller is not used at output line 340.
  • they have also recognized that switching to a control value output of a previously unused controller once the switching cnte ⁇ on for the unused controller have been met in the control output selection switch logic 375 may result in the control system 68 driving the reactor 12 to the desired set-point temperature value in a sub-optimal manner This is due to the fact that the dynamic model used in the unused controller differs from the dynamic model of the controller that is used pnor to the control value switch
  • the different dynamic models result in substantially different control value solutions available for output at line 340
  • each controller 296, 298, and 300 is logically divided into a respective observer gain feedback logic unit 385, 390, and 395, and a respective temperature control logic unit 400, 405, and 410
  • Each temperature control logic unit 400, 405, and 410 implements the respective dynamic model based on the set-point input value 355, the plurality of thermocouple data values indicated by line 415, and an observer gain feedback output value provided from the respective observer gain feedback logic unit as shown at lines 420, 425, and 430
  • Each observer gain feedback logic unit 385, 390, and 395 receives one or more input values that are used to generate the observer gam feedback output value to the respective temperature control logic unit 385, 390, and 395
  • each observer gain feedback logic unit 385, 390, and 395 receives one or more controller output values calculated by the respective temperature control logic umt 400, 405, and 410, as shown at lines 435,
  • the observer ga feedback value at lines 420, 425, and 430 for a particular controller differs for a giv en set of controller output values at lines 435, 440, and 445 depending on whether or not the control value output of the particular controller is being supplied at output line 340 for provision to the heating element firing interface 345
  • a given set of low temperature controller output values at line 435 results in a set of control values, X, at line 360 when the value mput at lme 450 indicates that the output of the controller 296 at line 360 is provided at output 340
  • This same given set of low temperature controller output values at line 435 results in a different set of control values, Y, at line 360 when the value put at line 450 indicates that the output of the controller 96 at line 360 is not provided at output 340
  • the dynamic model values at lines 435, 440, and 445 are preferably subject to a first control matrix calculation by the respective observer gain feedback logic unit 385, 390, and 395, when the control value output
  • Fig 8 is generally independent of the particular multi-variable dynamic model used by the temperature controllers 296, 298, and 300 Fig 9, however, illustrates one manner of implementing a temperature controller using two dynamic models one model relating power inputs to spike outputs, and the other model relating spike inputs to profile outputs
  • the dynamic models are specifically designed for using the temperature values provided by the profile and spike thermocouples
  • the architecture of Fig 9, although designated with the label 296 of the low-level temperature controller, is suitable for use m the design of each of the temperature controllers 296, 298, and 300
  • the controller shown generally at 296, includes a profile error signal generator 490 that generates profile error values at line 495 based on a companson between the temperature set-point value as designated at line 335 and profile thermocouple values received at line 300 Similarly, a spike error signal generator 505 generates spike error values at line 510 The profile error values at line 495 are provided to the input 15 of the profile controller 520 while the spike error values at line 510 are provided to the input 525 of the spike controller 530
  • a profile error values at line 495 are provided to the input 15 of the profile controller 520 while the spike error values at line 510 are provided to the input 525 of the spike controller 530
  • U S S N 08/791,024 titled “Model Based Temperature Controller For Semiconductor Thermal Processors", filed January 27, 1997, and the specific details thereof are omitted for the sake of simplicity
  • the controller 296 implements observer gain feedback logic in accordance with the system architecture of Fig 9 and the corresponding disclosure above To this end, an anti-wmdup gain computation mat ⁇ x 535, a gain-schedule computation mat ⁇ x 540, and an observer mode switch 545 are used to compute the values of the parameters provided at input 515
  • the anti-windup gam computation mat ⁇ x 535 provides output values at 555 that are computed using a first set of gam parameters
  • the gain-schedule computation matrix 540 provides output values at 560 that are computed using a second set of gain parameters
  • the output values at 555 and 560 are provided to the input of the observer mode switch 545
  • the observer mode switch 545 selects which of the values at 555 or 560 are provided to the input 515 of the profile controller 520
  • the observer mode switch 545 provides the output values at 555 of the anti-wmdup gain computation mat ⁇ x 535 when the value of the signal illustrated at 450 indicates that the control values at
  • a similar logic architecture is associated with the spike controller 530.
  • an anti-windup ga computation matrix 570 provides output values at 585 that are computed using a first set of gam parameters
  • the gain-schedule computation matrix 575 provides output values at 590 that are computed using a second set of gain parameters
  • the output values at 585 and 590 are provided to the input of the observer mode switch 580
  • the observer mode switch 580 selects which of the values at 585 or 590 are provided to the input 525 of the spike controller 530
  • the observer mode switch 580 provides the output values at 585 of the anti-windup gain computation mat ⁇ x 570 when the value of the signal illustrated at 450 indicates that the control values at output 360 of the controller 296 are being prov ided to the heating element fi ⁇ ng interface 345 Similarly, the observer mode switch 5
  • a de-coupled observer feedback system can also be implemented using the logic architecture of Fig 9 In such a system, the ga s associated with the input values designated with circles are set to zero
  • a wide range of system logic architectures are suitable for implementing a temperature control system that utilizes both the profile and spike thermocouple data values to calculate control values that are selectively provided to the heating element firing interface 345 and which include the disclosed observer gam feedback logic
  • the temperature control system may be designed so that a set of output values from one of a plurality of profile controllers designed for different temperature ranges are selectively supplied to the input of a single, common spike controller
  • the disclosed observer mode feedback logic would be applied solely to each profile controller
  • Fig 10 A graph of the reactor temperature-vs -time when the reactor temperature is dnven in this manner is illustrated in Fig 10 As shown, the temperature of the reactor overshoots the set-point temperature before the temperature controller it is ultimately able to regulate the reactor temperature at the set-point Such overshoot may significantly alter the thermal processing of the semiconductor wafers, or other workpieces, in an undesirable manner Overshoot generally increase as the ramp rate increases and, as such, may be very significant when rapid ramp rates are used
  • Fig 11 illustrates one manner of implementing the temperature control system 268 so as to minimize overshoot thereby allowing the use of rapid ramp rates
  • a controller 640 is connected to receive a plurality of data values represented by line 635 that co ⁇ espond to the temperature values as measured by the thermocouples 236, 242 Additionally, the controller 640 receives temperature output values, T outp ut, from a ramp-up/ramp-down temperature value generator 645 As will be explained in further detail below, the temperature value generator 645 provides the temperature output values, Tout p ut, to the controller 640 in response to at least the temperature set- point input value, shown logically at 650.
  • the controller 640 is constructed using robust optimal control theory with empi ⁇ cally denved models of the furnace and workpieces that are to be heated More particularly, the controller 640 is preferably implemented in the manner descnbed above in which multiple temperature range models and observer gain feedback are employed However, it will be recognized that other multi-va ⁇ able control logic designs may alternatively be used The control logic flow illustrated in Fig 11 , however, is shown as being generally independent of the particular control theory used to design the controller. The only general requirement for overshoot control is that the controller 640 is capable of executing a dynamic model based on one or more measured vanable inputs
  • the controller 640 applies the temperature output value provided at 655 and the thermocouple data values at 635 to its dynamic model
  • the controller 640 uses the mput values to generate an output that comprises a plurality of control values that are provided, for example, at the output represented by line 660 to the input of a heatmg element fi ⁇ ng interface 665
  • the firing interface 665 applies controlled power to the heating element zones at lines 670 based on the values of the control values to thereby adjust the amount of heat provided in each zone and thus regulating the reactor temperature
  • the controller 640 does not receive the set-point input value for direct input to its dynamic model Rather, the temperature set-point input value is provided to the temperature value generator 645 which, in turn, provides the controller 640 with mcremental temperature output values, T output , that the controller 640 uses for temperature control of the thermal reactor 12
  • the temperature output values, T 0Ut p U t form a modified ramp function over time
  • the temperature output values forming the modified ramp function dnve the controller 640 at or close to a maximum ramp rate toward the temperature set-point input value, T sp , during a portion of the ramp-up phase
  • the ramp rate of the modified ramp function is reduced as it approaches the temperature set-point value to thereby inhibit temperature overshoot m the thermal reactor 12
  • the goal of the temperature value generator 645 is to provide a sequence of temperature output values, T ou t pu t, that d ⁇ ve the controller 640 and, thus, the reactor temperature, from an initial temperature, T ⁇ mt , a ⁇ , to the temperature set-pomt input value. T sp
  • the temperature value generator 645 provides temperature output values, T outpul , that form a modified ramp function over time
  • T outpul temperature output values
  • the temperature value generator 645 receives a new temperature set-point input value at time ti and proceeds to provide the controller 640 with incremental temperature output values, T ⁇ u tput, that correspond to a maximum ramp rate, R max
  • the value of the maximum ramp rate, Rmax, mav be based on a value mput by the user or may be a predetermined svstem constant
  • the temperature value generator 645 begins to provide the controller 640 with temperature output values, T ou tput, that correspond to a minimum ramp rate, RTM,,
  • This minimum ramp rate is used until the temperature output value, T 0U ⁇ P ut, provided bv the temperature value generator 645 equals the temperature set-point input value, T sp
  • the value of the minimum ramp rate, R m ,,, may be based on a value input by the user or may be a predetermined system constant It is preferably set to the minimum ramp rate that generates the maximum tolerable temperature overshoot in the thermal reactor 12 that does not impair the thermal processing of the workpieces beyond process tolerances
  • the point at which the temperature value generator 645 switches from the maximum ramp rate, R m ⁇ , to the minimum ramp rate, Rmm may be set m a number of ways
  • the temperature value generator 645 may switch to the mimmum ramp rate when the temperature value is equal to or exceeds a threshold value
  • This threshold value mav be based on the percentage, X, of the temperature set-pomt mput value, T sp
  • the value of X mav be part of the recipe entered by the user, or it may be a predetermined system constant
  • the temperature value generator 645 may switch to the minimum ramp rate at a predetermined time in the ramp-up phase This predetermined time value mav be based on the percentage predetermined percentage, Z, of the total ramp time, (t 2 - tj)
  • Fig 13 illustrates a further modified ramp function that may be implemented by the temperature value generator 645
  • the temperature v alue generator 645 generates temperature output values, T 0U t P ut, that dnve the controller 640 at the minimum ramp rate, R m , n , at a beginning portion of the ramp-up phase
  • the temperature value generator 645 generates temperature output values, T ou tput, that dnve the controller 640 at the maximum ramp rate, R m a x
  • a further predetermined pomt such as at a percentage, X.
  • the temperature value generator 645 a gam generates temperature output values, T ou t pu t, that drive the controller 640 at the minimum ramp rate, Rm, n , until the temperature output value reaches the temperature set-point mput value, T sp
  • ramp rate switching may alternatively be based on total ramp- up time, user programmed recipe values, predetermined system constants, etc
  • a further modified ramp-up function that may be implemented by the temperature value generator 645 is shown in Fig 14
  • the ramp rate, Rc urr e n t used by the controller 640 varies over the ramp-up phase, but is in no event less than the minimum ramp rate, Rm, n
  • the ramp rate, Rcurre n t at a given temperature output value.
  • T ou tput, mav be described as follows
  • T sp is the temperature set-point value
  • temperature output values, T ou t p ut, generated in the foregoing manner provide a smoother transition between the minimum and maximum ramp rates used over the duration of the ramp-up phase Such smooth transitions allow the controller 640 to more accurately control the temperature of the thermal reactor 12
  • Fig 15 illustrates the effect of the value of given minimum ramp rate values, R mm , on the temperature output value, T ou t pu t
  • line 710 is a graph of the temperature output values.
  • T ou t pu t where a large minimum ramp rate, R mm , is used.
  • Line 715 is a graph of the temperature output values, T outpu t, wherem a minimum ramp rate, R m , n , is used that is less than the minimum ramp rate used to obtain the temperature output values illustrated by line 710 Similarly, lines 718 and 720 represent temperature output values in which even lower minimum ramp rates are used As can be seen from Fig 15, a lower minimum ramp rate lengthens the time that it takes to ultimately reach the temperature set-point value, T sp , but provides for a smoother transition toward that value thereby reducing and/or eliminating temperature overshoot in the thermal reactor 12 A similar effect results when the time constant, ⁇ , is va ⁇ ed Larger time constants result in smoother transitions between the minimum and maximum ramp rates and, further, provide for smoother transition as the temperature output value reaches the temperature set-point value, T sp
  • modified ramp functions illustrated in the foregoing environments are directed toward application in a temperature ramp-up phase, it will be recognized that such modified ramp techniques may also be used in a temperature ramp-down phase
  • one of the goals of the modified ramp operation is to prevent the temperature of the reactor from fallmg below its newly applied set-pomt temperature

Landscapes

  • Chemical & Material Sciences (AREA)
  • Engineering & Computer Science (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Materials Engineering (AREA)
  • Metallurgy (AREA)
  • Organic Chemistry (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • General Chemical & Material Sciences (AREA)
  • Chemical Vapour Deposition (AREA)

Abstract

L'invention concerne un procédé basse température permettant de former une couche épitaxiale sur la surface d'une pièce sans que des conditions de dépression et de propreté extrêmes ne soient requises à l'intérieur de l'enceinte de traitement pendant la formation de cette couche épitaxiale. Ce procédé permet en outre de former simultanément une couche épitaxiale sur une pluralité de pièces (28). Ces pièces sont placées dans une enceinte (12) comprenant un système (212) de chauffage à commandes multiples et des systèmes de commande (308, 306). Le gaz (250) est acheminé via un tube et un panneau (248) de commande permettant le réglage du débit.
PCT/US1999/019684 1998-08-26 1999-08-26 Procede basse temperature permettant de former une couche epitaxiale sur un substrat semiconducteur WO2000012785A1 (fr)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP2000567765A JP2002523908A (ja) 1998-08-26 1999-08-26 半導体基板にエピタキシャル層を形成する低温プロセス
EP99945264A EP1114210A4 (fr) 1998-08-26 1999-08-26 Procede basse temperature permettant de former une couche epitaxiale sur un substrat semiconducteur

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US9805798P 1998-08-26 1998-08-26
US60/098,057 1998-08-26

Publications (1)

Publication Number Publication Date
WO2000012785A1 true WO2000012785A1 (fr) 2000-03-09

Family

ID=22266670

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US1999/019684 WO2000012785A1 (fr) 1998-08-26 1999-08-26 Procede basse temperature permettant de former une couche epitaxiale sur un substrat semiconducteur

Country Status (3)

Country Link
EP (1) EP1114210A4 (fr)
JP (1) JP2002523908A (fr)
WO (1) WO2000012785A1 (fr)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2003012840A2 (fr) * 2001-07-27 2003-02-13 Ihp Gmbh-Innovations For High Performance Microelectronics/Institut Für Innovative Mikroelektronik Procede et dispositif de production de minces couches epitaxiales
DE10335460A1 (de) * 2003-08-02 2005-03-10 Infineon Technologies Ag CVD-Anlage und Verfahren zum Betreiben einer solchen CVD-Anlage
CN100418247C (zh) * 2003-11-07 2008-09-10 崇越科技股份有限公司 多腔体分离外延层有机金属化学气相外延装置及方法

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5089441A (en) * 1990-04-16 1992-02-18 Texas Instruments Incorporated Low-temperature in-situ dry cleaning process for semiconductor wafers
US5168089A (en) * 1989-11-27 1992-12-01 At&T Bell Laboratories Substantially facet-free selective epitaxial growth process
US5273621A (en) * 1989-11-27 1993-12-28 At&T Bell Laboratories Substantially facet-free selective epitaxial growth process
US5308788A (en) * 1991-09-13 1994-05-03 Motorola, Inc. Temperature controlled process for the epitaxial growth of a film of material
US5498578A (en) * 1994-05-02 1996-03-12 Motorola, Inc. Method for selectively forming semiconductor regions
US5906708A (en) * 1994-11-10 1999-05-25 Lawrence Semiconductor Research Laboratory, Inc. Silicon-germanium-carbon compositions in selective etch processes

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4738618A (en) * 1987-05-14 1988-04-19 Semitherm Vertical thermal processor
JP2950272B2 (ja) * 1997-01-24 1999-09-20 日本電気株式会社 半導体薄膜の製造方法
US5895596A (en) * 1997-01-27 1999-04-20 Semitool Thermal Model based temperature controller for semiconductor thermal processors

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5168089A (en) * 1989-11-27 1992-12-01 At&T Bell Laboratories Substantially facet-free selective epitaxial growth process
US5273621A (en) * 1989-11-27 1993-12-28 At&T Bell Laboratories Substantially facet-free selective epitaxial growth process
US5089441A (en) * 1990-04-16 1992-02-18 Texas Instruments Incorporated Low-temperature in-situ dry cleaning process for semiconductor wafers
US5308788A (en) * 1991-09-13 1994-05-03 Motorola, Inc. Temperature controlled process for the epitaxial growth of a film of material
US5498578A (en) * 1994-05-02 1996-03-12 Motorola, Inc. Method for selectively forming semiconductor regions
US5906708A (en) * 1994-11-10 1999-05-25 Lawrence Semiconductor Research Laboratory, Inc. Silicon-germanium-carbon compositions in selective etch processes

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
See also references of EP1114210A4 *

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2003012840A2 (fr) * 2001-07-27 2003-02-13 Ihp Gmbh-Innovations For High Performance Microelectronics/Institut Für Innovative Mikroelektronik Procede et dispositif de production de minces couches epitaxiales
WO2003012840A3 (fr) * 2001-07-27 2003-11-20 Ihp Gmbh Procede et dispositif de production de minces couches epitaxiales
US7244667B2 (en) 2001-07-27 2007-07-17 Ihp Gmbh - Innovations For High Performance Microelectronics Method and device for the production of thin epitaxial semiconductor layers
DE10335460A1 (de) * 2003-08-02 2005-03-10 Infineon Technologies Ag CVD-Anlage und Verfahren zum Betreiben einer solchen CVD-Anlage
DE10335460B4 (de) * 2003-08-02 2008-02-28 Infineon Technologies Ag Verfahren zum Betreiben einer CVD-Anlage
CN100418247C (zh) * 2003-11-07 2008-09-10 崇越科技股份有限公司 多腔体分离外延层有机金属化学气相外延装置及方法

Also Published As

Publication number Publication date
JP2002523908A (ja) 2002-07-30
EP1114210A1 (fr) 2001-07-11
EP1114210A4 (fr) 2003-04-16

Similar Documents

Publication Publication Date Title
KR101267288B1 (ko) 기판 처리 장치, 기판 처리 장치의 온도 제어 방법 및 기판 처리 장치의 가열 방법
EP0606737A1 (fr) Procédé et appareillage de croissance épitaxiale d'une couche de silicium, avec un contrôle des flux massiques des gaz réactifs
US20070243317A1 (en) Thermal Processing System and Configurable Vertical Chamber
US20050121145A1 (en) Thermal processing system with cross flow injection system with rotatable injectors
US20070137794A1 (en) Thermal processing system with across-flow liner
US20050098107A1 (en) Thermal processing system with cross-flow liner
US8417394B2 (en) Substrate processing apparatus, semiconductor device manufacturing method and temperature controlling method
EP1522090A2 (fr) Systeme de traitement thermique et chambre verticale configurable
EP1535314A2 (fr) Depot a vitesse elevee a basses pressions dans un petit reacteur a fonctionnement discontinu
US6975917B2 (en) Heat treatment method and heat treatment device
US20100151682A1 (en) Method of manufacturing semiconductor device and substrate processing apparatus
US20100240224A1 (en) Multi-zone semiconductor furnace
US20100282166A1 (en) Heat treatment apparatus and method of heat treatment
EP1315854B1 (fr) Appareil et procede de nettoyage d'une cloche dans un reacteur epitaxial cylindrique
TWI497627B (zh) 熱處理裝置及熱處理方法
Schaper et al. Control of MMST RTP: repeatability, uniformity, and integration for flexible manufacturing [ICs]
EP0808917B1 (fr) Procédé et dispositif de régulation de la température d'une paroi d'un chambre de réaction
EP1114210A1 (fr) Procede basse temperature permettant de former une couche epitaxiale sur un substrat semiconducteur
JP2012193985A (ja) 基板処理装置、及び、基板の製造方法
JP3764689B2 (ja) 半導体製造方法および半導体製造装置
Apte et al. Temperature Uniformity Optimization Using Three-Zone Lamp and Dynamic Control in Rapid Thermal Multiprocessor
JP5783859B2 (ja) 基板処理装置及び基板処理装置の温度制御方法
US6784031B2 (en) Method for forming thin films of semiconductor devices
JP2005093747A (ja) 半導体処理装置

Legal Events

Date Code Title Description
AK Designated states

Kind code of ref document: A1

Designated state(s): CN JP KR SG US

AL Designated countries for regional patents

Kind code of ref document: A1

Designated state(s): AT BE CH CY DE DK ES FI FR GB GR IE IT LU MC NL PT SE

121 Ep: the epo has been informed by wipo that ep was designated in this application
DFPE Request for preliminary examination filed prior to expiration of 19th month from priority date (pct application filed before 20040101)
WWE Wipo information: entry into national phase

Ref document number: 1999945264

Country of ref document: EP

WWE Wipo information: entry into national phase

Ref document number: 09790994

Country of ref document: US

WWP Wipo information: published in national office

Ref document number: 1999945264

Country of ref document: EP

WWW Wipo information: withdrawn in national office

Ref document number: 1999945264

Country of ref document: EP