WO1999067895A1 - Procede et dispositif servant a memoriser differentes sequences d'elements et a acceder a ces sequences - Google Patents

Procede et dispositif servant a memoriser differentes sequences d'elements et a acceder a ces sequences Download PDF

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Publication number
WO1999067895A1
WO1999067895A1 PCT/SE1999/001078 SE9901078W WO9967895A1 WO 1999067895 A1 WO1999067895 A1 WO 1999067895A1 SE 9901078 W SE9901078 W SE 9901078W WO 9967895 A1 WO9967895 A1 WO 9967895A1
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WO
WIPO (PCT)
Prior art keywords
chip
memory
chip sequence
sequence
sequences
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Application number
PCT/SE1999/001078
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English (en)
Inventor
Håkan ERIKSSON
Martin Jonson
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Telefonaktiebolaget Lm Ericsson (Publ)
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Filing date
Publication date
Application filed by Telefonaktiebolaget Lm Ericsson (Publ) filed Critical Telefonaktiebolaget Lm Ericsson (Publ)
Priority to IL13984099A priority Critical patent/IL139840A0/xx
Priority to BR9911434-8A priority patent/BR9911434A/pt
Priority to EP99933343A priority patent/EP1090465A1/fr
Priority to EEP200000777A priority patent/EE200000777A/xx
Priority to AU49410/99A priority patent/AU4941099A/en
Priority to KR1020007014605A priority patent/KR20010071566A/ko
Priority to CA002335742A priority patent/CA2335742A1/fr
Priority to JP2000556455A priority patent/JP2002519887A/ja
Publication of WO1999067895A1 publication Critical patent/WO1999067895A1/fr
Priority to NO20006509A priority patent/NO20006509L/no
Priority to HK02100737.6A priority patent/HK1039225A1/zh

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Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04B—TRANSMISSION
    • H04B1/00—Details of transmission systems, not covered by a single one of groups H04B3/00 - H04B13/00; Details of transmission systems not characterised by the medium used for transmission
    • H04B1/69—Spread spectrum techniques
    • H04B1/707—Spread spectrum techniques using direct sequence modulation
    • H04B1/7097—Interference-related aspects
    • H04B1/711—Interference-related aspects the interference being multi-path interference
    • H04B1/7115—Constructive combining of multi-path signals, i.e. RAKE receivers
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04B—TRANSMISSION
    • H04B1/00—Details of transmission systems, not covered by a single one of groups H04B3/00 - H04B13/00; Details of transmission systems not characterised by the medium used for transmission
    • H04B1/69—Spread spectrum techniques
    • H04B1/707—Spread spectrum techniques using direct sequence modulation
    • H04B1/7073—Synchronisation aspects
    • H04B1/7075—Synchronisation aspects with code phase acquisition
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04B—TRANSMISSION
    • H04B1/00—Details of transmission systems, not covered by a single one of groups H04B3/00 - H04B13/00; Details of transmission systems not characterised by the medium used for transmission
    • H04B1/69—Spread spectrum techniques
    • H04B1/707—Spread spectrum techniques using direct sequence modulation
    • H04B1/709—Correlator structure
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04B—TRANSMISSION
    • H04B1/00—Details of transmission systems, not covered by a single one of groups H04B3/00 - H04B13/00; Details of transmission systems not characterised by the medium used for transmission
    • H04B1/69—Spread spectrum techniques
    • H04B1/707—Spread spectrum techniques using direct sequence modulation
    • H04B1/7097—Interference-related aspects
    • H04B1/711—Interference-related aspects the interference being multi-path interference
    • H04B1/7115—Constructive combining of multi-path signals, i.e. RAKE receivers
    • H04B1/7117—Selection, re-selection, allocation or re-allocation of paths to fingers, e.g. timing offset control of allocated fingers
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04B—TRANSMISSION
    • H04B2201/00—Indexing scheme relating to details of transmission systems not covered by a single group of H04B3/00 - H04B13/00
    • H04B2201/69—Orthogonal indexing scheme relating to spread spectrum techniques in general
    • H04B2201/707—Orthogonal indexing scheme relating to spread spectrum techniques in general relating to direct sequence modulation
    • H04B2201/70707—Efficiency-related aspects

Definitions

  • the invention relates to receiving spread spectrum radio signals, such as digitally modulated signals in a Code Division Multiple Access (CDMA) mobile radio telephone system, and more particularly, to using a random access memory to store and access different chip sequences and different phases of the different chip sequences.
  • CDMA Code Division Multiple Access
  • a spreading code is a binary sequence of +1 and -1 values that are usually referred to as chips.
  • Spreading codes are usually generated by a pseudo- noise (PN) process that appears random, but that can be replicated by an authorized receiver.
  • PN pseudo- noise
  • the informational signal and the high-bit-rate spreading codes are combined by multiplying the two bit streams together. This combination of the higher-bit-rate signal with the lower-bit-rate data stream is called "coding" or "spreading" the informational data stream.
  • Each informational data stream, or channel is allocated a unique sequence, or "spreading code.”
  • Coded informational signals are used to modulate a radio-frequency (RF) carrier by, for example, quadrature phase shift keying (QPSK), and are jointly received as a composite signal at a receiver.
  • the coded signals and noise related signals overlap in both frequency and time.
  • a receiver can correlate the composite signal with one or more spreading codes to isolate and decode a corresponding information signal. It will be appreciated by those skilled in the art that the composite signal is actually correlated with a complex conjugated version of the one or more spreading codes.
  • One CDMA technique called “traditional CDMA with direct spreading," uses a spreading code (a signature sequence) to represent one bit of information.
  • FIG. 1 illustrates an example of a CDMA transmitter and a CDMA receiver.
  • a transmitter 10 receives input user data from multiple users.
  • each symbol of input user data 20 is multiplied by a signature sequence 22.
  • the signature sequence can be, for example, 256 chips long or selected from one of 64 possible codes.
  • Input user data is then spread by a long code 24.
  • the long code 24 is 2 15 chips long.
  • the signature sequences eliminate multiple access interference among users in the same cell, the long code is used to eliminate multiple access interference among the transmitters. For example, each base station in a group of base stations can use a different long code.
  • the spread signal for input user data 22 is then summed with the other spread signals to form composite signal 26.
  • Composite signal 26 is used to modulate a radio frequency carrier 28 which is transmitted by transmitting antenna 30.
  • a receiving antenna 42 receives signal 32.
  • Receiver 40 demodulates signal 32 using carrier signal 44 to provide composite signal 46.
  • Composite signal 46 is multiplied by a synchronized long code 48.
  • Receiver 40 has at least one chip sequence generator (not shown).
  • Long code 48 is a locally generated complex conjugated replica of long code 24.
  • the despread signal 50 is then multiplied by a synchronized signature sequence 50.
  • Signature sequence 52 is a locally generated complex conjugated replica of signature sequence 22 (or one of the other N signature sequences used by transmitter 10). The multiplication by signature sequence 52 eliminates the interference due to transmission to the other users.
  • the receiver 10 integrates over the length of each symbol to determine whether the symbol is a "+1 " or a "-1.” It will be evident to those skilled in the art that receiver 40 can not reconstruct input user data 20 unless it can (1) determine long code 24 and synchronize a locally generated complex conjugated replica of long code 24 with the received signal 32, and (2) determine signature sequence 22 and synchronize a locally generated complex conjugated replica of signature sequence 22 with the despread signal 50.
  • U.S. Patent 5,457,713 discloses a soft-ware assisted method for maintaining spread spectrum chip sequence synchronization.
  • appropriate chip code generators can be fashioned from an exclusive OR gate tapped shift register with feedback, a random access memory/read only memory (RAM/ROM) look- up table wherein the appropriate chip code pattern is stored, or a serial shift register wherein the appropriate chip code pattern is stored.
  • RAM/ROM random access memory/read only memory
  • U.S. Patent 5,457,713 achieves chip sequence synchronization by using a ROM look-up table that has several inputs designed to alter the time/phase offset of the repetitive chip code output. An advance input time advances the chip code position; and, a delay input time delays the chip code position.
  • RAM/ROM look-up table is useful for storing a list of relatively short signature sequences, it is not feasible to store a list of long codes that are each 2 15 bits in length.
  • a look-up table does not allow for new chip sequences or for accessing different phases of the new chip sequences.
  • a list of all possible long codes (or even portions of all possible long codes) would be too large to fit on a single chip. It is for this reason that most receivers use a bank of sequential logic circuits, such as feedback registers, to generate the necessary long codes.
  • the received signal includes two components, an I (in-phase) component and a Q (quadrature) component.
  • the transmitter codes the I components and Q components separately.
  • the received I and Q component signals are sampled every T c seconds, where T c is the duration of a chip, and stored as streams of I and Q samples.
  • T c is the duration of a chip
  • the signal has two components, usually one chip sequence generator generates a first chip sequence for the I components, and a second chip sequence generator generates a second chip sequence for the Q components.
  • signals transmitted between base and mobile stations typically suffer from echo distortion or time dispersion (multipath delay). Multipath delay is caused by, for example, signal reflections from large buildings or nearby mountain ranges.
  • the obstructions cause the signal to proceed to the receiver along not one, but many paths.
  • the receiver receives a composite signal of multiple versions of the transmitted signal that have propagated along different paths (referred to as "rays").
  • the rays have different and randomly varying delays and amplitudes.
  • Each distinguishable "ray” has a certain relative time of arrival, kT c seconds, and spans n of the I and Q chip samples, where n is the number of chips in the spreading code.
  • Each signal image is a n chip sequence.
  • the correlator outputs several smaller spikes rather than one large spike.
  • Each ray that is received after the spreading code period (that is, if the time delay caused by a reflection exceeds one spreading code period) appears as an uncorrelated interfering signal that reduces the total capacity of the communication system.
  • FIG. 2 illustrates an example of a multipath profile of a received composite signal.
  • the ray that propagates along the shortest path arrives at a time T 0 with an amplitude A Q
  • rays propagating along longer paths arrive at time T,, T 2 , T 3 with amplitudes A A 2 , A 3 , respectively.
  • the spikes received must be combined in an appropriate way. This is usually done by a RAKE receiver, which is so named because it "rakes" all the multipath contributions together.
  • a RAKE receiver uses a form of diversity combining to collect the signal energy from the various received signal paths (or rays). Diversity produces redundant communication channels so that when some channels fade, communication is still possible over non-fading channels.
  • a CDMA RAKE receiver combats fading by detecting the echo signals individually using a correlation method and adding them coherently.
  • FIG. 3a illustrates a RAKE receiver wherein delayed versions of a received signal are processed in parallel.
  • a radio frequency (RF) receiver 310 demodulates an input signal and quantizes the demodulated signal to provide digital samples 312. Digital samples 312 correspond to a composite signal.
  • the composite signal has in-phase and quadrature components that are divided into streams of I and Q samples.
  • the RAKE receiver comprises digital data receivers 320, 322, 330, and 332. When digital data receivers are used as part of a RAKE receiver, they are sometimes referred to as fingers.
  • the digital samples 312 corresponding to time T 3 are delivered to digital data receiver 332.
  • the digital samples 312 are correlated with one or more chip sequences. If, for example, digital samples 312 are complex digital samples, the stream of I samples are correlated with a first chip sequence and the stream of Q samples are correlated with a second chip sequence.
  • the RAKE reciever has delay taps 315 that correspond to the delays between each of the rays.
  • a delayed version of the digital samples 312 corresponding to time T 2 are delivered to digital data receiver 330; a delayed version of the digital samples 312 corresponding to time T, are delivered to digital data receiver 322; and a delayed version of the digital samples 312 corresponding to time T 0 are delivered to digital data receiver 320.
  • the digital samples can be collected in a buffer and different sets of the digital samples can be delivered to the digital data receivers simultaneously. The total time delay of the delay line (or the size of the buffer) limits the amount of arrival time delay that can be raked together.
  • the input samples are correlated with the same one or more chip sequences as in digital data receiver 332.
  • the finger outputs that have significant energy are appropriately weighted and combined to maximize the received signal-to-noise- and-interference ratio.
  • the finger outputs are each multiplied by a multiplier 352, and then added together by an accumulator 354.
  • the output of the accumulator 354 is decoded by a threshold device 356.
  • FIG. 3b illustrates a RAKE receiver wherein a received signal is processed in parallel with delayed versions of one or more chip sequences.
  • Digital samples 312 are processed serially instead of collecting delayed versions of the digital samples 312 from a delay tap line or a buffer.
  • the digital data samples 312 are correlated with one or more chip sequences that have a phase corresponding to time T 3 .
  • the digital data samples 312 are correlated with one or more chip sequences that have a phase corresponding to time T 2 .
  • the digital data samples 312 are correlated with one or more chip sequences that have a phase corresponding to time T,.
  • the digital data samples 312 are correlated with one or more chip sequences that have a phase corresponding to time T 0 .
  • the finger outputs that have significant energy are appropriately weighted and combined to maximize the received signal-to-noise-and-interference ratio.
  • the chip sequences are usually provided by a set (bank) of chip sequence generators. Because each ray is correlated with a different phase of the one or more chip sequences, at least one chip sequence generator is required for each ray.
  • the RAKE receiver would require four chip sequence generators, one for each phase of the chip sequence. If there is a stream of I samples and a stream of Q samples for each ray, the RAKE receiver would require eight chip sequence generators.
  • the quality of the received signal usually decreases.
  • the quality of the received signal decreases to the point that another source can provide a better signal or the system determines that it can decrease the amount of interference experienced by other mobile stations in the system, the system should perform a handoff.
  • the base station or base stations can perform what is referred to as a soft handoff.
  • a soft handoff occurs when the original source and the new source transmit substantially the same information to the mobile station at the same time until the original source terminates its transmission. If the mobile station is using a RAKE receiver, the signal from the new source appears as additional multipaths, and the RAKE receiver can process the two signals as a single signal.
  • the receiver In a soft handoff situation, the receiver allots some of the digital data receivers (first group) to the first source and its multipath rays and some of the digital data receivers (second group) to the second source and its multipath rays.
  • the first group of receivers uses a first chip sequence and the second group of receivers uses a second chip sequence. If the received signal is processed in parallel with delayed versions of the chip sequences, the first group uses different phases of the first chip sequence, and the second group uses different phases of the second chip sequence.
  • One of the problems with using multiple chip sequence generators to provide different chip sequences (and different phases of the different chip sequences) is that many portable devices are designed to enter sleep mode when not in use.
  • a mobile station roaming in a cellular system can reduce power consumption by spending the majority of its time asleep.
  • the mobile station can obtain (from the cellular system) information regarding the chip sequence that is used for pages (the paging sequence) and information regarding when in time to listen for the paging sequence (the assigned paging frame).
  • the mobile station can awaken before the assigned paging frame in order to listen for the paging sequence, and if a page is not received, the mobile station can return to sleep mode. While in sleep mode, the mobile station can power down most of its circuits.
  • it is usually still necessary to advance the chip sequence generators so that the chip sequence generators provide the same phase at the end of the sleep period as at the beginning of the sleep period. As the number of chip sequence generators increases, the benefits of sleep mode decrease.
  • one code generator and suitable components can be used to replace multiple code generators. If the chip sequence is relatively short, it is possible to use one code generator and a serial shift register to advance or delay the code.
  • these and other attempts to replace multiple code generators are not well suited for receiving increasingly longer chip sequences or processing signals serially (as opposed to initially collecting them in a memory and providing them in parallel to the correlators).
  • these attempts to replace multiple code generators with a single code generator do not provide for searching for new multipath rays. Searching for new multipath rays often involves retarding (or backing up) the chip sequence. Retarding the chip sequence is the same as advancing the chip sequence an amount less than a full period.
  • the chip sequence generator and the chip sequence reader can be implemented in hardware or software as part of or separate from a controller.
  • the chip sequence reader can access different phases of different sequences and provide the same to various correlators or circuits used in a receiver.
  • the chip sequence generator writes different chip sequences to a memory having a memory address system
  • the chip sequence reader uses a memory read address generator to access the different phases of the different sequences.
  • the memory read address generator can use a finger select value and/or a counter value to generate the memory read address(es).
  • the memory read address generator uses a finger select value that corresponds to a particular chip sequence and a particular phase of the chip sequence.
  • a first finger is designated a first finger select value corresponding to a first phase of a first sequence
  • a second finger is designated a second finger select value corresponding to a second phase of the first sequence
  • a third finger is designated a third finger select value corresponding to a first phase of a second sequence.
  • Stored sequences can also be used to search for stronger signals or rays
  • the counter value corresponds to a number of clock cycles.
  • the counter value is advanced a number of clock cycles equal to a number of clock cycles in a sleep period.
  • the receiver can conserve power during sleep mode and still access the correct phase of the correct sequence at the end of the sleep period.
  • the chip sequence generator can generate new chip sequences as needed and write the new chip sequences to addresses that are used to store chip sequences that are no longer needed. As a result, it is not necessary to store extraneous chip sequences that use up valuable chip space.
  • the memory is used to store a paging sequence that is used by a cellular system to page a mobile station. The mobile station can access the paging sequence during a period of time preceding an assigned paging frame.
  • An advantage of the invention is that a single chip sequence generator can replace multiple chip sequence generators. Another advantage is that once a chip sequence is stored in the memory, the code generator can be powered down until needed. As a result, power consumption is reduced. Moreover, different phases of different sequences are readily available whether the code generator is active or not.
  • FIG. 1 illustrates an example of a CDMA transmitter and a CDMA receiver
  • FIG. 2 illustrates an example of a multipath profile of a received composite signal
  • FIGS. 3a and 3b illustrate different RAKE receivers
  • FIG. 4 illustrates an example of a chip sequence generator
  • FIG. 5 illustrates a spread spectrum receiver and an apparatus for accessing different chip sequences and different phases of the different chip sequences
  • FIG. 6 illustrates in more detail an apparatus for accessing different chip sequences and different phases of the different chip sequences
  • FIG. 7 illustrates an apparatus for generating a memory read address
  • FIG. 8 is a flow chart diagram for storing a locally generated chip sequence in a memory.
  • FIG. 1 illustrates an example of a CDMA transmitter and a CDMA receiver.
  • FIG. 2 illustrates an example of a multipath profile of a received composite signal.
  • FIGS. 3a and 3b illustrate different RAKE receivers.
  • FIG. 4 illustrates an example of a chip sequence generator.
  • a pseudo-noise (PN) or pseudorandom sequence is one type of chip sequence that is frequently used in CDMA systems.
  • a PN sequence is a binary sequence with an autocorrelation that resembles, over a period, the autocorrelation of a random binary sequence. Its autocorrelation also roughly resembles the autocorrelation of band-limited white noise.
  • a pseudonoise sequence has many characteristics that are similar to those of random binary sequences, such as having a nearly equal number of Os and Is, very low correlation between shifted versions of the sequence, very low crosscorrelation between any two sequences, etc.
  • a PN sequence is usually generated using sequential logic circuits such as a feedback shift register.
  • Feedback shift register 70 has memory devices 71, 72, 73, . . . , m and a feedback logic circuit 78.
  • Binary sequences are shifted through the shift registers in response to clock pulses, and the output of the various stages are logically combined and fed back as the input to the first stage 71.
  • the feedback logic circuit 78 consists of exclusive-OR gates the shift register is usually referred to as a linear PN sequence generator.
  • the initial contents of the memory stages 71, 72, 73, . . . , m and the feedback logic circuit 78 determine the successive contents of the memory. If a linear shift register ever reaches a zero state, it remains in a zero state so that the output would subsequently be all 0's. Since there are exactly 2 m -l nonzero states for a m-stage feedback shift register, the period of a PN sequence produced by a linear m-stage shift register cannot exceed 2 m -l symbols. A sequence of period 2 m -l generated by a linear feedback register is called a maximal length (ML) sequence.
  • a Gold code is another type of chip sequence that is frequently used in CDMA systems. A Gold code can be created by linearly combining two PN sequences.
  • FIG. 5 illustrates a spread spectrum receiver and an apparatus for accessing different chip sequences and different phases of the different chip sequences.
  • Chip sequence generator 160 generates a chip sequence 164 that is stored in a memory 190.
  • a controller 150 is connected to the memory 190 by a bus or one or more suitable connections.
  • Chip sequence generator 160 can use memory stages and a feedback logic circuit as shown in FIG. 4 to generate the chip sequence 164.
  • the controller 150 can control the chip sequence generator 160, and ultimately the chip sequence 164, by controlling the initial contents of the memory stages.
  • the chip sequence generator 160 can generate many different chip sequences.
  • Memory 190 is any device that is suitable for storing chip sequences. One example is a random access memory device.
  • Memory 190 can use a memory address system (an address counter) so that there is an address for each chip stored in the memory 190.
  • the memory 190 can also be arranged so that each address corresponds to a particular set of chips. Each set of chips corresponds to a particular phase of a particular sequence.
  • the controller 150 can access different phases of the different chip sequences by accessing different addresses in memory 190.
  • the controller 150 can also designate an address (or a set of addresses).
  • the controller 150 can generate new chip sequences using chip sequence generator 160 and write the new chip sequences to address 166.
  • Memory 190 can use multiple outputs (or a single output) for delivering multiple phases of the chip sequence to multiple circuits in a spread spectrum receiver. These circuits can include circuits for correlating, adding, and/or multiplying two sequences together. In an exemplary embodiment, memory 190 has a bus for delivering different phases of the different chip sequence to fingers of a RAKE receiver and a searcher receiver.
  • antenna 300 receives a spread spectrum signal.
  • a radio frequency (RF) receiver 310 amplifies and filters the received signal.
  • the receiver 310 demodulates the received signal and quantizes the demodulated signal to provide digital samples 312.
  • Digital samples 312 correspond to a composite signal.
  • the composite signal has in-phase and quadrature components that are divided into streams of complex digital samples I and Q .
  • the digital samples 312 are delivered to digital data receivers 320, 322, 330, and 332 and to searcher receiver 340.
  • a delayed tap line can be used to deliver delayed versions of the digital samples to the digital data received and the searcher receiver.
  • the digital samples are processed by digital receivers 320, 322, 330, and 332 using chip sequences stored in memory 190.
  • Memory 190 has a bus or one or more suitable connections for providing chip sequences to the receiver.
  • controller 150 uses a first memory read address 181a to provide a first set of chips 201a to digital data receiver 332; a second memory read address 181b to provide a second set of chips 201b to digital data receiver 330; a third memory read address 181c to provide a third set of chips 201c to digital data receiver 322; a fourth memory read address 18 Id to provide a fourth set of chips 20 Id to digital data receiver 320; and, a fifth memory read address 181e to provide a fifth set of chips 20 le to searcher receiver 340.
  • the first set of chips 201a is a first phase of a first chip sequence
  • the second set of chips 201b is a second phase of the first chip sequence
  • the third set of chips 201c is a third phase of the first chip sequence
  • the fourth set of chips 20 Id is a fourth phase of the first chip sequence
  • the fifth set of chips 20 le is a fifth phase of the first chip sequence.
  • one or more of the set of chips can be phases of a second or third chip sequence.
  • controller 150 can provide control signals to digital data receivers 320, 322, 330, and 332.
  • the outputs of receivers 320, 322, 330, and 332 are provided to diversity combiner and decoder 350.
  • Controller 150 can assist combiner 350 in adjusting the timing of the outputs and in finding the weighted sum of the realigned outputs. Methods for diversity combining and decoding are well known in the art and will vary from system to system.
  • Searcher receiver 340 can scan different phases of a currently used sequence to look for other multipath signals (rays). Controller 150 can instruct searcher receiver 340 to search certain phases. When the controller 150 determines that searcher receiver 340 has found a stronger ray, the controller 150 can update digital data receivers 320, 322, 330, or 332 by instructing them to use a different phase of the current sequence.
  • the searcher receiver 340 can also search different phases of an inactive chip sequence. If the searcher receiver determines that the inactive chip sequence provides a stronger signal than the current chip sequence, one or more of the digital data receivers can be updated to use different phases of the inactive sequence. New chip sequences can be generated by the chip sequence generator 160 or an additional chip sequence generator (not shown). If additional chip sequences are required, these additional chip sequences are also stored in memory 190 or an additional memory (not shown). As discussed more fully below, the disclosed structure is extremely useful in soft handoff and/or sleep mode situations.
  • FIG. 6 illustrates in more detail an apparatus for accessing different chip sequences and different phases of the different chip sequences.
  • Memory 190 is any device that is suitable for storing chip sequences. If memory 190 has a memory address system that is divided into rows and columns, each row can be used to store a different sequence, a portion of a sequence, or a single chip.
  • each portion may depend on the total number of different sequences stored in the memory. As the number of sequences is increased, the length of each portion can be decreased accordingly.
  • a controller 150 has an input 360 for conditions or instructions from other circuits. Controller 150 delivers instructions to a chip sequence generator 160. Chip sequence generator 160 is capable of generating different chip sequences. The chip sequence generator 160 can write the different chip sequences to the memory 190. A serial-to-parallel converter 162 can be used to allot (or configure) the sequence 164 to rows in the memory 190. For example, the serial-to-parallel converter 162 can control how many chips are written to each row. The controller 150 generates a memory write address 166. The memory write address 166 is used to store the chip sequence 164.
  • the controller 150 also generates a memory read address 181.
  • the memory read address 181 is used to access a particular phase of a particular chip sequence.
  • the particular phase of a particular chip sequence is delivered from the memory 190 using a suitable connection 201.
  • the desired memory read address 181 will depend on conditions or instructions from other circuits via input 360. If, for example, the invention is used in a spread spectrum receiver, the memory read address 181 will depend on the chip sequence, the phase of the chip sequence, and when in time the chip sequence is needed.
  • a combiner combines the output from different fingers that are receiving the same physical channel.
  • the fingers can be configured to receive signals that use different chip sequences; signals that use the same chip sequence, but with a different phase shift; and/or signals that use the same chip sequence and the same phase shift, but that are multi-path delays.
  • the controller 150 can keep track of the fingers and which chip sequence and which phase each finger is using.
  • FIG. 7 illustrates an apparatus for generating a memory read address.
  • Memory read address generator 151 can be implemented in hardware or software as part of or separate from controller 150.
  • Memory read address generator 151 has an input for a finger select value 170 and a counter value 174.
  • the finger select value 170 corresponds to a chip sequence value 171 and a phase offset value 172.
  • the memory read address 181 depends on the combination 173 of the chip sequence value 171 and the phase offset 172.
  • the read address generator 151 can use a clock cycle to keep track of time and can advance the counter value 174 with each clock cycle. If a group of fingers are configured to receive multipaths of the same signal, the group of fingers should use the same counter value.
  • the memory read address 181 depends on the combination 175 of the combination 173 and the counter value 174.
  • the counter value 174 is useful to ensure that a circuit continues to receive the correct phase of the correct sequence. Referring back to FIGS. 5 and 6, the read address 181 is used to access a particular phase of a particular chip sequence. The particular phase of the particular chip sequence is then delivered via an output 201 to a particular finger or searcher.
  • the memory 190 can use individual connections (as shown in FIG.
  • the controller 150 can provide a series of finger select values, thereby accessing different sequences and/or phases, and provide the different sequences and/or phases to the searcher receiver.
  • the controller 150 can instruct the sequence generator 160 to generate the new sequences and to write them to the memory 190. Moreover, the controller 150 can instruct the sequence generator 160 to write to addresses that are used to store chip sequences that are no longer needed.
  • Memory 190 is also particularly useful for soft handoff situations.
  • the controller 150 can configure one or more of the fingers to receive the old chip signal and multipath rays using an old chip sequence, and configure the remaining fingers to receive the new signal and multipath rays using a new chip sequence.
  • the controller 150 can configure a fmger select value for each fmger so that the first group of fingers uses a different phase of the old chip sequence, and each fmger in the second group of fingers uses a different phase of the new chip sequence.
  • memory 190 is particularly useful for sleep mode situations. As discussed above, the full benefits of sleep mode are not realized if there are many chip sequence generators, and the sequence generators are active during sleep mode. This problem is overcome by using a single generator, storing different sequences in a memory, and advancing (or changing) a counter value before or during a sleep period. In a sleep mode situation, the controller 150 can advance the counter value 174 a number of clock cycles equal to the number of clock cycles that the receiver will be asleep so that when the receiver wakes up, each fmger is using the correct phase of the correct sequence.
  • FIG. 8 is a flow chart diagram for storing a locally generated chip sequence in a random access memory.
  • a control processor can reset a local code generator. For example, the control processor can reset the initial contents of memory stages of a feedback shift register.
  • the code generator generates stage i of a chip sequence that is determined by the initial contents of the code generator the feedback logic circuit.
  • stage i of the chip sequence is stored in a memory. Once stage i of the chip sequence is stored, different phases of the chip sequence are readily available.
  • step 440 the control processor can check to see if additional stages of the chip sequence are needed. If additional stages are needed, the code generator can generate the next stage of the chip sequence. Once the chip sequence is fully loaded, the code generator can be powered down. As discussed above, a linear feedback register generates a sequence that has a maximum period of 2 m -l, where m is the number of stages.
  • the control processor can check to see if an additional chip sequence is needed. If so, the control processor can reset the code generator and generate additional chip sequences.
  • the size of the memory can be decreased by not storing extra chip sequences and by loading chip sequences as needed. While the memory can be used to store more than one sequence, it is not necessary to store sequences that are no longer necessary for receiving signals. While the description above makes frequent reference to providing chip sequences to the fingers of a RAKE receiver or a searcher receiver, memory 190 is also useful for storing chip sequences used for specific or other purposes. For example, memory 190 can be used to store one or more chip sequences used exclusively for listening for pages.
  • the cellular system can assign a paging frame and one or more paging sequences to each mobile station.
  • Each mobile station can store the paging sequences in memory 190 so that the paging sequences are readily available.
  • the mobile station can obtain the paging sequence from the memory 190.

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Mobile Radio Communication Systems (AREA)
  • Radar Systems Or Details Thereof (AREA)
  • Circuits Of Receivers In General (AREA)

Abstract

Un générateur (160) de séquences d'éléments mémorise des séquences dans une mémoire (190) possédant un système d'adresse de mémoire. Un lecteur de séquences d'éléments met en application un générateur (150) d'adresse de lecture de mémoire afin d'accéder à différentes phases des séquences. Ce lecteur transmet les différentes phases à des corrélateurs ou des circuits d'un récepteur à spectre étalé. Le générateur d'adresse de lecture de mémoire génère des adresses en fonction d'une valeur de sélection de récepteur de données numériques et d'une valeur de compteur. Chaque valeur de sélection de récepteur de données numériques correspond à une phase déterminée d'une séquence. La valeur de compteur correspond à une position dans le temps. En mode sommeil, cette valeur de compteur est modifiée, de façon à correspondre au nombre de cycles d'horloge d'une période de sommeil. Le récepteur conserve de la puissance pendant le sommeil et accède à la phase correcte de la séquence au moment du réveil. La mémoire peut également mémoriser des séquences de recherche. Le générateur de séquences d'éléments génère de nouvelles séquences en fonction des besoins et les enregistre dans des adresses utilisées pour mémoriser des séquences ne présentant plus d'utilité.
PCT/SE1999/001078 1998-06-23 1999-06-16 Procede et dispositif servant a memoriser differentes sequences d'elements et a acceder a ces sequences WO1999067895A1 (fr)

Priority Applications (10)

Application Number Priority Date Filing Date Title
IL13984099A IL139840A0 (en) 1998-06-23 1999-06-16 Method and apparatus for storing and accessing different chip sequences
BR9911434-8A BR9911434A (pt) 1998-06-23 1999-06-16 Aparelhos para acessar diferentes sequências de chips e diferentes fases das diferentes sequências de chips, e para acessar uma ou mais sequências de radiobusca, e, processo para prover diferentes sequências de chips e diferentes fases das diferentes sequências de chips
EP99933343A EP1090465A1 (fr) 1998-06-23 1999-06-16 Procede et dispositif servant a memoriser differentes sequences d'elements et a acceder a ces sequences
EEP200000777A EE200000777A (et) 1998-06-23 1999-06-16 Meetod ja seade erinevate elementaarsignaalide järjestuste salvestamiseks ja juurdepääsuks
AU49410/99A AU4941099A (en) 1998-06-23 1999-06-16 Method and apparatus for storing and accessing different chip sequences
KR1020007014605A KR20010071566A (ko) 1998-06-23 1999-06-16 상이한 칩 시퀀스들을 기억하고 액세스하기 위한 방법 및장치
CA002335742A CA2335742A1 (fr) 1998-06-23 1999-06-16 Procede et dispositif servant a memoriser differentes sequences d'elements et a acceder a ces sequences
JP2000556455A JP2002519887A (ja) 1998-06-23 1999-06-16 異なったチップ・シーケンスの格納及びアクセスのための方法及び装置
NO20006509A NO20006509L (no) 1998-06-23 2000-12-20 Fremgangsmåte og apparat for å lagre og aksessere forskjellige chip-sekvenser
HK02100737.6A HK1039225A1 (zh) 1998-06-23 2002-01-30 存儲和讀取不同碼片序列的方法和裝置

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US10277098A 1998-06-23 1998-06-23
US09/102,770 1998-06-23

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JP (1) JP2002519887A (fr)
KR (1) KR20010071566A (fr)
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AR (1) AR018927A1 (fr)
AU (1) AU4941099A (fr)
BR (1) BR9911434A (fr)
CA (1) CA2335742A1 (fr)
EE (1) EE200000777A (fr)
HK (1) HK1039225A1 (fr)
ID (1) ID27301A (fr)
IL (1) IL139840A0 (fr)
NO (1) NO20006509L (fr)
RU (1) RU2001101930A (fr)
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Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE10024220C2 (de) * 1999-05-19 2002-06-20 Motorola Inc Verfahren und Vorrichtung zum Aktivieren eines Funktelefonempfängers mit Streuspektrum
US7085246B1 (en) 1999-05-19 2006-08-01 Motorola, Inc. Method and apparatus for acquisition of a spread-spectrum signal
US7522655B2 (en) 2002-09-09 2009-04-21 Infineon Technologies Ag Method and device for carrying out a plurality of correlation procedures in a mobile telephony environment

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE10241691A1 (de) * 2002-09-09 2004-03-25 Infineon Technologies Ag Einrichtung und Verfahren zur Durchführung von Korrelationen in einem Mobilfunksystem
CN100365945C (zh) * 2005-07-28 2008-01-30 上海大学 码分多址的扩谱通信系统和无中心无线网络
CN101162919B (zh) * 2006-10-11 2011-01-05 中兴通讯股份有限公司 一种数据缓存电路

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5345508A (en) * 1993-08-23 1994-09-06 Apple Computer, Inc. Method and apparatus for variable-overhead cached encryption
EP0661830A2 (fr) * 1993-12-30 1995-07-05 Nec Corporation Acquisition et poursuite de synchronisation pour un récepteur à spectre étalé par séquence directe
US5457713A (en) * 1994-03-07 1995-10-10 Sanconix, Inc. Spread spectrum alignment repositioning method
US5490165A (en) * 1993-10-28 1996-02-06 Qualcomm Incorporated Demodulation element assignment in a system capable of receiving multiple signals
EP0744840A2 (fr) * 1995-05-24 1996-11-27 Sony Corporation Récepteur AMDC avec consommation d'énergie réduite dans un état intermittent
EP0767544A2 (fr) * 1995-10-04 1997-04-09 Interuniversitair Micro-Elektronica Centrum Vzw Modem programmable utilisant la communication à spectre étalé

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5345508A (en) * 1993-08-23 1994-09-06 Apple Computer, Inc. Method and apparatus for variable-overhead cached encryption
US5490165A (en) * 1993-10-28 1996-02-06 Qualcomm Incorporated Demodulation element assignment in a system capable of receiving multiple signals
EP0661830A2 (fr) * 1993-12-30 1995-07-05 Nec Corporation Acquisition et poursuite de synchronisation pour un récepteur à spectre étalé par séquence directe
US5457713A (en) * 1994-03-07 1995-10-10 Sanconix, Inc. Spread spectrum alignment repositioning method
EP0744840A2 (fr) * 1995-05-24 1996-11-27 Sony Corporation Récepteur AMDC avec consommation d'énergie réduite dans un état intermittent
EP0767544A2 (fr) * 1995-10-04 1997-04-09 Interuniversitair Micro-Elektronica Centrum Vzw Modem programmable utilisant la communication à spectre étalé

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE10024220C2 (de) * 1999-05-19 2002-06-20 Motorola Inc Verfahren und Vorrichtung zum Aktivieren eines Funktelefonempfängers mit Streuspektrum
US7031271B1 (en) 1999-05-19 2006-04-18 Motorola, Inc. Method of and apparatus for activating a spread-spectrum radiotelephone
US7085246B1 (en) 1999-05-19 2006-08-01 Motorola, Inc. Method and apparatus for acquisition of a spread-spectrum signal
US7522655B2 (en) 2002-09-09 2009-04-21 Infineon Technologies Ag Method and device for carrying out a plurality of correlation procedures in a mobile telephony environment

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AU4941099A (en) 2000-01-10
NO20006509D0 (no) 2000-12-20
HK1039225A1 (zh) 2002-04-12
CN1307756A (zh) 2001-08-08
KR20010071566A (ko) 2001-07-28
NO20006509L (no) 2000-12-20
RU2001101930A (ru) 2002-12-20
EP1090465A1 (fr) 2001-04-11
AR018927A1 (es) 2001-12-12
ID27301A (id) 2001-03-22
CA2335742A1 (fr) 1999-12-29
BR9911434A (pt) 2001-03-20
JP2002519887A (ja) 2002-07-02
EE200000777A (et) 2002-04-15
IL139840A0 (en) 2002-02-10

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