CN101162919B - 一种数据缓存电路 - Google Patents
一种数据缓存电路 Download PDFInfo
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- CN101162919B CN101162919B CN2006101411406A CN200610141140A CN101162919B CN 101162919 B CN101162919 B CN 101162919B CN 2006101411406 A CN2006101411406 A CN 2006101411406A CN 200610141140 A CN200610141140 A CN 200610141140A CN 101162919 B CN101162919 B CN 101162919B
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Priority Applications (1)
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CN2006101411406A CN101162919B (zh) | 2006-10-11 | 2006-10-11 | 一种数据缓存电路 |
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CN2006101411406A CN101162919B (zh) | 2006-10-11 | 2006-10-11 | 一种数据缓存电路 |
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CN101162919A CN101162919A (zh) | 2008-04-16 |
CN101162919B true CN101162919B (zh) | 2011-01-05 |
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CN2006101411406A Expired - Fee Related CN101162919B (zh) | 2006-10-11 | 2006-10-11 | 一种数据缓存电路 |
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Families Citing this family (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN102231140B (zh) * | 2011-06-07 | 2014-04-09 | 上海电力学院 | 一种基于双口ram的数据包络获取方法 |
CN102435935B (zh) * | 2011-10-28 | 2016-06-01 | 上海华虹宏力半导体制造有限公司 | 扫描测试方法 |
CN103346808B (zh) | 2013-06-19 | 2015-09-09 | 华为技术有限公司 | 一种终端设备 |
CN103488602A (zh) * | 2013-09-14 | 2014-01-01 | 西安电子科技大学 | 一种基于总线的多位数据相关器设计方法 |
KR102521298B1 (ko) * | 2018-02-14 | 2023-04-14 | 에스케이하이닉스 주식회사 | 메모리 컨트롤러 및 그 동작 방법 |
CN110554852B (zh) * | 2018-05-31 | 2021-11-12 | 赛灵思公司 | 数据拼接结构、方法及其片上实现 |
CN109376098B (zh) * | 2018-10-12 | 2022-12-27 | 芯来科技(武汉)有限公司 | 前向旁路缓存电路 |
CN110602524B (zh) * | 2019-08-19 | 2021-12-10 | 北京影谱科技股份有限公司 | 一种多路数字流同步方法、装置、系统及存储介质 |
CN112269747B (zh) * | 2020-10-19 | 2022-04-15 | 天津光电通信技术有限公司 | 一种时分复用缓存实现时隙数据包重组的方法 |
Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5742780A (en) * | 1995-10-06 | 1998-04-21 | Lsi Logic Corporation | Dual pipeline superscalar reduced instruction set computer system architecture |
CN1307756A (zh) * | 1998-06-23 | 2001-08-08 | 艾利森电话股份有限公司 | 存储和读取不同码片序列的方法和装置 |
CN1428983A (zh) * | 2001-12-24 | 2003-07-09 | Lg电子株式会社 | 在使用不同相位时钟的传输系统之间传输数据的设备和方法 |
CN1650590A (zh) * | 2002-04-26 | 2005-08-03 | 摩托罗拉公司 | 在cdma通信系统中的弹性相关和排队 |
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Patent Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5742780A (en) * | 1995-10-06 | 1998-04-21 | Lsi Logic Corporation | Dual pipeline superscalar reduced instruction set computer system architecture |
CN1307756A (zh) * | 1998-06-23 | 2001-08-08 | 艾利森电话股份有限公司 | 存储和读取不同码片序列的方法和装置 |
CN1428983A (zh) * | 2001-12-24 | 2003-07-09 | Lg电子株式会社 | 在使用不同相位时钟的传输系统之间传输数据的设备和方法 |
CN1650590A (zh) * | 2002-04-26 | 2005-08-03 | 摩托罗拉公司 | 在cdma通信系统中的弹性相关和排队 |
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CN101162919A (zh) | 2008-04-16 |
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Effective date of registration: 20151104 Address after: Dameisha Yantian District of Shenzhen City, Guangdong province 518085 Building No. 1 Patentee after: SANECHIPS TECHNOLOGY Co.,Ltd. Address before: 518057 Nanshan District high tech Industrial Park, Guangdong, South Road, science and technology, ZTE building, legal department Patentee before: ZTE Corp. |
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Application publication date: 20080416 Assignee: Xi'an Chris Semiconductor Technology Co.,Ltd. Assignor: SANECHIPS TECHNOLOGY Co.,Ltd. Contract record no.: 2019440020036 Denomination of invention: Data caching circuit Granted publication date: 20110105 License type: Common License Record date: 20190619 |
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