WO1999065147A1 - Convertisseur a/n, n/a a surechantillonnage - Google Patents
Convertisseur a/n, n/a a surechantillonnage Download PDFInfo
- Publication number
- WO1999065147A1 WO1999065147A1 PCT/JP1999/003131 JP9903131W WO9965147A1 WO 1999065147 A1 WO1999065147 A1 WO 1999065147A1 JP 9903131 W JP9903131 W JP 9903131W WO 9965147 A1 WO9965147 A1 WO 9965147A1
- Authority
- WO
- WIPO (PCT)
- Prior art keywords
- register
- mode switching
- oversampling
- division ratio
- value
- Prior art date
Links
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M3/00—Conversion of analogue values to or from differential modulation
- H03M3/30—Delta-sigma modulation
- H03M3/39—Structural details of delta-sigma modulators, e.g. incremental delta-sigma modulators
- H03M3/392—Arrangements for selecting among plural operation modes, e.g. for multi-standard operation
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/06—Continuously compensating for, or preventing, undesired influence of physical parameters
- H03M1/08—Continuously compensating for, or preventing, undesired influence of physical parameters of noise
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M3/00—Conversion of analogue values to or from differential modulation
- H03M3/30—Delta-sigma modulation
- H03M3/458—Analogue/digital converters using delta-sigma modulation as an intermediate step
- H03M3/494—Sampling or signal conditioning arrangements specially adapted for delta-sigma type analogue/digital conversion systems
- H03M3/496—Details of sampling arrangements or methods
- H03M3/498—Variable sample rate
Definitions
- the present invention relates to an oversampling A / D (analog digital) and DZA (digital / analog) converter, and particularly relates to a sampling frequency and oversampling rate setting function.
- the sampling is performed at a frequency higher than the predetermined sampling frequency (hereinafter, referred to as “oversampling frequency” to distinguish from the predetermined “sampling frequency”), and the sampled data is digitized.
- Oversampling A / D conversion technology that obtains data at a predetermined sampling frequency by filtering data and thinning it out, or oversampling D / A conversion technology, and vice versa, has been used in the past. Used.
- AZ D in order to be the this relegated to a high frequency domain quantization noise derived from the conversion error of the D ZA converter, AZD used: signal DZA converter conversion accuracy over the accuracy of the Can be converted.
- the requirement for the conversion accuracy of the AZD / D / A converter to obtain the predetermined conversion accuracy can be relaxed.
- the Nyquist frequency that is, the aliasing frequency at which aliasing occurs during sampling
- the required characteristics of the pre-filter that cuts signals with frequencies higher than the Nyquist frequency during AZD conversion are also eased.
- the conversion accuracy can be improved, and the required characteristics of analog filters such as prefilters can be greatly reduced.
- the ratio between the over sampling frequency and the sampling frequency is constant. Therefore, if the decimator is operated at over-sampling frequency, taking advantage of the characteristics of the digital filter whose frequency characteristics are scaled by the operating frequency, 1 / or more of the sampling frequency will be attenuated. There is an advantage that the frequency characteristics of a decimator can be realized by a digital filter with a set of filter coefficients.
- the over-sampling ratio is made variable.
- the ratio of the oversampling frequency to the sampling frequency is not constant, and the frequency characteristics cannot take advantage of the characteristics of a digital filter that is scaled by the operating frequency.
- the coefficients of the digital filter that constitutes the decimator must be designed for each ratio.
- the operation parameters - data - also naturally first 2 view configuration register for setting a first
- an object of the present invention is to provide hardware of an oversampling AZD and DZA converter operable with software developed for any method of hardware. If this objective can be achieved, it will be possible to realize hardware that can be replaced with hardware of any method, and this will lead to significant cost reduction due to mass production effects.
- the present invention takes the following measures. (1) In the configuration where the hardware has a fixed oversampling ratio (a) When operating with software based on the first method in which the oversampling ratio is fixed, the register is set by software. The original oscillation frequency is divided based on the division ratio written in. (b) When operating with software based on the second method in which the oversampling ratio is variable, the division ratio and the oversampling ratio written to the register by the software are determined by the division ratio. Then, the original oscillation frequency is divided based on the converted division ratio.
- the first method in which the oversampling ratio is fixed by hardware in which the oversampling ratio is fixed by converting or converting the parameter of the register, the oversampling ratio.
- the software can be operated with any of the second systems in which the ratio is variable.
- FIG. 1 is a diagram showing a configuration for operating with software having a variable oversampling ratio.
- FIG. 2 is a diagram showing a configuration for operating with both variable and fixed oversampling ratio software.
- FIG. 3 is a diagram showing a configuration to which a mode switching function is added.
- FIG. 4 is a diagram showing the register configuration of FIG.
- FIG. 5 is a diagram showing a configuration including a mode switching register.
- FIG. 6 is a diagram showing the register configuration of FIG.
- FIG. 7 is a diagram showing a configuration for operating the frequency divider with software corresponding to a two-stage configuration.
- FIG. 8 is a diagram showing the register configuration of FIG.
- FIG. 9 is a diagram showing a configuration using a variable air oversampling ratio.
- FIG. 10 is a diagram showing a DZA converter.
- FIG. 11 is a diagram showing a conventional technique (fixed oversampling ratio).
- FIG. 12 is a diagram showing the register configuration of FIG. 11.
- Fig. 13 is a diagram showing the conventional technology (variable oversampling ratio).
- FIG. 14 is a diagram showing the register configuration of FIG.
- Fig. 15 is a diagram showing the conventional technology (two-stage frequency divider).
- FIG. 16 is a diagram showing the register configuration of FIG. BEST MODE FOR CARRYING OUT THE INVENTION
- FIG. 1 shows a basic embodiment of the present invention, in which hardware having a fixed oversampling ratio is operated by software corresponding to the second system having a variable oversampling ratio. .
- N 1 N 3 * N 4 / N 2
- N 3 and N 4 to generate N 1 there are two methods, one is to execute the above operation, and the other is to convert using a conversion table from N 3, N 4 to N 1. is there.
- the conversion method using the conversion table is particularly effective for reducing the circuit scale when the set of N 3 and N 4 is limited.
- the original oscillation frequency f clk generated by the oscillator 30 is divided by the frequency divider 31 into 1 / N 1 to become the oversampling frequency f sl. Further, the frequency divider 32 divides the frequency into 1 ZN 2 to obtain the sampling frequency f s2.
- the AZD converter 33 samples the input analog signal at an oversampling frequency fs1 to produce a digital signal.
- the decimator 134 converts the input signal sampled at the oversampling frequency f sl to 1 / N 2 and converts it to a signal at the sampling frequency f s2.
- the decimator 134 has a characteristic of sufficiently attenuating the frequency component of f s2Z 2 or more. Such frequency characteristics are often realized by a combination of a digital comb filter and a mouth-to-mouth filter.
- thinning is performed not in 1ZN2 at a time but in several steps. In this case, the product of the thinning rates of each stage is N 2.
- N 1 In order to set many sampling frequencies f s2 in the embodiment of FIG. 1, N 1 must be large. So the oscillator The original oscillation frequency f clk of the output of 30, that is, N 1 XN 2 xfs2 has a high value. Therefore, as shown in Fig. 2, by adding a multiplier 35 to multiply the frequency to N5 times, the original oscillation frequency f clk of the output of the oscillator 30 is suppressed to 1 ZN5. Oscillator 30 can be inexpensive.
- the PLL Phase Locked Loop
- N 1 N 3 * N 4 * N 5 / N 2
- Fig. 3 shows the software corresponding to the first method with the fixed oversampling ratio and the software corresponding to the second method with the variable oversampling ratio. This is an embodiment for operating both.
- which method of software is operated is switched by a mode switching signal to operate with both types of software.
- the mode switching signal is set to 1 and the value input via the user interface is divided as it is. Written to ratio register 10.
- the mode switching signal is set to 0 and written to the pseudo dividing ratio register 10 via the user interface.
- the converted value N 3 and the value N 4 written in the pseudo oversampling ratio register 21 are converted into the frequency dividing ratio N 1 by the conversion circuit 12 and written into the frequency dividing ratio register 10.
- the mode switching signal is input as an independent signal from the outside. If the AZD converter according to the present invention is implemented as an LSI, the mode switching signal is input. Has input pins I can.
- FIG. 4 shows the configuration of the register according to the embodiment of FIG.
- the pseudo frequency dividing ratio register 11 and the pseudo oversampling ratio register 21 or the frequency dividing ratio register 10 are assigned to a part of bits of one register word.
- the pseudo frequency dividing ratio register 11 and the pseudo oversampling ratio register 21 are part of one register word. Assigned to a bit.
- the operation of the hardware can be set according to the register write format of the software corresponding to the second method of varying the oversampling ratio.
- the hardware operation can be set according to the software register write format corresponding to the first method with a fixed oversampling ratio.
- FIG. 5 shows an embodiment in which the mode switching signal of the embodiment of FIG. 3 is given as a set value of the mode switching register 13 via the user interface.
- FIG. 5 shows the configuration of the register according to the embodiment of FIG.
- the mode switching register 13 is assigned to the LSB (Least Significant Bit) of the register word, it is needless to say that it can be assigned to any other pit. It is.
- the assignment of the mode switching registers 13 should be determined in consideration of compatibility and consistency with the conventional method. In many cases, both the first and second methods assume that some bits of the register word are unused (Reserved) for future expansion, and that these unused bits are switched in mode. It should be used as register 13.
- the pseudo division ratio register 11 and the pseudo oversampling ratio register 21 are one register. Allocated to some bits of the word. In this mode, the operation of the hardware can be set in accordance with the register write format of the software corresponding to the second method of varying the oversampling ratio.
- Fig. 7 shows a second method with a variable oversampling ratio. As shown in Fig. 15, there are two stages of frequency dividers, 31a and 31b. In this configuration, software that supports the method of setting N la and N 1b in the division ratio registers 10a and 10b operates. In this method, as shown in Fig.
- the frequency division ratio registers 10a and 10b and the over-sampling ratio register 20 are assigned to some bits of one register word.
- which of the two systems is operated by the software corresponding to the system is switched by the setting value of the mode switching register 13 and both are operated. It is designed to work with different types of software.
- the software supports the first method with a fixed oversampling ratio
- the value set in the mode switching register 13 is set to 1, and the value input via the user interface is used.
- the data is written to the division ratio register 10 as it is.
- the setting value of the mode switching register 13 is set to 0, and the pseudo dividing ratio register is set via the user interface.
- the values N3a and N3b written to the data 11a and 11b and the value N4 written to the pseudo oversampling ratio register 21 are converted to the dividing ratio N1 by the conversion circuit 12. Then, it is written to the division ratio register 10.
- FIG. 8 shows the configuration of the register according to the embodiment of FIG.
- the mode switching register 13 is assigned to the least significant bit (LSB) of the register word, it is needless to say that it can be assigned to any other bit. It is.
- the assignment of the mode switching registers 13 should be determined in consideration of compatibility and consistency with the conventional method. In many cases, the first and second methods use register words. Some bits are reserved (Reserved) for future expansion, and these unused bits can be used as the mode switching register 13.
- the pseudo frequency division ratio registers 11a and 11b and the pseudo oversampling ratio register 2 1 is assigned to some bits of one register word.
- the operation of the hardware can be set in accordance with the software register write format corresponding to the second method of varying the oversampling ratio.
- FIG. 9 shows an embodiment for operating hardware with a variable oversampling ratio with software that supports the first method with a fixed oversampling ratio.
- the value written to the pseudo division ratio register 11 via the user interface is converted by the conversion circuit 12 into the division ratio Nl and the oversampler.
- the data is converted to the scaling ratio N 2 and written to the frequency division ratio register 10 and oversampling ratio register 20.
- the AZD converter consisting of the oscillator 30, dividers 31, 32, A / D converter 33, and decimator 34 operates according to the values of the division ratio register 10 and oversampling ratio register 20. You.
- FIG. 10 shows the embodiment.
- the value N 3 written to the pseudo division ratio register 11 via the user interface and the value N 4 written to the pseudo over sampling ratio register 21 via the user interface are converted by the conversion circuit 12 into the division ratio N 1 And written to the division ratio register 10.
- the original oscillation frequency f elk generated by the oscillator 30 is divided into 1 ZN 1 by the frequency divider 31 to become the oversampling frequency f sl. Further, the frequency is divided by the frequency divider 21 to 1 / N2 to become the sampling frequency fs2.
- the interpolator 36 temporally interpolates the signal of the sampling frequency fs2 and converts it into a signal of the oversampling frequency fsi.
- unnecessary frequency components called images are generated, so that the interpolator 36 is a combination of a digital comb filter and a single pass filter. In many cases, this is achieved by using a combination.
- interpolation is performed in several stages. In this case, the product of the interpolation magnification of each stage is N 2.
- the signal interpolated by the interpolator 36 is converted to an analog signal by the DZA converter 35.
- a post filter (not shown) is provided after the DZA converter 35 to remove quantization noise and the like generated during the D / A conversion.
- a mode switching register 13 is added as in the embodiment of FIG. 3, software and overload corresponding to the first method with a fixed oversampling ratio can be set by mode setting. It is also possible to operate with both software that supports the second method with a variable sampling ratio.
- the first method in which the oversampling AZD conversion or DZA conversion of a single configuration is fixed by the mode setting in the hardware for the AZD conversion or the DZA conversion. It can be operated with both compatible software and software compatible with the second method of variable oversampling ratio.
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- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Compression, Expansion, Code Conversion, And Decoders (AREA)
- Analogue/Digital Conversion (AREA)
Description
Claims
Priority Applications (4)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US09/485,349 US6476750B1 (en) | 1998-06-12 | 1999-06-11 | Over-sampling A/D, D/A converter |
KR1020007001846A KR100337140B1 (ko) | 1998-06-12 | 1999-06-11 | 오버 샘플링 a/d, d/a 변환 장치 |
EP99924006A EP1120915A4 (en) | 1998-06-12 | 1999-06-11 | A / D CONVERTER, N / A WITH OVERSAMPLE |
JP2000554055A JP3657881B2 (ja) | 1998-06-12 | 1999-06-11 | オーバーサンプリングa/d,d/a変換装置 |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP10/164694 | 1998-06-12 | ||
JP16469498 | 1998-06-12 |
Publications (1)
Publication Number | Publication Date |
---|---|
WO1999065147A1 true WO1999065147A1 (fr) | 1999-12-16 |
Family
ID=15798100
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
PCT/JP1999/003131 WO1999065147A1 (fr) | 1998-06-12 | 1999-06-11 | Convertisseur a/n, n/a a surechantillonnage |
Country Status (5)
Country | Link |
---|---|
US (1) | US6476750B1 (ja) |
EP (1) | EP1120915A4 (ja) |
JP (1) | JP3657881B2 (ja) |
KR (1) | KR100337140B1 (ja) |
WO (1) | WO1999065147A1 (ja) |
Families Citing this family (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP1304808B1 (en) * | 2001-09-28 | 2005-11-23 | Freescale Semiconductor, Inc. | Multi-rate analog-to-digital converter |
Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS61137279A (ja) * | 1984-12-06 | 1986-06-24 | Sony Corp | デイスクプレ−ヤ |
JPH04291823A (ja) * | 1991-03-20 | 1992-10-15 | Canon Inc | A/d変換器 |
JPH04349709A (ja) * | 1991-05-28 | 1992-12-04 | Nec Corp | A/d変換回路 |
JPH05143632A (ja) * | 1991-11-22 | 1993-06-11 | Kawasaki Steel Corp | 積和演算器 |
JPH0763638A (ja) * | 1993-08-30 | 1995-03-10 | Akashi:Kk | 加振機の駆動制御装置 |
Family Cites Families (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS6130186A (ja) * | 1984-07-20 | 1986-02-12 | Hitachi Micro Comput Eng Ltd | 発振回路 |
JP3190080B2 (ja) * | 1990-11-30 | 2001-07-16 | 株式会社東芝 | サンプリング周波数変換装置 |
US5619202A (en) * | 1994-11-22 | 1997-04-08 | Analog Devices, Inc. | Variable sample rate ADC |
US5457456A (en) * | 1993-12-16 | 1995-10-10 | At&T Ipm Corp. | Data converter with programmable decimation or interpolation factor |
US5617088A (en) * | 1994-01-26 | 1997-04-01 | Sony Corporation | Sampling frequency converting device and memory address control device |
US5731769A (en) * | 1995-12-04 | 1998-03-24 | Motorola, Inc. | Multi-rate digital filter apparatus and method for sigma-delta conversion processes |
JP3849892B2 (ja) * | 1996-09-09 | 2006-11-22 | ソニー株式会社 | フイルタ装置及び無線通信端末装置 |
JPH10126218A (ja) * | 1996-10-15 | 1998-05-15 | Sony Corp | サンプリング周波数変換装置 |
JP3087833B2 (ja) * | 1997-03-12 | 2000-09-11 | 日本電気株式会社 | サンプル周波数変換装置 |
-
1999
- 1999-06-11 KR KR1020007001846A patent/KR100337140B1/ko not_active IP Right Cessation
- 1999-06-11 US US09/485,349 patent/US6476750B1/en not_active Expired - Fee Related
- 1999-06-11 EP EP99924006A patent/EP1120915A4/en not_active Withdrawn
- 1999-06-11 JP JP2000554055A patent/JP3657881B2/ja not_active Expired - Fee Related
- 1999-06-11 WO PCT/JP1999/003131 patent/WO1999065147A1/ja not_active Application Discontinuation
Patent Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS61137279A (ja) * | 1984-12-06 | 1986-06-24 | Sony Corp | デイスクプレ−ヤ |
JPH04291823A (ja) * | 1991-03-20 | 1992-10-15 | Canon Inc | A/d変換器 |
JPH04349709A (ja) * | 1991-05-28 | 1992-12-04 | Nec Corp | A/d変換回路 |
JPH05143632A (ja) * | 1991-11-22 | 1993-06-11 | Kawasaki Steel Corp | 積和演算器 |
JPH0763638A (ja) * | 1993-08-30 | 1995-03-10 | Akashi:Kk | 加振機の駆動制御装置 |
Non-Patent Citations (1)
Title |
---|
See also references of EP1120915A4 * |
Also Published As
Publication number | Publication date |
---|---|
KR100337140B1 (ko) | 2002-05-18 |
JP3657881B2 (ja) | 2005-06-08 |
EP1120915A1 (en) | 2001-08-01 |
KR20010023217A (ko) | 2001-03-26 |
US6476750B1 (en) | 2002-11-05 |
EP1120915A4 (en) | 2003-10-08 |
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