WO1999063540A1 - Processeur de donnees et procede de traitement de donnees - Google Patents

Processeur de donnees et procede de traitement de donnees Download PDF

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Publication number
WO1999063540A1
WO1999063540A1 PCT/JP1998/002476 JP9802476W WO9963540A1 WO 1999063540 A1 WO1999063540 A1 WO 1999063540A1 JP 9802476 W JP9802476 W JP 9802476W WO 9963540 A1 WO9963540 A1 WO 9963540A1
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WO
WIPO (PCT)
Prior art keywords
data
dram
circuit
row
correction
Prior art date
Application number
PCT/JP1998/002476
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English (en)
Japanese (ja)
Inventor
Hirotsugu Kojima
Kenji Kaneko
Nobuyuki Takei
Original Assignee
Hitachi, Ltd.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi, Ltd. filed Critical Hitachi, Ltd.
Priority to JP2000552676A priority Critical patent/JP3904138B2/ja
Priority to AU75501/98A priority patent/AU7550198A/en
Priority to PCT/JP1998/002476 priority patent/WO1999063540A1/fr
Priority to TW088105230A priority patent/TW436724B/zh
Publication of WO1999063540A1 publication Critical patent/WO1999063540A1/fr

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Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
    • H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
    • H03M13/13—Linear codes
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
    • G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
    • G06F11/1008—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices

Definitions

  • the present invention relates to a DVD (Digita 1 Versatile Disk) and a CD-ROM (Compact) using a dynamic random access memory (hereinafter referred to as DRAM) as a data buffer.
  • DRAM dynamic random access memory
  • Disk read only memory or a data processing device including a reading device for error correction which can cope with both, and a processing method.
  • DVD drive device As a next-generation personal computer peripheral device, a DVD drive device is attracting attention.
  • the DVD drive that replaces the currently installed CD-ROM is a practically essential requirement to be able to support the CD-ROM that has been widely used. I have.
  • When configuring devices that reproduce signals read from the disks of the CD-ROM and DVD drive devices it is an important issue to develop components that can handle both of them. At this time, the remarkable difference between the recording format of DVD and that of CD-ROM is the S road when developing the configuration means that can cope with both.
  • FIG. 19 (a) is an arrangement diagram of time-series data after CD-ROM demodulation
  • FIG. 19 (b) is a format diagram of an error correction code of CD-ROM data.
  • the signal read from the disc passes through a demodulation circuit and becomes an 8-bit (1 byte) time-series signal as shown in Fig. 19 (a).
  • One byte of subcode followed by 32 bytes of data is called a frame.
  • One section consists of 98 frames.
  • One section consists of 98 subframes starting with special subcodes SO and S1 that indicate the start of the section, and a subcode is a group of meaningful data written in one section. ing.
  • Figure 19 (b) shows the data input in chronological order, with one frame arranged on one line.
  • the data for one symbol is indicated by (s, f, b), where s is the section number, f is the frame number, and b is the byte number.
  • FIG. 20 is a format diagram of an error correction code of CD, CD-ROM specified by the standard.
  • C 1 and C 2 are correction units for double protection, and are both read-solomon error correction codes with one byte as one symbol.
  • Figure 20 shows the delay relationship between the data supplied assuming the time required for correction to be zero, the data input to C1 and C2 error correction, and the data output after correction.
  • the rectangle with the number is a delay circuit that applies the frame delay of that number. Inverter indicates all bit inversion.
  • FIG. 21 (a) is a diagram showing time-series data after demodulation of the DVD code
  • FIG. 21 (b) is a format diagram of the error correction code of the DVD data.
  • the signal read from the disk goes through a demodulation circuit to become an 8-bit (1 it) time-series signal as shown in Fig. 21 (a).
  • the unit of correction is a matrix of 18 2 columns and 208 rows, which is called an ECC (Error Correction Code) block.
  • the ECC block is a lead-solomon error correction code that uses 8 bits (1 byte) as one symbol, and has a row direction (inner code parity) and a column direction (outer code parity). This is a product code in which parity is independently added to.
  • the data of one symbol is indicated by (brc).
  • b is the block number
  • r is the row number
  • c is the column number.
  • (b, r, 2) ⁇ ⁇ ⁇ (b, r, 18 1) is defined as one line, and each line is composed of the main data of 17 2 symbol and the inner code parity of 10 symbols. ing.
  • the 208 symbols (b, 0, c), (b, 1, c), (b, 2, c), ... (b, 200, c) are 1 It consists of 92 symbol body data and 16 symbol outer code parity. However, one row of outer code parity is inserted in time series with respect to 12 rows of main data. Error correction is completed by executing inner code correction in 208 rows in row units and outer code correction in 1832 columns in column units, and performing erasure correction as necessary.
  • the error correction processing for CD_ROM and DVD is the first error correction processing that can execute data input in chronological order without greatly changing the order. It can be said that this is a combination of the second correction processing that can be executed first after accumulating data for a period of time.
  • the first correction process is the C1 correction process for CD-ROM, the inner code correction process for DVD.
  • the second correction process is the C2 correction process for CD-ROM, and the outer code correction for DVD. Processing.
  • Such an error correction format is widely applied not only to other recording media but also to broadcasting media such as digital television receivers.
  • CD-ROMs have 2 kBytes to 4 kBytes of SRAM
  • DVDs have 256 kBytes of RAM.
  • a 2 kByte DRAM has been used.
  • DRAM instead of SRAM is used for the DVD playback device because of the economical reason of reducing costs.
  • the nofee memory be composed of DRAM. Also, we want to share the DVD memory with the DVD-ROM and the CD-ROM so that the DVD-ROM drive can read the CD-ROM as well. In addition, the DRAM has a high speed access within the same row address, but a random access across different row addresses is extremely slow.
  • an object of the present invention is to solve these conventional problems, to use high-speed access in the same row address of DRAM, and without using particularly high-speed and expensive memory.
  • Inexpensive configuration writing data read from media to non-volatile memory, reading for DVD, CD-ROM first and second correction processing And to provide a data processing device and a processing method suitable for writing. Disclosure of the invention
  • the data accessed by the writing from the input circuit to the DRAM and the reading from the DRAM for the second correction processing have an appropriate number of bits.
  • Each unit is allocated in the same ROW address on the DRAM, and in each access, the ROW address and the column address of the ROW are continuously issued for the number of addresses. It is characterized by performing DRAM access control.
  • FIG. 1 is a block diagram of a data processing device according to a first embodiment of the present invention.
  • FIG. 2 is a detailed block diagram of the input circuit in FIG.
  • FIG. 3 is a detailed block diagram of the first data rearrangement circuit and counter in FIG.
  • FIG. 4 is a timing chart illustrating the operation of the input circuit for the CD-ROM signal.
  • FIG. 5 is a diagram showing an example of data allocation on an 8-bit word DRAM of CD-ROM data.
  • FIG. 6 is a diagram showing an example of data allocation on an 8-bit word DRAM of DVD data.
  • FIG. 7 is a configuration diagram showing one embodiment of the second data rearranging circuit of the present invention.
  • FIG. 8 is a diagram showing an example of data allocation on 16-bit / lead DRAM of CD-ROM data.
  • FIG. 9 is a diagram showing an example of data allocation on 16 bits / code DRAM of DVD data.
  • FIG. 10 is a configuration diagram showing another embodiment of the second data rearranging circuit of the present invention.
  • FIG. 11 is a diagram showing an example of data allocation on CD-ROM data on a 32-bit Z word DRAM.
  • FIG. 12 is a diagram showing an example of data allocation on a 32-bit word DRAM of DVD data.
  • FIG. 13 is a configuration diagram showing a first embodiment (for 8 bits / word DRAM) of the output circuit in FIG.
  • FIG. 14 is a configuration diagram showing a second embodiment (for 16 bits / mode DRAM) of the output circuit in FIG.
  • FIG. 15 is a configuration diagram showing a third embodiment (for a 32-bit Z-mode DRAM) of the output circuit in FIG.
  • FIG. 16 is a configuration diagram showing an embodiment of the address generation circuit in FIG.
  • FIG. 17 is a block diagram of an embodiment of a CD-R OMZD VD reproducing apparatus to which the present invention is applied.
  • FIG. 18 is a configuration diagram showing an embodiment of the data processing circuit of the present invention.
  • FIG. 19 is a format diagram of time-series data after CD-ROM demodulation and error correction codes of CD-ROM data.
  • FIG. 20 is a diagram showing the standard of error correction and deinterleaving of CD-ROM.
  • FIG. 21 is a format diagram of the time-series data after the CD-ROM demodulation and the error correction code of the CD-ROM data.
  • FIG. 22 is a block diagram of a data processing device S showing a second embodiment of the present invention.
  • FIG. 23 is a flowchart of the priority determination routine of the microprocessor in FIG.
  • FIG. 24 is a flowchart of a writeaccess processing routine from the demodulation circuit in FIG.
  • FIG. 1 is a block diagram of a data processing device according to a first embodiment of the present invention.
  • DRAM 18 used for buffering data, input circuit 11 and output circuit Route 12, buffer registers 14 for data processing are interconnected via an internal bus 13.
  • the data transfer request signal from each is input to the priority determination circuit 16, the data according to the determination result is output to the internal path 13, and the address generation access control circuit 17 An address is generated in accordance with the result of the priority determination, and the access control of the DRAM 18 is performed.
  • the input circuit 11 performs a pre-processing suitable for the medium on the signal input from the medium, and accumulates the signal until the number of words to be written into the DRAM 18 is reduced.
  • the term “collective word count” refers to the number of data words written continuously in the same row address by synchronous DRAM or normal DRAM page mode access. Point.
  • the location and value of the found error are corrected by accessing DRAM 18 in symbol units.
  • the corrected data is determined through the output circuit 12 It is sent to the subsequent stage using the specified protocol.
  • the output circuit 12 also sends a data request signal to the priority determination circuit 16 as necessary.
  • the priority determination circuit 16 determines the priority of the above-mentioned memory access request, and permits access in descending order of priority, thereby improving efficiency and restricting real-time processing. Operate the system while observing the conditions. For example, requests from the input circuit 11 are usually processed with the highest priority. This is because the data entered must not be lost before it is processed. In addition to the illustration, refresh of DRAM 18 is also a high priority request.
  • FIG. 2 is a detailed block diagram of the input circuit in FIG.
  • a preferred embodiment of the input circuit 11 is configured as shown in FIG.
  • the data input from the CD-ROM through the demodulation circuit is in 1 symbol (8 bit) units, and a clock synchronized with that and a signal indicating the beginning of the frame are input.
  • the demodulated data passes through the first data rearrangement circuit 111, is rearranged in an order suitable for C1 correction, and is sent to the C1 correction circuit 114 and the second data rearrangement circuit 112. .
  • the C 1 correction circuit 1 14 may perform all the correction processing, but may perform at least the syndrome generation and transfer the syndrome to a correction operation circuit (not shown).
  • the frequency of errors in a normal CD-ROM disc is not as high as about 1 symbol out of 1,000 symbols. Since the syndrome of an error-free data string becomes zero, if only the erroneous syndrome is transferred to the correction processing circuit, the correction processing circuit is used more efficiently. This is what happens.
  • demodulated data demodulated data, a demodulation clock synchronized with the demodulated data, and a signal representing the beginning of an ECC block are input.
  • the row address signal is input, it can be used for rescue if the row address becomes irregular in the ECC block for any reason.
  • the error correction of the DVD can be executed by inputting the signals to the inner code correction circuit 115 in the order of the signals input in time series from the demodulation circuit. Therefore, unlike the case of the CD-ROM, there is no need for the first data sorting circuit 111. By devising the addressing of the DRAM, the second data rearrangement circuit 112 may not be necessary.
  • FIG. 3 is a diagram showing a configuration example of a first data rearrangement circuit and a counter of the CD-ROM demodulated signal in FIG. 2, and FIG. 4 is a timing chart thereof.
  • the demodulated data is input in synchronization with the demodulation clock.
  • the ternary counter 1 19 counts the demodulation clock of the CD-ROM and outputs the count value i.
  • the count value i is reset each time the frame head signal is input, and outputs a value from 0 to 32.
  • i 0
  • CD-ROM demodulated data is output as it is because it is a subcode.
  • i l, 3, 5, ⁇ ⁇ ⁇ 11, 17, 19, ⁇ ' ⁇ 27, the data does not require one frame delay as shown in Fig. 20. Therefore, the terminal a is selected by the selection circuit 122 and output.
  • i 13, 15, 29, 31 the terminal b is selected by the selection circuit 122 and inverted data is output.
  • the signals output to terminals a, b, c, and d in Fig. 3 are shown by terminals a, b, c, and d in Fig. 4.
  • the output of the selection circuit 122 is shown as C I data to be corrected, and is data in an order suitable for C 1 correction.
  • the second data rearrangement circuit 112 needs to be devised so as to be adaptable to the configuration of the DRAM used as a knocker.
  • DRAMs are available in 8-bit / 1-word, 16-bit / 1-word, and 32-bit / 1-word configurations. Since the unit of correction is 1 symbol, that is, 8 bits, in both CD—ROM and DVD, access is made to 1, 2, and 4 symbols according to the word length of the DRAM.
  • the second data rearranging circuit 1 12 is not necessary, and the C 1 corrected data is left unaltered in the DRAM addressing. Just write.
  • FIG. 5 is a diagram showing a method for allocating data on an 8-bit / word DRAM of CD-ROM data. (0, 0, 0), (—1, 97, 1), (0, 0, 2),..., (1-1, 97, 31) output as CI corrected data Are written to the addresses H'00, H'021, H'042, ..., H'3FF in the first ROW of the DRAM.
  • the data (s, f, b) is the byte number of (s: section number, f: frame number, b: byte number)-12, 13, 14,
  • the data of 15, 28, 29, 30, and 31 are all bits inverted, but it is not important that the data is inverted data in particular.
  • H'X used in address notation indicates that X is represented in hexadecimal.
  • the C 1 corrected data (0, 1, 0), (0, 0, 1), (0, 1, 2),..., (0, 0, 31) of the next frame is the DRAM Are written to the addresses H'400, H'412, H'424, ..., H'7FF of the second row.
  • the next is the first ROW
  • a series of data required for C2 correction is arranged in 1F.
  • a series of data for C2 correction is written in FF. Since the address is continuous, the configuration of the address generation circuit is easy. In this embodiment, it is described that byte numbers 28, 29, 30 and 31 are also written in the DRAM. However, since these are parity for C1 correction, C2 correction is performed. There is no need to write unless there is a reason such as performing C1 correction again after the '.
  • the deinterleaving can be realized by the addressing of the DRAM reading.
  • the interleave in FIG. 20 includes a 2-byte delay everywhere.
  • the above access is not necessarily efficient because the first row and the third row are alternately accessed, but the processing of the day interleave required for output (see Fig. 20) is performed. It has no special hardware and is realized only by DRAM addressing, which is effective for simplified configuration and cost reduction.
  • FIG. 13 is a configuration diagram showing a first embodiment (for 8-bit / word DRAM) of the output circuit in FIG.
  • the first ROW and the third ROW shown in Fig. 5 And read them one by one at a time.
  • the read data is transferred to the output circuit shown in Fig. 13 via the internal bus. Data transfer is performed in synchronization with the read clock, and the address of the register to be written is specified by the input binary quaternion counter 131 in the output circuit.
  • the binary quaternary counter 13 1 is 0, and is incremented by 1 each time a read clock is input.
  • FIG. 6 is a diagram showing an example of data allocation on DVD data bit / word DRAMs according to the present invention.
  • FIG. 6 shows a data allocation method when the same DRAM is used for error correction of a signal read from DVD.
  • the data (0, 0, 0), (0, 0, 1),... (0, 0, 181) of the first row of the ECC block input in chronological order from the demodulation circuit are added to the DRAM. From the first row to the sixth row.
  • the first row stores the data (0, 0, 0) and the data (0, 0, 31) before the address H'00001F and H'001F.
  • the next data (0, 0, 32) to (0, 0, 63) are stored from the address H'0400 to H, 04IF of the second ROW.
  • the addresses of the 6th ROW, H'1 4 16 It is used area.
  • the data (0, 1, 0), (0, 1, 1), (0, 1, 181) of the second row of the ECC block, which is input in time series from the demodulation circuit, are Returning to the first row of the DRAM, data is written from the address H'0202 to H'003F of the continuation of the data in the first row. Similarly, the data in the third to third rows of the ECC block are sequentially written to the first to sixth rows of the DRAM.
  • lines 3 to 64 are the data from the 7th row of DRAM to the 12th row
  • the data in lines 65 to 96 are data in the DRAM.
  • the data in the 16th row from the first row to the 26th row in the DRAM are changed from the 25th row to the 30th row in the DRAM.
  • the data from the 31st row to the 36th row of AM and the remaining data from the 19th row to the 208th row are the 3rd row power of the DRAM.
  • the data of the first and second lines of the ECC block are sequentially written to the 42nd ROW in the same manner as the data written in the 1st ROW to the 6th ROW of the DRAM, respectively.
  • the last 37th ROW to the 42nd ROW are virtual areas of the ECC block 209 to 228 which are not originally present in order to maintain the regularity of the address. Are assigned. In practice, no such data is entered, so this area is also unused.
  • a series of data necessary for outer code correction is (b, 0, c), (b, 1, c),... (B, 207, c).
  • (0, 0, 0), (0, 1, 0),... (0, 31, 0) are stored in the first row of the DRAM. Up to 32 symbols can be read continuously without reissuing the OW address. Therefore, to read a series of data (0, 0, 0), (0, 1, 0),... (0, 207, 0) necessary for outer code correction, the following steps must be taken. Just do it.
  • Steps 1 through 6 issue a ROW address and can continue for 32 bytes, but the last seventh step issues an ROW address and issues a 16 Reading over bytes is not desirable because it accesses unused area.
  • Reading of the second and subsequent columns of the ECC block can be performed in the same manner.
  • the read of the corrected data may be performed in exactly the same order as the first write.
  • FIG. 6 shows the data allocation for only one ECC block.However, with a normal device, data of at least 3 ECC blocks is usually stored in DRAM and processed. It is a target. That is, the first ECC block is for writing data, the second ECC block is for access for correction, The third ECC block is divided into readouts for output, and the first, second, and third ECC blocks are used in a pipeline manner each time processing is completed. Things. It is not uncommon to accumulate more than 4 ECC blocks of data and process them sequentially in order to allow time for error correction.
  • FIG. 7 is a diagram showing an embodiment of the second data rearranging circuit when a 16-bit / 1-word DRAM is used.
  • the data of 6, •. 32) is output to the lower byte without delay.
  • data (0, 0, 0) is output in combination with data (0, 3, 1).
  • the two bytes (16 bits) output in combination after receiving the delay in the second data rearrangement circuit are written to the first DRAM.
  • FIG. 8 is a diagram showing a method of allocating data on 16-bit lead DRAM of CD-ROM data.
  • the day interleaving can be realized by the DRAM addressing of the DRAM reading.
  • the deinterleave in FIG. 20 includes a 2-knot delay everywhere.
  • this is the first and third, the second and fourth, the third and fifth, the fourth and sixth, the fifth and seventh, the sixth and eighth, the seventh and first, Or it is equivalent to the difference between the 8th and 2nd ROW. Therefore, in FIG. 20, (0, 0, 0), (0,
  • Output is achieved by repeating the ROW address update and reading in the 4-byte ROW address six times as follows.
  • the addressing can be divided into two sets, the first row and the third row, and an output circuit as shown in Fig. 14 can be added to realize interleaving. .
  • the first row and the third row are read out in six words each.
  • the read data is transferred to the output circuit shown in Fig. 14 via the internal bus. Data transfer is performed in synchronization with the read clock, and the register register to be written by the binary counter 14 1 on the input side in the output circuit Specify the address.
  • the binary counter 11 is 0, and is incremented by 1 each time a read clock is input.
  • connection destination of the output of the decoder 146 on the output side is not specified. It is designed to be In the present embodiment, the input side is devised so that data is stored in the latch circuit 144 in the order of output. Therefore, since the output is a sequential access, a shift register format may be used. It is also possible to design such that the input side is stored in the order read from the DRAM and the output is output in an appropriate order.
  • FIG. 9 is a diagram showing a data allocation method when the same 16-bit word DRAM is used for error correction of a signal read from a DVD.
  • the data (0, 0, 0), (0, 0, 1),... (0, 0, 181) of the first row of the ECC block input in time series from the demodulation circuit are converted to the DR.
  • two consecutive symbols are combined into 16-bit data. 1st R OW
  • the data H (0,0,0), data ((0,0,0), (0,0,1)) and ((0,0,3) 0), (0, 0, 31) ⁇ are stored.
  • the data in the ECC block 17th line to 32nd line are changed from the 7th ROW to the 12th ROW of the DRAM, and the data in the 33rd line; From the 1st 3rd row of the AM to the 1st row, the last 19th row!
  • the data on line 208 of the ECC block is changed from the 73rd row of the DRAM to the 78th row of the DRAM, and the data on the 32nd line of the ECC block is transferred from the first row of the DRAM to the first row of the DRAM.
  • a series of data necessary for outer code correction is (b, 0, c), (b, 1, c),... (B, 207, c).
  • (0, 0, 0), (0, 1, 0), ... (0, 15, 0) are stored in the first row of the DRAM. Up to 16 symbols can be read continuously without re-issuing the ROW address.
  • a force that is a two-byte Z-word can simultaneously read (0, 0, 1), (0, 1, 1), ... (0, 15, 1) at this time. Therefore, it is efficient to process the outer code correction of the 0th column and the 1st column in parallel.
  • the method of generating the DRAM address can be easily configured as in the case of the 8-bit DRAM.
  • the read of the corrected data may be performed in exactly the same order as the first write.
  • Fig. 9 shows the data allocation for only one ECC block, as in Fig. 6, but with a normal device, data of a minimum of 3 ECC blocks is stored on the DRAM as described above. Generally, it is processed.
  • FIG. 10 is a configuration diagram of a second data rearranging circuit according to the second embodiment of the present invention, showing a case where a 32-bit / 1-bit DRAM is used.
  • the data of 3) is output to the least significant byte without delay, for a total of 4 bytes.
  • data (0, 0, 0) (0, 3, 1) (0, 8, 2) (0, 11, 1, 3) are combined and output.
  • the second data rearrangement circuit receives the delay and combines and outputs 4 bytes (32 bits) to one word of DRAM.
  • FIG. 11 is a diagram showing a method of allocating data on 32 bits / word DRAM of CD-ROM data.
  • the data of (0,0,0), (0,3,1), (0,8,2), (0,11,3), which is a combination of (0,0,0,0), is converted to ⁇ (0,0,0,0) 0), (0,3,1), (0,8,2), (0,11,3) ⁇ , the 16 words ⁇ (0,0,0) output in time series ), (0,3,1), (0,8,2), (0,11,3) ⁇ , ⁇ (0,0,4), (0,3,5), (0,8, 6), (0,11,7) ⁇ , ..., ⁇ (0,0,28), (0,3,29), (0,8,30), (0,11) , 3 1) ⁇ is written to the addresses H ′ 0 0 0, H ′ 0 09, H ′ 0 1 2, ⁇ ′ ⁇ H ′ 0 3 F in the first ROW of the DRAM.
  • the deinterleaving can be realized by the DRAM read addressing.
  • the interleave of FIG. 20 includes a 2-byte delay everywhere. This means that on the DRAM, the first and third, the second and fourth, the third and fifth, the fourth and sixth, the fifth and seventh, the sixth and eighth,. And the first, or the difference between the 16 and the 2 ROW. Therefore, (0, 0, 0), (0, 3, 1), (0, 24, 6), (0, 27, 7), (0, 62, 1) in FIG.
  • Output of (1, 7, 27) is achieved by repeating the update of the row address and reading in the 3-word row address twice as follows.
  • FIG. 15 is a configuration diagram (for 32 bits / word DRAM) of an output circuit showing a third embodiment of the present invention.
  • a day interleave circuit as shown in Fig. 15 is required.
  • the read data is transferred to the output circuit shown in Fig. 15 via the internal bus.
  • Data transfer is performed in synchronization with the read clock, and the hexadecimal counter 152 on the input side in the output circuit specifies the address of the register to be written. Since there are four symbols per word, four latches to be written are specified at the same time.
  • the hexadecimal counter 152 is 0 when the first data is input, and is incremented by 1 each time a read clock is input.
  • the output of the decoder 15 1 has six lines from 0 to 5 corresponding to the value of the counter 15 2 so that the data is stored in the 24 output latches 15 3 in the order of output. Issues a write enable. After all data has been stored in latch 15 Each time a tick is input, one symbol of data is output.
  • connection destination of the output of the decoder 155 on the output side is not explicitly shown in FIG. 15, it is output in order from the top corresponding to the count value of the binary counter 156 on the output side. It is designed to:
  • the input side is devised so that data is stored in the latch circuit in the order of output. Therefore, since the output is sequential access, a shift register format may be used.
  • FIG. 12 is a diagram showing a data allocation method when the same 32-bit word DRAM is used for error correction of a signal read from DVD.
  • the data (0, 0, 0), (0, 0, 1), (0, 0, 181) of the first row of the ECC block input in time series from the demodulation circuit are converted to DR Write sequentially to the first to sixth rows of AM.
  • 32 consecutive bits 1 mode data is obtained by combining four consecutive symbols.
  • the first ROW contains data ⁇ (0,0,0), (0,0,1), (0,0,2) from address H'00.00 to H'00.07. ), (0, 0, 3) ⁇ force> ((0, 0, 28), (0, 0, 29), (0, 0, 30), (0, 0, 31)) ⁇ Is stored.
  • the following data ⁇ (0,0,32), (0,0,33), (0,0,34), (0,0,35) ⁇ force> ( ⁇ 0,0,6) 0), (0, 0, 6 1), (0, 0, 6 2), (0, 0, 6 3) ⁇ are the addresses of the second row H '0 0 4 0 Stored by 0 4 7 Write data sequentially from the top of the third, fourth, fifth, and sixth ROWs.
  • the address H'0 of the sixth ROW H'0 14 F is an unused area.
  • the data of the second row of the ECC block, which is successively input from the demodulation circuit, is ⁇ (0,1,0), (0,1,1), (0,1,2), (0,1) , 3) ⁇ ,... ⁇ (0, 1, 178), (0, 1, 179), (0, 1, 18 0), (0, 1, 18 1) ⁇
  • the address of the continuation of the data in the first row is H'0 0 8 to H '0 0 0 F.
  • the second row address H' 0 0 4 8 The data is sequentially written to the sixth ROW address H'004F.
  • the data in the third to sixteenth lines of the ECC block are sequentially written to the first to sixth rows of the DRAM.
  • the data in the ECC block 17th line to 32nd line is the data from the 7th ROW to the 12th ROW of the DRAM, and the data in the 33rd line to the 48th line is the data in the DRAM.
  • the data from the 13th ROW to the 18th ROW, and the last data from the 19th row to the 28th row are ECC from the 15th ROW to the 15th ROW of the DRAM
  • the data in the first and second blocks of the block are written sequentially in the same way as the data in the first to sixth rows of the DRAM are written to the second and third rows.
  • FIG. 2 an example is shown in which all or part of the inner code correction is executed before storing the data in the DRAM.However, the data allocation shown in FIG. According to this, a series of 18 2 symbols required for inner code correction are stored in the same ROW address of the DRAM in units of 32 symbols, and up to 32 symbols without re-issuing the ROW address. Data can be read continuously, so even if the inner code is corrected after storing the data in DRAM, Good.
  • a series of data necessary for the outer code correction is (b, 0, c), (b, 1, c),... (B, 207, c).
  • (0, 0, 0), (0, 1, 0), ⁇ '' (0, 7, 0) are stored in the first row of the DRAM, and R Up to 8 symbols can be read continuously without re-issuing the OW address.
  • the DRAM is a 4-byte word.
  • the first row (0, 0, 1), (0, 1, 1), ... (0, 7, 1), the second row U (0, 0, 2), (0, 1, 2), ... (0, 7, 2), 3rd system 1 "(0, 0, 3), (0, 1, 3), ⁇ ⁇ Since (0, 7, 3) can also be read out at the same time, it is efficient to process the outer code correction in the 0th to 3rd columns in parallel.
  • the method of generating the address of the DRAM can be configured easily as in the case of the 8-bit word DRAM.
  • the read of the corrected data may be performed in exactly the same order as the first write.
  • Fig. 12 shows the data allocation for only one ECC block, as in Fig. 6, but with the usual equipment, at least 3 ECC blocks of data are stored on the DRAM as described above. Generally, the data is accumulated and processed.
  • FIG. 16 is a configuration diagram of an address generation circuit applied to each embodiment of the present invention.
  • the ROW address register 163, the COLT dress register It is composed of 163a, register 0 and register n (164).
  • the values of the ROW address register 163 and the COL address register 1663a are respectively passed through the mask / offset circuit 1667. Selected by the multiplexer 1668 and input to the DRAM address terminal.
  • the mask / offset circuit 1666 is configured using a general-purpose ALU (Arithmetic Logic Unit) and a register.
  • ALU performs bitwise logical operations (logical addition, logical AND, exclusive OR, etc.) and numerical addition / subtraction, so masks that fix a part of the address value to 0 or 1 and constant values
  • the offset for adding the sum can be easily realized.
  • the first input of the adder circuit 16 5 is the row address register 16 3, the address register register 16 3 a, the register 0 to the register n (16 4 ) And input it to one of the adders 1 65.
  • the second input path selects one of the registers n (1 64) from register 0. And input it to the other of the adders 1 65.
  • the result of the addition is written to one of the registers 164 and 163 via the output bus. Also, the values can be directly stored in registers 1664 and 1663 through the output bus.
  • the address generation circuit is given an operation procedure by a sequence control circuit that receives the result of the priority determination circuit.
  • an appropriate input circuit according to the number of bits of the DRAM word, particularly the second data rearrangement circuit in the CD-ROM, and an appropriate output circuit, particularly the CD-ROM By providing a deinterleave circuit, the access to the DRAM can be integrated into a continuous read access to the same row address. As a result, a high transfer rate using page mode access can be obtained, and a low-speed DRAM, that is, a low-cost DRAM, can be used effectively.
  • the larger the number of bits per word of DRAM the more the number of access cycles can be reduced.
  • there are disadvantages such as an increase in the number of pins and an increase in the scale of the input / output circuit. This point is traded off.
  • the configuration of the DRAM on the same LSI is almost the same as that of the external DRAM described above, but it is most preferable that the bit is 8 bits per mode.
  • there is no need for address multiplexing that is, a load address and a column address can be issued simultaneously.
  • the speed of reading the data in the same address while changing the column address is sufficiently fast.
  • a second data rearrangement circuit that collects the symbols of the symbols is unnecessary.
  • FIG. 17 is a diagram showing an example of an optical disc reproducing apparatus capable of reproducing CD-ROMs and DVDs embodying the present invention.
  • the entire electrical system is controlled by the microcontroller 174.
  • the laser control circuit 1778 operates to control the output of the laser diode 1772 through the laser
  • the signal processing circuit 1 7 9 is an actuator Controls mechanical systems through motor dryno 180.
  • the signal detected by the photodetector 173 is input to the servo processing circuit 179 and the sampling / binarization circuit 182 through the analog signal processing circuit 177.
  • the signal input to the servo signal processing circuit 179 is tracking and focus error information, and the source signal for fine adjustment of the stage position and lens, and adjustment of the spindle motor speed. Used as Sampling
  • the binarized information is the disk information to be reproduced.
  • a clock synchronized with the data is reproduced from the signal of the photodetector 173, and the clock is used to perform sampling and binarization to obtain a digital signal.
  • the synchronization pattern specified in the standard is detected from the obtained digital signal, and the start timing of the CD-ROM or DVD frame is identified.
  • the microcontroller 184 monitors the synchronization status of the playback clock, the synchronization pattern detection status and the synchronization status, and controls the actuator 171, servo, laser, and CD-R. ⁇ Used for OM / DVD mode setting.
  • the binarized serial digital signal is converted to a 17-bit or 16-bit parallel signal depending on the CD-ROM / DVD mode setting.
  • the signal is demodulated and 168 demodulated and input to the input circuit shown in the above-described embodiment.
  • three bits are added for connection to 14 bits of Eight-to-Fourteen Modulation (EFM) modulation, so the outputs of the SZP conversion circuits 18 5 and 18 6 It is 17 bits.
  • EFM Eight-to-Fourteen Modulation
  • the operations of the input circuit, the output circuit, the address generation circuit, the priority determination circuit, the error correction processing circuit, the DRAM, and the like are the same as those of the embodiment described above.
  • the corrected data sent through the output circuit is sent to the protocol control circuit 1 According to 87, it is transferred to 188, such as a personal computer, video / audio playback device, etc., using the specified protocol.
  • the microcontroller 184 selects the laser diode 172 assuming that a CD-ROM or DVD is loaded when the disc is loaded, and performs servo processing and error correction processing. Operate 1 9 2 etc. If the assumption is different from the loaded disc, the information monitored by the microcontroller 184, such as no clock playback, no sync pattern detection, and no error correction, And switch to playback mode of the other disk. In this way, the medium is automatically determined.
  • the data processing circuit 15 shown in FIG. 1 may be constituted by a parallel processor. Assuming that the number of processor elements constituting the parallel processor is n, n sets of CDs—the C1 code and C2 code of ROM, the inner code of DVD, and the received code of outer code are input in parallel. It is efficient. That is, data of n rows in the case of the inner code of a DVD and n columns in the case of the outer code are input to n processor elements, respectively, to perform parallel processing.
  • 1 is a configuration diagram of a data processing circuit according to an embodiment, showing the configuration of a buffer register and a data processing circuit when the number of processor elements PE is eight.
  • DRAM is 16-bit words, so the internal bus is also assumed to be 16-bit wide. Also, the data allocation on the DRAM is as shown in FIG. 8 in the case of CD-ROM playback, and as shown in FIG. 9 in the case of DVD playback.
  • the register is a 1-byte register having 8 rows and 8 columns and 1 input and 2 outputs.
  • the data input terminal DB [15: 0] is before Is connected to the internal bus described above, and the row write enable signal WAR0 to WAR7 is selected by the row, the column write enable signal WACO is set by the WAC3 to the column selected by WAC3.
  • Data is stored in two byte registers.
  • reading is output in parallel from eight registers arranged in the row or column direction.
  • the control terminal RZC specifies the row or column direction, and in the case of the row direction, the data processing circuit reads one byte and eight bytes of data selected from RR7 from RR7 and reads one byte at a time. Is supplied to PE7 from the processor element PE0. In the column direction, data of 8 bytes is read from one row selected from RC0 to RC7, and the data is processed one byte at a time. 0 power is supplied to PE 7.
  • the 182 bytes required for the inner code correction are from the lower address H'0 to H'F of the first ROW to the sixth ROW of the DRAM every 32 bytes. Are stored at consecutive addresses.
  • the address H '0 0 0 0 is set to the address H' 0 0 3 in the first row of the knock-off register. Repeat this with 8 bytes of data of 11'0 013 on the second line of the buffer register, and address H'0 0 70 0 to H'0 0 73 Transfers 8 bytes of data to the 8th line of the buffer register.
  • the first 8 bytes of the ECC block from line 1 to line 8, were transferred from line 1 to line 8 of the knock-off register.
  • Select the C side that is, the column side, with the R / C pin, and sequentially transfer data of 8 bytes each from RC0 to RC7 to PE7 from processor element PE7.
  • the power of the first line of the buffer register >
  • the data from the first row to the eighth row are sequentially transferred to the processor elements PE0 to PE7, respectively.
  • the buffer register is now empty, so the next address of the first row of the DRAM is again H'0 0 0 4 and H '0 0 7 and H' 0 0 1 4 H'017, ...
  • H'0074 A total of 64 bytes from the input to the processor, H'0777, are passed through the knock-off register to the processor element. Transfer from PE 0 to PE 7. By repeating this, all necessary data is transferred from the processor element PE0 to PE7. In the data processing circuit, the inner code correction can be executed in parallel by eight processor elements PE0 to PE7.
  • the 208 bytes required for outer code correction are the same lower order of 61 60 ⁇ from the first ROW of the DRAM to the 7810th ⁇ of the DRAM every 16 bytes. It is stored at the address.
  • the address H'0 0 0 0, the data 8 of H '0 0 3 is placed in the first line of the register, and the address H' 0 0 1 0
  • This is repeated for the second row of the buffer register with 8 data of the data of H '013 and the data of H' 0 0 7 3 Transfers 8 bytes of data to the 8th line of the knocker register.
  • the first eight bytes from the first line to the eighth line of the ECC block were transferred to the first to eighth lines of the buffer register. This is also equivalent to the first eight bytes of the ECC block from the first row to the eighth row.
  • the C side that is, the column side
  • the R side that is, the row side
  • RR 0 to RR 7 were sequentially selected.
  • the data in the first to eighth columns of the register are sequentially transferred to the processor elements PE0 to PE7, respectively.
  • the buffer register is empty, the next address in the 7th ROW of the DRAM will be H'0600, H'0600, H'0700, and so on.
  • the outer code correction can be executed in parallel by the eight processor elements PE0 to PE7.
  • Fig. 18 describes the parallel processing of CD-ROM and DVD error correction, but the operation for DVD in particular is used to correct the error in the general product code of a lead solomon. Can be widely applied.
  • the present invention can easily cope with other media.
  • the data format of the error correction is the same as the data format of the CD-ROM or DVD described in the above embodiment, regardless of whether it is storage media or broadcast media. Therefore, the address generation circuit, priority determination circuit, etc. can be easily applied to different formats by only slightly changing the sequence control.
  • FIG. 22 is a configuration diagram of a data processing apparatus showing another embodiment of the present invention, in which the processing method of the present invention is realized by software.
  • the data processing apparatus of the present invention is configured by hardware.
  • the buffer register 14 can also be realized by software for a processor such as a microcontroller.
  • FIG. 22 shows a hardware configuration that is assumed to be realized by software on the microcontroller 22.
  • the main memory 222 and the DRAM interface circuit 222 are connected via a common bus, and the input circuit 211 and the output circuit 222 are connected via a peripheral path.
  • controller 2 23 Connected to controller 2 23.
  • the microcontroller 223 monitors a register (DRAM access request status register Regst) for requesting access to the DRAM 226 for each access factor. Perform appropriate processing according to the priority of the request.
  • the DRAM access request status register is a register that indicates the presence or absence of a request as an access factor, and can be realized by hardware or virtually by software. Good.
  • the input circuit 222 has a register of one symbol or more.
  • FIG. 23 is a flowchart of the priority determination routine of the microprocessor, which monitors the DRAM access request status and starts the necessary processing subroutine as needed. Is shown.
  • Steps 230 and 231 read the contents of the DRAM access request status register. (Steps 230 and 231), check the presence or absence of an access request according to the priority, and if there is a request, start a subroutine corresponding to the request, reset the request, and reset the request. Return to reading the data register.
  • the priority shown here is only an example, and it is fully conceivable that the priority may be changed in configuring the system. It may also be changed during the operation of the program.
  • the refresh processing subroutines 23, 2, 24, and 248 manage time using timers, which are peripheral functions of the microcontroller 23, and refresh the DRAM at regular intervals.
  • This is a subroutine that performs
  • the configuration of the subroutines 23, 33, 241, and 249 for performing w r i t e a c c e s s from the demodulation circuits differs depending on the type of medium, the position and method of data on DRAM.
  • Read access processing subroutine for C1 correction (steps 234, 242, 250), read access processing routine for C2 correction (steps 235, 2) 43, 25 1), read processing subroutine for output (steps 23 36, 24 44, 25 2), read and write processing subroutine for correction (step 237, 245, 253) and other read and write processing subroutines (steps 238, 239, 246, 27, 254, 255) Are invoked according to priority.
  • FIG. 24 is a flowchart showing an example of a processing routine of writheaccesss from the demodulation circuit.
  • the data arrangement shown in Fig. 5 will be implemented using a DRAM with an 8-bit data width. Shows a subroutine for writing data into the subroutine.
  • the input data from the demodulation circuit is assumed to be "DATA”, and the position of the data at this time is assumed to be the output "i" of the ternary counter 119 shown in FIG. Data is given.
  • this ternary counter 1 19 can be easily realized by hardware or software.
  • Steps 2 6 7 Since the sub-code processing body is not essentially related to the present invention, the description is omitted. If i is an even number, one frame delay is given (steps 26 2 and 26 3), and if odd, it damages the DRAM without delay (steps 26 2 and 26 8). ). Ooutbuuf in the flow is an array variable that stores 32 bytes of data that will be written to DRAM next. d1ybuuf is an array variable for one-frame delay, and holds the data before one frame (step 2665).
  • step 2622 If the data is an odd number (step 2622), d1ybut [i] one frame before is stored in ooutbuf [i] to be output next (step 270).
  • the data of i 13, 14, 15, 15, 16, 29, 30, 30, 31, 32 is the norm, and as shown in the CD standard of FIG. The parity is inverted for all bits and used for the subsequent processing (steps 264 and 269)
  • the variables row, co 10 and co 1 are variables for DRAM row, initial column, and column address calculation, respectively, and the variables DR AM R OW, DRAM COL, and DRAM DATA are actually DR Row, column address and data issued to AM.
  • the load address of the DRAM increases by one for each frame of the CD, and returns to 0 at an appropriate value (see 271).
  • the initial column address co 10 increases by 32 (H'20 in quaternary notation) for each frame, and returns to 0 when it reaches the maximum value in the same row. (See 272).
  • the column address is actually issued to the DRAM, and the data is simultaneously output to the DRAM to perform writing (steps 271, 272). ). Thereafter, the column address is increased by 33 (H'21) in the same low address, and the remaining 31 bytes are sequentially written (step 274).
  • the data rearrangement circuit realized by the hardware shown in FIG. 3 can be realized by the software. You.
  • the data processing device of the present invention can utilize high-speed access within the same ROW address of DRAM, and is commonly used for error correction of signals from different media. Therefore, it is not necessary to use particularly high-speed and expensive memory, and an inexpensive data processing device can be realized. Furthermore, if the input circuit and output circuit connected to the internal bus are designed to be adapted to the system, the correction processing circuit including DRAM access can be diverted to a different system with only minor changes. This also has the effect of reducing development costs.

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  • Physics & Mathematics (AREA)
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  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Error Detection And Correction (AREA)
  • Optical Recording Or Reproduction (AREA)

Abstract

L'invention concerne un processeur de données équipé d'un circuit d'entrée (11) pour prétraiter des signaux lus sur un support, un premier moyen (16) d'analyse de priorité d'accès à la mémoire vive dynamique, destiné à écrire les résultats prétraités dans une mémoire vive dynamique, un deuxième moyen d'accès (15) à la mémoire vive dynamique, destiné à lire des données dans la mémoire précitée en vue d'une deuxième correction, un troisième circuit de sortie (12) d'accès à la mémoire vive dynamique, destiné à lire des données en vue d'émettre des données corrigées à un étage suivant, et un circuit de commande d'accès (17) constitué de sorte que les premier, deuxième et troisième accès à la mémoire vive dynamique peuvent être stockés dans la même adresse de ligne sur plusieurs mots. Ainsi, le processeur de données ne nécessite pas de mémoire rapide coûteuse, puisque le processeur peut utiliser un accès rapide dans la même adresse de ligne de la mémoire vive dynamique et peut généralement assurer la correction d'erreurs sur des signaux provenant de différents supports.
PCT/JP1998/002476 1998-06-04 1998-06-04 Processeur de donnees et procede de traitement de donnees WO1999063540A1 (fr)

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JP2000552676A JP3904138B2 (ja) 1998-06-04 1998-06-04 データ処理装置および処理方法
AU75501/98A AU7550198A (en) 1998-06-04 1998-06-04 Data processor and data processing method
PCT/JP1998/002476 WO1999063540A1 (fr) 1998-06-04 1998-06-04 Processeur de donnees et procede de traitement de donnees
TW088105230A TW436724B (en) 1998-06-04 1999-04-01 Data process device and process method

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Cited By (2)

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US7024616B2 (en) 2000-06-09 2006-04-04 Hitachi, Ltd. Method for encoding/decoding error correcting code, transmitting apparatus and network
CN109872745A (zh) * 2017-12-05 2019-06-11 南亚科技股份有限公司 动态随机存取存储器及其操作方法

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JPS6226930A (ja) * 1985-07-26 1987-02-04 Nec Corp 誤り訂正復号装置
JPH097365A (ja) * 1995-06-23 1997-01-10 Nec Corp Ｃｄ−ｒｏｍ用ｄｒａｍアドレス生成回路
JPH09115244A (ja) * 1995-10-20 1997-05-02 Hitachi Ltd 記録再生装置及びその集積回路
JPH09259261A (ja) * 1996-03-22 1997-10-03 Toshiba Corp メモリアドレス発生装置及び方法

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JPS6226930A (ja) * 1985-07-26 1987-02-04 Nec Corp 誤り訂正復号装置
JPH097365A (ja) * 1995-06-23 1997-01-10 Nec Corp Ｃｄ−ｒｏｍ用ｄｒａｍアドレス生成回路
JPH09115244A (ja) * 1995-10-20 1997-05-02 Hitachi Ltd 記録再生装置及びその集積回路
JPH09259261A (ja) * 1996-03-22 1997-10-03 Toshiba Corp メモリアドレス発生装置及び方法

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7024616B2 (en) 2000-06-09 2006-04-04 Hitachi, Ltd. Method for encoding/decoding error correcting code, transmitting apparatus and network
US7512867B2 (en) 2000-06-09 2009-03-31 Hitachi, Ltd Method for encoding/decoding error correcting code, transmitting apparatus and network
CN109872745A (zh) * 2017-12-05 2019-06-11 南亚科技股份有限公司 动态随机存取存储器及其操作方法
CN109872745B (zh) * 2017-12-05 2021-05-04 南亚科技股份有限公司 动态随机存取存储器及其操作方法

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