WO1999056313A1 - Dispositif semi-conducteur et son procede de production - Google Patents

Dispositif semi-conducteur et son procede de production Download PDF

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Publication number
WO1999056313A1
WO1999056313A1 PCT/JP1998/001920 JP9801920W WO9956313A1 WO 1999056313 A1 WO1999056313 A1 WO 1999056313A1 JP 9801920 W JP9801920 W JP 9801920W WO 9956313 A1 WO9956313 A1 WO 9956313A1
Authority
WO
WIPO (PCT)
Prior art keywords
wiring board
semiconductor device
reinforcing frame
semiconductor chip
semiconductor
Prior art date
Application number
PCT/JP1998/001920
Other languages
English (en)
Japanese (ja)
Inventor
Noriyuki Takahashi
Seiichi Ichihara
Chuichi Miyazaki
Original Assignee
Hitachi, Ltd.
Hitachi Yonezawa Electronics Co., Ltd.
Hitachi Ulsi Systems Co., Ltd.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi, Ltd., Hitachi Yonezawa Electronics Co., Ltd., Hitachi Ulsi Systems Co., Ltd. filed Critical Hitachi, Ltd.
Priority to PCT/JP1998/001920 priority Critical patent/WO1999056313A1/fr
Priority to JP2000546392A priority patent/JP4038021B2/ja
Priority to KR1020007011386A priority patent/KR20010042682A/ko
Priority to TW088105306A priority patent/TW426870B/zh
Publication of WO1999056313A1 publication Critical patent/WO1999056313A1/fr

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/565—Moulds
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/4985—Flexible insulating substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/50—Tape automated bonding [TAB] connectors, i.e. film carriers; Manufacturing methods related thereto
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H01L2924/143—Digital devices
    • H01L2924/1433—Application-specific integrated circuit [ASIC]

Definitions

  • the present invention relates to a semiconductor device and a method of manufacturing the same, and more particularly, to a semiconductor device of a ball grid array (BGA) type in which a package substrate on which a semiconductor chip is mounted is mounted on a printed wiring board via solder bumps. Effective technology.
  • BGA ball grid array
  • Solder bumps are mounted on one surface of a package substrate on which a semiconductor chip is mounted, and the package substrate is mounted on a printed wiring board via these solder bumps.
  • the BGA is a QFP (Quad Flat Package) in which leads are drawn out from the side of the package. It has the advantage that the number of pins can be easily increased and the mounting area can be reduced as compared with SOPs and SOPs (Sma 11 Outline Package).
  • a BGA suitable for mounting on small and lightweight electronic devices such as portable information devices, digital cameras, and notebook computers is a TCP (package substrate) made of insulating tape.
  • a BGA (Tape BGA) of the Tape Carrier Package type is known. This type of tape BGA is described in, for example, Japanese Patent Application Laid-Open Nos. Hei 7-3212-48, Hei 8-82843, Japanese Patent Laid-Open No. Hei 8-111443, etc. is there.
  • the inventor has also developed a BGA having the following structure (particularly, a fine pitch BGA in which the bump pitch is narrowed).
  • a device hole is formed in the center of a resin wiring board with a plurality of leads made of Cu (copper) foil on one side, and a semiconductor chip is placed there.
  • One end is electrically connected to the other via an Au bump electrode, and the main surface of the semiconductor chip is sealed with a potting resin.
  • the other end of the lead extends to the periphery of the wiring board to form a land portion, to which a solder bump serving as an external connection terminal of the BGA is connected.
  • a square frame-shaped metal frame is formed on the surface of the periphery of the wiring board opposite to the solder bump bonding surface. Adhesive is used, and the metal frame prevents warping around the wiring board.
  • the metal frame used in the above BGA is pressed with a thin metal plate such as Cu (copper) with a press, and adhesive is applied to one side, and a cover tape is applied to the surface to protect the adhesive.
  • a thin metal plate such as Cu (copper) with a press
  • adhesive is applied to one side
  • a cover tape is applied to the surface to protect the adhesive.
  • An object of the present invention is to provide a technique capable of reducing the manufacturing cost of BGA (tape BGA, fine pitch BGA, etc.).
  • Another object of the present invention is to provide a technique capable of improving the reliability of BGA (tape BGA, fine pitch BGA, etc.).
  • the semiconductor device of the present invention includes: a semiconductor chip; a wiring board provided so as to surround the semiconductor chip; and a plurality of leads formed on the wiring board, one end of which is electrically connected to the semiconductor chip.
  • the reinforcing frame is made of resin.
  • a semiconductor device of the present invention includes a semiconductor chip, a wiring board provided so as to surround the semiconductor chip, and a semiconductor chip formed on the wiring board, one end of which is formed by the semiconductor chip.
  • the method for manufacturing a semiconductor device according to the present invention includes the following steps.
  • a semiconductor chip is mounted on the device hole of a tape base having a plurality of leads having one end extending inside the device hole and a land portion for connecting a bump to another portion. Arranging, and electrically connecting the semiconductor chip and one end of the lead;
  • FIG. 1 and 2 are perspective views of a semiconductor device according to Embodiment 1 of the present invention.
  • FIG. 3 is a cross-sectional view of the semiconductor device according to the first embodiment of the present invention.
  • FIG. 4 is a plan view of the tape substrate, illustrating the method for manufacturing a semiconductor device according to the first embodiment of the present invention.
  • FIG. 5 is a perspective view illustrating the method for manufacturing the semiconductor device according to the first embodiment of the present invention.
  • FIG. 6 is a plan view illustrating the method for manufacturing the semiconductor device according to the first embodiment of the present invention.
  • 7 and 8 are schematic cross-sectional views illustrating a method for manufacturing a semiconductor device according to Embodiment 1 of the present invention.
  • 9 and 10 are plan views illustrating the method for manufacturing the semiconductor device according to the first embodiment of the present invention.
  • FIG. 11 is a schematic cross-sectional view illustrating the method for manufacturing the semiconductor device according to the first embodiment of the present invention.
  • FIG. 12 is a plan view of a printed wiring board on which the semiconductor device according to the first embodiment of the present invention is mounted.
  • FIG. 13 is a perspective view of a semiconductor device according to Embodiment 2 of the present invention.
  • FIGS. 14 and 15 are cross-sectional views of a semiconductor device according to Embodiment 2 of the present invention.
  • FIG. 16 is a perspective view of a semiconductor device according to Embodiment 3 of the present invention.
  • FIG. 17 is a cross-sectional view of a semiconductor device according to Embodiment 3 of the present invention.
  • FIG. 18 is a schematic cross-sectional view illustrating a method of manufacturing a semiconductor device according to Embodiment 3 of the present invention.
  • FIG. 19 is a cross-sectional view of a multi-chip module using the semiconductor device according to the third embodiment of the present invention.
  • FIG. 20 is a cross-sectional view of a semiconductor device according to Embodiment 4 of the present invention.
  • FIGS. 21 and 22 are schematic cross-sectional views illustrating a method for manufacturing a semiconductor device according to Embodiment 4 of the present invention.
  • FIG. 23 is a perspective view of a semiconductor device according to another embodiment of the present invention. BEST MODE FOR CARRYING OUT THE INVENTION
  • FIG. 1 is a perspective view showing a tape BGA (fine pitch BGA) of the present embodiment
  • FIG. 2 is a perspective view showing a mounting surface (a solder bump mounting surface) of the tape BGA
  • FIG. FIG. 1 is a perspective view showing a tape BGA (fine pitch BGA) of the present embodiment
  • FIG. 2 is a perspective view showing a mounting surface (a solder bump mounting surface) of the tape BGA
  • FIG. FIG. 1 is a perspective view showing a tape BGA (fine pitch BGA) of the present embodiment
  • FIG. 2 is a perspective view showing a mounting surface (a solder bump mounting surface) of the tape BGA
  • the tape BGA of the present embodiment includes a wiring board 2 made of polyimide resin having a plurality of leads 1 made of copper foil wiring formed on one side, and a device hole of the wiring board 2.
  • the semiconductor chip 3 on which an LSI such as a microcomputer or AS IC is formed is electrically connected to one end (inner lead 1A) of the lead 1 via an Au bump electrode 7 provided on the periphery of the main surface. Connected.
  • the other end of the lead 1 extends to the lower part of the reinforcing frame 5 provided on the periphery of the wiring board 2, and is electrically connected to the solder bump 6 in this region.
  • One surface of the wiring board 2 except for the other end (land portion 1B) of the lead 1 to which the solder bump 6 is joined is covered with a solder resist (not shown) for protecting the lead 1.
  • the reinforcing frame 5 is made of a synthetic resin formed by a transfer molding method.
  • the sealing resin 4 for protecting the semiconductor chip 3 from the external environment is made of a synthetic resin formed by the transfer molding method as in the case of the reinforcing frame 5, and covers the entire surface of the semiconductor chip 3. As shown in FIG. 1, the sealing resin 4 is connected to a reinforcing frame 5 at four corners thereof, and is formed integrally with the reinforcing frame 5.
  • the semiconductor chip 3 is made of single-crystal silicon, the dimensions are 7.6 thighs x 7.6 thighs, and the thickness is 0.4 hidden.
  • the dimensions of the wiring board 2 made of a polyimide resin are 15 thigh X I 5 mm and the thickness is 0.0705 mm.
  • the lead 1 is made of copper foil wiring formed by etching a 0.08-thick electrolytic copper foil (or a rolled copper foil) attached to one surface of the wiring board 2. The surfaces of the part 1A and the land 1B) are plated with Au / Ni.
  • the sealing resin 4 for sealing the semiconductor chip 3 and the reinforcing frame 5 formed integrally therewith are made of an epoxy resin filled with a filler such as silica.
  • the dimensions of the sealing resin 4 are 14.6 mm ⁇ 14.6 thighs and a thickness of 0.655 mm.
  • Reinforcement frame 5 is the wiring board 2 It is formed on only one side and has a thickness of 0.355 thigh.
  • the solder bump 7 bonded to the land 1B of the lead 1 is made of Sn (63%) ZPb (37%) alloy, its diameter is 0.3mm, and its pitch is 0.5mm .
  • a lead 1 made of copper foil wiring is formed on one side and a tape base material 2A having a through hole formed therein, and an element as shown in FIG.
  • a semiconductor chip 3 having Au bump electrodes 7 formed on the periphery of the formation surface is prepared.
  • the tape base material 2A is a long tape with a width of 35 s / w, one end of which is wound on a reel, but FIG. 4 shows only a BGA-area.
  • a substantially square device hole 8 in which the semiconductor chip 3 is arranged is formed at the center of the BGA-piece area of the tape base material 2 A, and one end of each of the leads 1 (the inner lead 1 A) is formed. ), Which extends inside the device hole 8.
  • a land 1B to which the solder bump 6 is connected in a later step is formed in the middle of the lead 1, a land 1B to which the solder bump 6 is connected in a later step is formed. These land portions 1 B are arranged in two rows along each side of the device hole 8.
  • a rectangular opening 9 is formed in the tape base 2A further outside the land portion 1B so as to surround the land portion 1B. These openings 9 are for facilitating the work of punching the tape base material 2A, and the tape base material 2A inside them constitutes the BGA wiring board 2.
  • the bump electrodes 7 are mounted on the semiconductor chip 3 by a ball bonding method using a wire bonding device.
  • the semiconductor chip 3 is positioned in the device hole 8 of the tape base 2A, and the bump electrode 7 and the corresponding lead 1 are electrically connected.
  • the inner lead 1A of the lead 1 is connected to the bump electrode 7 of the semiconductor chip 3 placed horizontally on the bonding stage 10.
  • the bonding tool 11 heated to about 500 ° C. from above is pressed for about 1 second, and all the bump electrodes 7 and the corresponding inner leads 1 A are simultaneously connected together.
  • the tape base material 2A is mounted on a mold as shown in FIG. 8, and a resin is injected into the cavity 12 where the semiconductor chip 3 is positioned.
  • the mold includes an upper mold 13A and a lower mold 13B.
  • a projection 14 is provided on a part of the upper mold 13 A, and the resin injected into the cavity 12 is a sealing resin for sealing the semiconductor chip 3 inside the projection 14. 4 and the outer part becomes the reinforcement frame 5.
  • the projection 14 is provided in a part of the upper mold 13A, the tape base material 2A in the area close to the semiconductor chip 3 is sandwiched between the projection 14 and the lower mold 13B. Securely fixed. This makes it difficult for the semiconductor chip 3 to oscillate when the resin is injected into the cavity 12, so that the molding defect rate due to the misalignment of the semiconductor chip 3 can be reduced.
  • a gate 15 which is a resin injection port is provided in each of the upper mold 13A and the lower mold 13B.
  • the resin flows uniformly into the main surface side and the back surface side of the semiconductor chip 3, so that the molding failure rate due to the resin inflow variation can be reduced.
  • FIG. 9 is a plan view showing a tape base material 2A (upper side) in which the resin 4 and the reinforcing frame 5 are formed by the transfer molding method using the above mold, and FIG. 10 is the same.
  • FIG. 5 is a plan view showing a tape base material 2A (mounting surface side).
  • solder bumps 6 are connected to the land portions 1B of the tape base material 2A.
  • the solder bump 6 previously formed into a ball shape is vacuum-sucked using a ball mounter 16 as shown in FIG.
  • the solder bumps 6 are temporarily attached to the corresponding land portions 1B using the adhesive force of the flux.
  • the reinforcing frame 5 is provided on the tape base material 2A in the area where the land portion 1B is formed, the tape base material 2A in this area is prevented from warping or deforming, and the flatness is reduced. improves. Therefore, even when a large number of solder bumps 6 are pressed against the corresponding land portions 1B at the same time, all the solder bumps 6 are securely brought into close contact with the land portions 1B.
  • FIG. 12 is a plan view of a printed wiring board 18 on which the above-described tape BGA and another surface-mounted package (for example, QFP) are mounted. Tape BGA and QFP are mounted simultaneously by reflowing the solder paste (or solder plating) applied to the solder bumps 6 of the tape BGA and the lead surface of the QFP in a heating furnace.
  • the encapsulating resin 4 for protecting the semiconductor chip 3 and the reinforcing frame 5 for ensuring the flatness of the peripheral portion of the wiring board 2 are simultaneously molded by the transfer molding method.
  • the manufacturing process can be reduced compared to the case where the semiconductor chip is sealed with potting resin, and the reinforcing frame is made of a mold resin that is less expensive than the metal frame. Since the material cost can be reduced by forming the tape, the tape BGA can be manufactured at low cost.
  • the reliability of the tape BGA can be improved.
  • FIG. 13 is a perspective view showing the tape BGA of the present embodiment
  • FIG. 14 is a sectional view of the tape BGA.
  • the tape BGA of the present embodiment has a structure in which the back surface of the semiconductor chip 3 is exposed from the sealing resin 4. Such a structure is particularly effective for reducing the thermal resistance of the tape BGA on which the semiconductor chip 3 consuming a large amount of power is mounted.
  • the thermal resistance of the tape BGA can be further reduced. .
  • the tape BGA In order to manufacture the tape BGA in which the back surface of the semiconductor chip 3 is exposed from the sealing resin 4, first, the tape BGA having a shallower depth than the mold shown in FIG. Prepare a mold with a cavity, and inject resin into the cavity with the tape base 2A attached so that the backside of the semiconductor chip 3 contacts the upper mold of the mold, and then seal it. What is necessary is just to shape the resin 4.
  • FIG. 16 is a perspective view showing the tape BGA of the present embodiment
  • FIG. 17 is a sectional view of the tape BGA.
  • the reinforcing frame 5 of the tape BGA and the wiring board 2 thereunder are provided with a large number of through-holes 20 penetrating through the upper and lower surfaces thereof and reaching the land portion 1B of the lead 1.
  • a conductive material 21 is embedded in the through hole 20.
  • the conductive material 21 is made of solder or conductive paste having a higher melting point than the solder bump 6 connected to the land 1B, and is formed by screen printing or a dispenser having a multipoint nozzle. Filled inside.
  • the reinforcing frame 5 is formed using a mold having a large number of pins 22 provided in a part of the upper die 13A. Molding.
  • a plurality of tape BGAs are overlapped in a direction perpendicular to the board mounting surface, and the solder bump 6 and the conductive material 21 are connected.
  • a multi-chip module in which common pins are electrically connected to each other via a pin can be easily realized.
  • a semiconductor chip 3 having a memory LSI such as DRAM is used.
  • FIG. 20 is a cross-sectional view showing the tape BGA of the present embodiment.
  • the tape BGA has a structure in which a reinforcing frame 5 is provided on the lower surface side of the wiring board 2, and solder bumps 6 are arranged inside concave grooves 23 formed in the reinforcing frame 5. .
  • the reinforcing frame 5 is formed using a mold having a large number of protrusions 24 provided in a part of the lower die 13 B. Molding.
  • the tape BGA has the above structure, as shown in FIG. 22, when the solder bumps 6 are temporarily attached to the lands 1 B using the ball mounters 16, the concave grooves 23 are formed in the solder bumps 6. Since it functions as a positioning guide, the temporary mounting of the solder bumps 6 can be performed easily and quickly. Also in this case, the reinforcing frame 5 is It functions to prevent warpage and deformation of the tape base material 2A in the region where is formed.
  • the invention made by the inventor has been specifically described based on the embodiment of the invention. However, the invention is not limited to the embodiment, and various changes can be made without departing from the gist of the invention. Needless to say, there is.
  • the sealing resin 4 and the reinforcing frame 5 may be separately molded.
  • a gate for directly supplying the resin to the cavity (1 2) of the molding die for molding the sealing resin 4 and a part of the upper die (13 A) for molding the reinforcing frame 5 is provided. It is necessary to provide a plurality of each. Industrial applicability
  • the tape BGA of the present invention in which a sealing resin for sealing a semiconductor chip and a reinforcing frame for preventing warpage and deformation of a wiring board are simultaneously resin-molded by the transfer molding method, requires a low manufacturing cost and high reliability. Therefore, it can be widely applied to mounting on small and lightweight electronic devices such as portable information devices, digital cameras, and notebook computers.

Abstract

L'invention concerne une matrice à sphères (Ball Grid Array = BGA) sur bande comprenant: une puce de semi-conducteur (3) montée sur un tableau de connexions (2) ayant plusieurs fils de connexion (1) formés sur celui-ci, et connectée électriquement à chaque extrémité des fils de connexion (1); une résine à sceller (4) destinée à recouvrir la puce de semi-conducteur (3); un cadre de renfort (5) conçu sur une partie périphérique du tableau de connexions; et plusieurs perles de soudure (6), chacun d'entre elles étant placée sur une partie périphérique du tableau de connexions et connectée électriquement à l'autre extrémité de chacun des fils de connexion (1). La résine à sceller (4) et le cadre de renfort (5) sont formés par moulage par transfert d'une résine synthétique.
PCT/JP1998/001920 1998-04-24 1998-04-24 Dispositif semi-conducteur et son procede de production WO1999056313A1 (fr)

Priority Applications (4)

Application Number Priority Date Filing Date Title
PCT/JP1998/001920 WO1999056313A1 (fr) 1998-04-24 1998-04-24 Dispositif semi-conducteur et son procede de production
JP2000546392A JP4038021B2 (ja) 1998-04-24 1998-04-24 半導体装置の製造方法
KR1020007011386A KR20010042682A (ko) 1998-04-24 1998-04-24 반도체장치 및 그 제조방법
TW088105306A TW426870B (en) 1998-04-24 1999-04-02 Semiconductor device and the manufacturing method thereof

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/JP1998/001920 WO1999056313A1 (fr) 1998-04-24 1998-04-24 Dispositif semi-conducteur et son procede de production

Related Child Applications (2)

Application Number Title Priority Date Filing Date
US09673574 A-371-Of-International 2000-10-18
US10/302,848 Division US6645794B2 (en) 2000-10-18 2002-11-25 Method of manufacturing a semiconductor device by monolithically forming a sealing resin for sealing a chip and a reinforcing frame by transfer molding

Publications (1)

Publication Number Publication Date
WO1999056313A1 true WO1999056313A1 (fr) 1999-11-04

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Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/JP1998/001920 WO1999056313A1 (fr) 1998-04-24 1998-04-24 Dispositif semi-conducteur et son procede de production

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Country Link
JP (1) JP4038021B2 (fr)
KR (1) KR20010042682A (fr)
TW (1) TW426870B (fr)
WO (1) WO1999056313A1 (fr)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2008073818A (ja) * 2006-09-22 2008-04-03 Murata Mfg Co Ltd 電子部品および複合電子部品
JP2010125829A (ja) * 2008-12-01 2010-06-10 Daiichi Seiko Kk 配線基板製造用金型およびこれを用いた配線基板の製造方法
JP2013123063A (ja) * 2013-01-17 2013-06-20 Apic Yamada Corp トランスファモールド金型およびこれを用いたトランスファモールド装置

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20010099298A (ko) * 2001-09-20 2001-11-09 신이술 반도체칩의 적층방법
JP4722690B2 (ja) * 2005-12-12 2011-07-13 富士通セミコンダクター株式会社 半導体装置およびその製造方法

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH09162233A (ja) * 1995-12-08 1997-06-20 Nec Corp 半導体装置
JPH1079401A (ja) * 1996-09-05 1998-03-24 Hitachi Ltd 半導体装置およびその製造方法
JPH1098072A (ja) * 1996-09-20 1998-04-14 Hitachi Ltd 半導体装置及びその製造方法

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH09162233A (ja) * 1995-12-08 1997-06-20 Nec Corp 半導体装置
JPH1079401A (ja) * 1996-09-05 1998-03-24 Hitachi Ltd 半導体装置およびその製造方法
JPH1098072A (ja) * 1996-09-20 1998-04-14 Hitachi Ltd 半導体装置及びその製造方法

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2008073818A (ja) * 2006-09-22 2008-04-03 Murata Mfg Co Ltd 電子部品および複合電子部品
JP2010125829A (ja) * 2008-12-01 2010-06-10 Daiichi Seiko Kk 配線基板製造用金型およびこれを用いた配線基板の製造方法
JP2013123063A (ja) * 2013-01-17 2013-06-20 Apic Yamada Corp トランスファモールド金型およびこれを用いたトランスファモールド装置

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KR20010042682A (ko) 2001-05-25
JP4038021B2 (ja) 2008-01-23
TW426870B (en) 2001-03-21

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