WO1999031803A1 - Synchronisation dans les circuits electroniques - Google Patents

Synchronisation dans les circuits electroniques Download PDF

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Publication number
WO1999031803A1
WO1999031803A1 PCT/IE1998/000105 IE9800105W WO9931803A1 WO 1999031803 A1 WO1999031803 A1 WO 1999031803A1 IE 9800105 W IE9800105 W IE 9800105W WO 9931803 A1 WO9931803 A1 WO 9931803A1
Authority
WO
WIPO (PCT)
Prior art keywords
circuit device
clock
pad
internal
clock signal
Prior art date
Application number
PCT/IE1998/000105
Other languages
English (en)
Inventor
Kevin Dewar
Original Assignee
Tellabs Research Limited
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Tellabs Research Limited filed Critical Tellabs Research Limited
Priority to AU16803/99A priority Critical patent/AU1680399A/en
Publication of WO1999031803A1 publication Critical patent/WO1999031803A1/fr

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/0175—Coupling arrangements; Interface arrangements
    • H03K19/01759—Coupling arrangements; Interface arrangements with a bidirectional operation

Definitions

  • the invention relates to provision of a clock signal for transfer of data between electronic circuits such as ASICs.
  • the clock source may be on one or other of the two interfacing devices, or it may be external to them.
  • Another problem is synchronising clock signals between devices if frequency is changed.
  • the invention is directed towards providing a clock circuit to provide additional flexibility in provision of clock signals for interfacing of devices such as ASICs.
  • Another object is to improve synchronisation of data between interfacing devices.
  • a circuit device comprising an interface comprising a terminal connected to a port for conducting an external clock signal, a terminal for conducting an internal clock signal, and a terminal connected to provide a clock signal to internal blocks of the circuit device, the terminals being interconnected to form a star pad.
  • the terminals are interconnected there is always synchronisation of internal and external clocking. For example, if the external clock signal is skewed due to high capacitive loading externally of the chip there will be the same effect both internally and externally.
  • the star pad is connected to an internal clock source. This allows the star pad to act as a clock output with excellent internal/external synchronisation.
  • the star pad is bi-directional and further comprises means for switching between the internal clock source and an external clock source to provide a clock from a selected source. This allows excellent flexibility as the circuit interface may be easily configured to act as either a clock input or output.
  • the star pad comprises means for driving a clock signal from the internal clock source to the external clock signal port. This allows the circuit device to drive internally generated clock signals to external circuits.
  • the switching means may comprise a tri-state buffer and means for delivering configuration control signals.
  • the configuration control means may comprise a circuit device register. As little as one bit may be used for configuration control of a tri-state buffer. This allows control to be achieved in a very simple manner with little circuit overhead.
  • the circuit device is an application specific integrated circuit.
  • Fig. 1 is a schematic representation of part of a circuit interface of the invention.
  • Fig. 2 is a diagram showing a star pad of the interface in more detail.
  • UTOPIA interface for .an ATM cell processing ASIC device.
  • the interface is indicated by the numeral 1 and the chip boundary by the numeral 2.
  • An external clock signal line 3, an output data bus 4, and an input data bus 5 cross the chip boundary 2.
  • the interface 1 comprises an on-chip internal clock 10.
  • the internal clock 10 is connected to a pad 11, which is also connected to the external clock line 3, to a UTOPIA logic block 12, and to a configuration control circuit 13.
  • the configuration control circuit 13 is an ASIC register having a single bit dedicated to provide a configuration control signal to the star pad circuit 11.
  • the pad 11 itself is shown more clearly in Fig. 2. It has a terminal 14 for connection to the external clock line 3, and is connected internally by lines 15 and 16 to the internal clock source 10 and to the UTOPIA logic block 12 respectively. Switching is performed by a tri-state buffer 17, which is connected to the configuration control circuit 13. Because of the star interconnection arrangement, the pad 11 is hereinafter referred to as a "star pad".
  • a bit 1 enable signal ('"en) causes configuration as an output.
  • an internal clock signal “a” drives onto the external clock line 3 via the tri- state buffer 17.
  • the signal “q " on the line 16 is logically equal to "a”, and so the UTOPIA logic block takes its clock signal from the internal source 10.
  • a bit 0 disables the tri-state buffer 17 so that "q" is logically equal to the external clock signal.
  • Such a signal may, for example, be provided by a communicating device.
  • star pad 11 allows:-
  • the star pad 11 ensures that there is a proper timing relationship between the external clock and output data signals i.e. there is always some positive hold-time on the data. This is because the star pad 11 is used as a star-point before the timing.
  • the star pad also allows self-compensation for the actual loading on the clock and data pads. For example, clock skewing due to high capacative loading externally of the chip has the same effect both internally and externally.
  • the logic block 12 performs the interfacing operation in conjunction with the relevant clock signals.
  • the invention provides excellent flexibility in a circuit device.
  • the internal clock signals may be selected either from an internal clock or from an external clock.
  • flexibility is enhanced by virtue of the fact that the internal clock may drive a clock signal for an external processor.
  • These features are very important in system design because of the flexibility which is provided. Also, these features have been achieved in a very simple manner with very little overhead on the circuit device. Indeed, only single bits are required for configuration control.
  • the star pad need not include a switching means, in which case the advantage of excellent synchronisation is still achieved.
  • the clock source may be set permanently as either the internal clock 10 or an external clock. Where a switching means is included, it need not necessarily be a tri-state buffer.

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Data Exchanges In Wide-Area Networks (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)

Abstract

L'invention concerne une interface Utopia (1) destinée à un processeur ASIC de cellules ATM, qui comporte une horloge (10) interne sur la puce. L'horloge (10) est connectée à un plot (11) qui est également connecté à une ligne (3) d'horloge externe, à un bloc de logique Utopia (12) et à un circuit de commande de la configuration (13). Le plot (11) peut être configuré comme une sortie, de façon que la source de synchronisation soit interne, ou comme une entrée, de façon que la source de synchronisation soit externe.
PCT/IE1998/000105 1997-12-15 1998-12-15 Synchronisation dans les circuits electroniques WO1999031803A1 (fr)

Priority Applications (1)

Application Number Priority Date Filing Date Title
AU16803/99A AU1680399A (en) 1997-12-15 1998-12-15 Clocking in electronic circuits

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
IE970887 1997-12-15
IE970887 1997-12-15
IES980711 1998-08-31
IE980711A IES980711A2 (en) 1997-12-15 1998-08-31 Clocking in electronic circuits

Publications (1)

Publication Number Publication Date
WO1999031803A1 true WO1999031803A1 (fr) 1999-06-24

Family

ID=26320136

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/IE1998/000105 WO1999031803A1 (fr) 1997-12-15 1998-12-15 Synchronisation dans les circuits electroniques

Country Status (3)

Country Link
AU (1) AU1680399A (fr)
IE (2) IES980711A2 (fr)
WO (1) WO1999031803A1 (fr)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2001020784A1 (fr) * 1999-09-15 2001-03-22 Thomson Licensing S.A. Circuit integre multi-horloge avec generateur d'horloge et disposition bidirectionnelle de broches d'horloge
WO2007050882A2 (fr) * 2005-10-26 2007-05-03 Intel Corporation Architecture d'horloge utilisant une horloge de reference bidirectionnelle

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0358501A2 (fr) * 1988-09-08 1990-03-14 Kawasaki Steel Corporation Circuit d'entrée/sortie programmable
US4940909A (en) * 1989-05-12 1990-07-10 Plus Logic, Inc. Configuration control circuit for programmable logic devices
EP0456400A2 (fr) * 1990-05-11 1991-11-13 Actel Corporation Module d'entrée et de sortie avec circuits de verrouillage
WO1997003444A1 (fr) * 1995-07-10 1997-01-30 Xilinx, Inc. Systeme comprenant un reseau de portes programmable par l'utilisateur et une memoire intelligente
US5686844A (en) * 1996-05-24 1997-11-11 Microchip Technology Incorporated Integrated circuit pins configurable as a clock input pin and as a digital I/O pin or as a device reset pin and as a digital I/O pin and method therefor

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0358501A2 (fr) * 1988-09-08 1990-03-14 Kawasaki Steel Corporation Circuit d'entrée/sortie programmable
US4940909A (en) * 1989-05-12 1990-07-10 Plus Logic, Inc. Configuration control circuit for programmable logic devices
EP0456400A2 (fr) * 1990-05-11 1991-11-13 Actel Corporation Module d'entrée et de sortie avec circuits de verrouillage
WO1997003444A1 (fr) * 1995-07-10 1997-01-30 Xilinx, Inc. Systeme comprenant un reseau de portes programmable par l'utilisateur et une memoire intelligente
US5686844A (en) * 1996-05-24 1997-11-11 Microchip Technology Incorporated Integrated circuit pins configurable as a clock input pin and as a digital I/O pin or as a device reset pin and as a digital I/O pin and method therefor

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
ANONYMOUS: "Test Optimization Via Second Level Metalization. May 1979.", IBM TECHNICAL DISCLOSURE BULLETIN, vol. 21, no. 12, May 1979 (1979-05-01), New York, US, pages 4891, XP002095888 *

Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2001020784A1 (fr) * 1999-09-15 2001-03-22 Thomson Licensing S.A. Circuit integre multi-horloge avec generateur d'horloge et disposition bidirectionnelle de broches d'horloge
US6639422B1 (en) 1999-09-15 2003-10-28 Thomson Licensing S.A. Multi-clock integrated circuit with clock generator and bi-directional clock pin arrangement
WO2007050882A2 (fr) * 2005-10-26 2007-05-03 Intel Corporation Architecture d'horloge utilisant une horloge de reference bidirectionnelle
WO2007050882A3 (fr) * 2005-10-26 2007-10-04 Intel Corp Architecture d'horloge utilisant une horloge de reference bidirectionnelle
GB2445698A (en) * 2005-10-26 2008-07-16 Intel Corp A clocking architecture using a bi-directional reference clock
US7555670B2 (en) 2005-10-26 2009-06-30 Intel Corporation Clocking architecture using a bidirectional clock port
DE112006002559B4 (de) * 2005-10-26 2010-04-29 Intel Corporation, Santa Clara Eine Taktgeberarchitektur unter Verwendung eines bi-direktionalen Taktanschlusses
GB2445698B (en) * 2005-10-26 2010-11-03 Intel Corp A clocking architecture using a bi-directional reference clock

Also Published As

Publication number Publication date
IES80917B2 (en) 1999-06-30
AU1680399A (en) 1999-07-05
IES980711A2 (en) 1999-06-30
IE981055A1 (en) 1999-06-16

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