WO1999018608A1 - VERFAHREN ZUR HERSTELLUNG EINER MATRIX AUS DÜNNSCHICHTTRANSISTOREN, INSBESONDERE MIT a:Si-H ALS HALBLEITER, FÜR FLÜSSIGKRISTALLBILDSCHIRME - Google Patents
VERFAHREN ZUR HERSTELLUNG EINER MATRIX AUS DÜNNSCHICHTTRANSISTOREN, INSBESONDERE MIT a:Si-H ALS HALBLEITER, FÜR FLÜSSIGKRISTALLBILDSCHIRME Download PDFInfo
- Publication number
- WO1999018608A1 WO1999018608A1 PCT/DE1998/002463 DE9802463W WO9918608A1 WO 1999018608 A1 WO1999018608 A1 WO 1999018608A1 DE 9802463 W DE9802463 W DE 9802463W WO 9918608 A1 WO9918608 A1 WO 9918608A1
- Authority
- WO
- WIPO (PCT)
- Prior art keywords
- thin
- semiconductor
- film transistors
- photoresist
- contacts
- Prior art date
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 23
- 239000010409 thin film Substances 0.000 title claims abstract description 18
- 239000004973 liquid crystal related substance Substances 0.000 title claims abstract description 10
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 10
- 239000011159 matrix material Substances 0.000 title claims abstract description 8
- 238000000034 method Methods 0.000 claims abstract description 30
- 229920002120 photoresistant polymer Polymers 0.000 claims abstract description 22
- 238000001465 metallisation Methods 0.000 claims description 11
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 claims description 10
- 239000011248 coating agent Substances 0.000 claims description 9
- 238000000576 coating method Methods 0.000 claims description 9
- 239000010936 titanium Substances 0.000 claims description 9
- 229910052719 titanium Inorganic materials 0.000 claims description 9
- ZOKXTWBITQBERF-UHFFFAOYSA-N Molybdenum Chemical compound [Mo] ZOKXTWBITQBERF-UHFFFAOYSA-N 0.000 claims description 6
- 229910021417 amorphous silicon Inorganic materials 0.000 claims description 6
- 229910052750 molybdenum Inorganic materials 0.000 claims description 6
- 239000011733 molybdenum Substances 0.000 claims description 6
- 238000002161 passivation Methods 0.000 claims description 6
- 239000000758 substrate Substances 0.000 claims description 6
- 238000003631 wet chemical etching Methods 0.000 claims description 6
- 229910052782 aluminium Inorganic materials 0.000 claims description 5
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims description 5
- 229910004205 SiNX Inorganic materials 0.000 claims description 4
- 238000001020 plasma etching Methods 0.000 claims description 4
- 239000011521 glass Substances 0.000 claims description 3
- AMGQUBHHOARCQH-UHFFFAOYSA-N indium;oxotin Chemical compound [In].[Sn]=O AMGQUBHHOARCQH-UHFFFAOYSA-N 0.000 claims description 3
- 239000012212 insulator Substances 0.000 claims description 3
- 229910052751 metal Inorganic materials 0.000 claims description 3
- 239000002184 metal Substances 0.000 claims description 3
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 claims description 3
- 101000652359 Homo sapiens Spermatogenesis-associated protein 2 Proteins 0.000 claims 1
- 101000642464 Homo sapiens Spermatogenesis-associated protein 2-like protein Proteins 0.000 claims 1
- 102100030254 Spermatogenesis-associated protein 2 Human genes 0.000 claims 1
- 229910004164 TaMo Inorganic materials 0.000 claims 1
- 239000000956 alloy Substances 0.000 claims 1
- 229910045601 alloy Inorganic materials 0.000 claims 1
- 230000007547 defect Effects 0.000 abstract description 3
- 238000011161 development Methods 0.000 description 4
- 230000018109 developmental process Effects 0.000 description 4
- 238000005530 etching Methods 0.000 description 2
- 238000007704 wet chemistry method Methods 0.000 description 2
- 229910001182 Mo alloy Inorganic materials 0.000 description 1
- 239000002800 charge carrier Substances 0.000 description 1
- 230000001419 dependent effect Effects 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 230000007613 environmental effect Effects 0.000 description 1
- 230000004927 fusion Effects 0.000 description 1
- 230000000873 masking effect Effects 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- JZLMRQMUNCKZTP-UHFFFAOYSA-N molybdenum tantalum Chemical compound [Mo].[Ta] JZLMRQMUNCKZTP-UHFFFAOYSA-N 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/84—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being other than a semiconductor body, e.g. being an insulating body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1259—Multistep manufacturing methods
- H01L27/1288—Multistep manufacturing methods employing particular masking sequences or specially adapted masks, e.g. half-tone mask
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
Definitions
- the invention is based on a method for producing a matrix of thin-film transistors, in particular with a: Si-H as a semiconductor, for liquid crystal screens.
- the method according to the invention with the characterizing features of claim 1 enables the production of a thin-film transistor matrix for liquid crystal screens with only three coating steps, screens with only a few pixel defects and thin-film transistors with high mobility of the charge carriers being achievable.
- the method also allows a high yield to be achieved.
- the invention is essentially based on the fusion of some process steps by double exposure of photoresist layers and a lift-off step in which the photoresist and the passivation in the area of the contacts are removed together. Due to the small number of process steps of the method according to the invention, the yield in the production of liquid crystal screens is very high. The shorter production times and the saving of machines and consumables enable cost-effective production, which can also be reflected in the product price. In addition, the lower number of process steps also results in a lower environmental impact than with conventional processes.
- the pixel electrodes are arranged directly on the substrate and can therefore be structured particularly easily.
- ITO indium tin oxide
- titanium or a tantalum-molybdenum alloy can preferably be sputtered on as row and gate contacts.
- the structuring of the ITO and titanium layers can preferably be carried out by wet chemistry.
- SiNx as gate insulator a-Si: H as semiconductor, n + " a-Si: H as drain and source contacts are deposited in a vacuum in a PECVD system and structured by plasma etching
- a-Si: H as drain and source contacts are deposited in a vacuum in a PECVD system and structured by plasma etching
- a molybdenum or titanium layer can be sputtered on and structured by wet chemical etching.
- aluminum can preferably be sputtered on and also etched using wet chemistry.
- other metals can also be used for the metallizations.
- Liquid crystal display in several process steps for structuring the gate oxide and the pixel electrode
- an indium tin oxide layer (ITO) 11 and a titanium layer 12 are applied to a glass substrate 10, preferably in a coating system with successive targets and then coated with a photoresist layer 13.
- the mask for structuring the gate oxide of the later thin-film transistor TFT and the pixel electrode of a pixel BP is then exposed and developed.
- the titanium layer 12 and then the ITO layer 11 are then wet-chemically etched in a system by switching over the etching media, so that the structure shown in FIG. 1 b) results.
- FIG. 1 c) the structure is in the region after the exposure and development of an ITO mask and the wet chemical etching of the titanium layer 12 of the pixel BP and shown after removal of the photoresist. This completes the first coating step.
- the second coating step is explained in FIG. 2.
- a layer sequence of SiNx, a-Si: H and n + -a-Si: H is deposited in a vacuum in a PECVD process, and then molybdenum as metallization of the gaps on this layer sequence and sputtered drain and source contacts.
- the entire substrate is then again provided with a photoresist layer 13.
- 2 b) shows the structure after exposure and development of a gate oxide mask and a semiconductor mask and the wet chemical etching of the molybdenum layer 17.
- 2 c) shows the structure after the plasma etching of the n-doped semiconductor 16, the intrinsic semiconductor 15 and the gate oxide 14.
- the semiconductor channel of the thin-film transistor TFT remains covered by the molybdenum layer 17.
- the molybdenum layer 17 in the region of the semiconductor channel was wet-chemically etched away and then the intrinsic semiconductor layer 16 and partly the undoped semiconductor layer 15 in a plasma etching step.
- the photoresist 13 is then removed, so that the structure shown in FIG. 2 f) results.
- FIG. 3 shows the third coating step.
- an aluminum layer 18 is sputtered over the entire surface and then a photoresist layer 13 was applied.
- the aluminum layer 18 and the photoresist layer 13 also extend over contacts which have been omitted in FIGS. 1 and 2 for reasons of clarity.
- 3 b) shows the structure after the exposure and development of a mask for the contacts and contact fingers KF in the area of the image point BP and the wet chemical etching of the aluminum layer 18.
- a transparent passivation is tion, preferably SiNx 19, applied.
- the photoresist 13 in the area of the contact fingers KF and the contacts together with the passivation 19 located above them is removed, resulting in the finished structure shown in FIG. 3 d).
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Manufacturing & Machinery (AREA)
- Thin Film Transistor (AREA)
- Liquid Crystal (AREA)
Abstract
Description
Claims
Priority Applications (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
EP98951194A EP0943156A1 (de) | 1997-10-06 | 1998-08-24 | VERFAHREN ZUR HERSTELLUNG EINER MATRIX AUS DÜNNSCHICHTTRANSISTOREN, INSBESONDERE MIT a:Si-H ALS HALBLEITER, FÜR FLÜSSIGKRISTALLBILDSCHIRME |
JP52074299A JP2001507481A (ja) | 1997-10-06 | 1998-08-24 | 液晶ディスプレイのためのとりわけ半導体としてa:Si−Hを有する薄膜トランジスタから成るマトリクスの製造方法 |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
DE19744098A DE19744098B4 (de) | 1997-10-06 | 1997-10-06 | Verfahren zur Herstellung einer Matrix aus Dünnschichttransistoren für Flüssigkristallbildschirme |
DE19744098.3 | 1997-10-06 |
Publications (1)
Publication Number | Publication Date |
---|---|
WO1999018608A1 true WO1999018608A1 (de) | 1999-04-15 |
Family
ID=7844733
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
PCT/DE1998/002463 WO1999018608A1 (de) | 1997-10-06 | 1998-08-24 | VERFAHREN ZUR HERSTELLUNG EINER MATRIX AUS DÜNNSCHICHTTRANSISTOREN, INSBESONDERE MIT a:Si-H ALS HALBLEITER, FÜR FLÜSSIGKRISTALLBILDSCHIRME |
Country Status (6)
Country | Link |
---|---|
EP (1) | EP0943156A1 (de) |
JP (1) | JP2001507481A (de) |
KR (1) | KR20000069207A (de) |
DE (1) | DE19744098B4 (de) |
TW (1) | TW437098B (de) |
WO (1) | WO1999018608A1 (de) |
Families Citing this family (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR100904270B1 (ko) | 2002-12-31 | 2009-06-25 | 엘지디스플레이 주식회사 | 박막 트랜지스터 어레이 기판 및 그 제조 방법 |
KR100561646B1 (ko) * | 2003-10-23 | 2006-03-20 | 엘지.필립스 엘시디 주식회사 | 표시 소자용 박막 트랜지스터 기판 및 그 제조 방법 |
Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS60234369A (ja) * | 1984-05-07 | 1985-11-21 | Nec Corp | 2重ゲ−ト型薄膜トランジスタ |
US4767723A (en) * | 1987-10-30 | 1988-08-30 | International Business Machines Corporation | Process for making self-aligning thin film transistors |
-
1997
- 1997-10-06 DE DE19744098A patent/DE19744098B4/de not_active Expired - Fee Related
-
1998
- 1998-08-24 KR KR1019997004784A patent/KR20000069207A/ko not_active Application Discontinuation
- 1998-08-24 EP EP98951194A patent/EP0943156A1/de not_active Withdrawn
- 1998-08-24 WO PCT/DE1998/002463 patent/WO1999018608A1/de not_active Application Discontinuation
- 1998-08-24 JP JP52074299A patent/JP2001507481A/ja active Pending
- 1998-08-29 TW TW087114349A patent/TW437098B/zh not_active IP Right Cessation
Patent Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS60234369A (ja) * | 1984-05-07 | 1985-11-21 | Nec Corp | 2重ゲ−ト型薄膜トランジスタ |
US4767723A (en) * | 1987-10-30 | 1988-08-30 | International Business Machines Corporation | Process for making self-aligning thin film transistors |
Non-Patent Citations (2)
Title |
---|
"PROCESSES FOR MAKING COMPLETE TWO MASK THIN FILM TRANSISTORS WITH THE DUAL-TONE PHOTORESIST PROCESSING METHOD", IBM TECHNICAL DISCLOSURE BULLETIN, vol. 36, no. 4, 1 April 1993 (1993-04-01), pages 477 - 478, XP000364586 * |
PATENT ABSTRACTS OF JAPAN vol. 010, no. 091 (E - 394) 9 April 1986 (1986-04-09) * |
Also Published As
Publication number | Publication date |
---|---|
DE19744098A1 (de) | 1999-04-15 |
DE19744098B4 (de) | 2004-12-09 |
JP2001507481A (ja) | 2001-06-05 |
TW437098B (en) | 2001-05-28 |
KR20000069207A (ko) | 2000-11-25 |
EP0943156A1 (de) | 1999-09-22 |
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