WO1998043412A1 - Circuit d'accentuation de contours - Google Patents
Circuit d'accentuation de contours Download PDFInfo
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- WO1998043412A1 WO1998043412A1 PCT/JP1997/000997 JP9700997W WO9843412A1 WO 1998043412 A1 WO1998043412 A1 WO 1998043412A1 JP 9700997 W JP9700997 W JP 9700997W WO 9843412 A1 WO9843412 A1 WO 9843412A1
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N5/00—Details of television systems
- H04N5/14—Picture signal circuitry for video frequency region
- H04N5/20—Circuitry for controlling amplitude response
- H04N5/205—Circuitry for controlling amplitude response for correcting amplitude versus frequency characteristic
- H04N5/208—Circuitry for controlling amplitude response for correcting amplitude versus frequency characteristic for compensating for attenuation of high frequency components, e.g. crispening, aperture distortion correction
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N9/00—Details of colour television systems
- H04N9/64—Circuits for processing colour signals
- H04N9/646—Circuits for processing colour signals for image enhancement, e.g. vertical detail restoration, cross-colour elimination, contour correction, chrominance trapping filters
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N5/00—Details of television systems
- H04N5/14—Picture signal circuitry for video frequency region
- H04N5/142—Edging; Contouring
Definitions
- the present invention relates to an outline emphasis circuit that outputs a digital color image signal whose outline is emphasized based on the input of an analog color image signal, such as a plasma display (hereinafter simply referred to as a PDP) and a liquid crystal display. It is used to display an outline-enhanced color image on a digitally driven display device (for example, a matrix type display device) such as a display (hereinafter simply referred to as LCD).
- a digitally driven display device for example, a matrix type display device
- LCD display
- the contour emphasis circuit that performs this contour emphasis processing includes a YZC separation circuit 10, a color demodulation circuit 12, a contour extraction circuit 14, a phase adjustment circuit 16, 18, 20, and an addition circuit. 22 and a matrix circuit 24.
- the Y / C separation circuit 10 separates a Y (luminance) signal and a C (color) signal from a composite video signal (for example, a composite color television signal) CV input to the input terminal 26, and a color demodulation circuit 12 Demodulates the Y, RY (color difference) and BY (color difference) signals based on the Y and C signals.
- the contour extraction circuit 14 extracts a contour component Ye, which is a high-frequency component of the video signal, based on the Y signal.
- the adding circuit 22 adds the contour component Ye to the Y signal.
- the matrix circuit 24 is composed of the (Y + Ye) signal added by the adding circuit 22, the (R ⁇ Y) signal whose phase has been adjusted by the phase adjusting circuits 18 and 20, and (B ⁇ Y) Based on the signals, a signal is created by adding the contour component Ye to each of the R (red), G (green), and B (blue) signals. That is, the matrix circuit 24 has the following equations (1), (2), R + Ye, G + Ye, and B + Ye are created based on the calculation of (3). By outputting these R + Ye, G + Ye, and B + Ye to the CRT display device via the output terminals 28r, 28g, and 28b, the image whose outline is emphasized by the CRT display device can be obtained. Is displayed.
- the present applicant has simultaneously proposed, as a separate application, a contour emphasis circuit for solving the above-described problems. That is, the analog color video signal is converted into a digital signal by the A / D conversion circuit, and then the Y signal is generated. The contour component extracted from the Y signal is added to the digital color video signal output from the A / D conversion circuit.
- the configuration is such that a digital video signal with contour enhancement is obtained, so that the contour enhancement component does not exceed the dynamic range of the AD conversion circuit unlike the conventional example.
- the circuit shown in FIG. 3 is a first phase adjustment circuit 31 composed of an AZD conversion circuit 30 r, 30 g, 30 b and a line memory 31 r, 31 g, 31 b, and a second phase adjustment circuit 3. 3, contour addition circuit 34 r, 34 g, 34 b, signal processing circuit 35, Y signal generation circuit 36, contour extraction circuit 38, contour component gain controller 40, and coefficient multiplication circuit 42 .
- the analog R, G, and B signals input to the input terminals 44 r, 44 g, and 44 b are converted to digital signals by the AZD conversion circuits 30 r, 30 g, and 30 b, and the first and second phases are converted to digital signals.
- the phase is adjusted by the adjustment circuits 31 and 33 and input to the contour addition circuits 34 r, 34 g, and 34 b.
- the Y signal generation circuit 36 generates a Y signal from the digital R, G and B signals
- the contour extraction circuit 38 extracts a contour component from the ⁇ signal
- the extracted contour component is used as a gain controller 40 and a coefficient multiplication circuit 4 Contour addition circuit via 2 34 Input to r, 34 g, 34 b and added to the original digital R, G, B signal.
- the digital R, G, and B signals edge-enhanced by the edge addition circuits 34r, 34g, and 34b are subjected to signal processing such as pixel number conversion and gamma correction by the signal processing circuit 35, and output.
- the image is supplied to the display device via the terminals 86r, 86g, and 86b, and a contour-enhanced image is displayed.
- the contour addition circuits 34 r, 34 g, and 34 b are added to the input signals R, G, and B output from the second phase adjustment circuit 33 as shown in FIG. 42 Adds the contour components as shown in Fig. (B) output from multipliers 84r, 84g, and 84g, and outputs R, G, and B signals with contour enhancement as shown in Fig. (C).
- the contour enhancement effect is halved by the signal processing circuit 35 at the subsequent stage.
- FIG. 5 the action of halving the above-described contour enhancement effect will be described with reference to FIGS. 5 and 6.
- FIG. 5 shows a case where the number of pixels is converted to match the number of sampling pixels to the number of display pixels of the display device.
- the original signal shown in FIG. When the rate conversion is performed with the number of sampling pixels being 1/2, the signals output from the output terminals 86 r, 86 g, and 86 b are as shown in FIG.
- this output signal has a step and the linearity is deviated, and the lance force s original signal of the undershoot and the overshoot, and the original signal Since the signals are different, when the image is supplied to the display device to display the image, the outline is emphasized, but the image is unnatural and the effect of the outline enhancement is reduced by half.
- S1 to S4 represent sampling points
- U1 represents the magnitude of undershoot
- O1 represents the magnitude of overshoot.
- Fig. 6 shows the case where gamma correction was performed to correct the display characteristics of the display device, and the input / output conversion characteristics shown in Fig. 6 (b) were used for the original signal shown in Fig. 6 (a).
- the signals output from output terminals 86 r, 86 g and 86 b are (c).
- this output signal has an undershoot and an overshoot that are far from the proper values shown in Fig. 6 (a).
- U2 represents the magnitude of undershoot
- O2 represents the magnitude of overshoot.
- the present invention has been made in view of the above-described problems.
- a display device driven by a digital video signal can display an edge-enhanced image without whiteout or blackout, and an edge enhancement circuit that can prevent the edge enhancement effect from being reduced to half by the added signal processing circuit. It is intended to be realized. Disclosure of the invention
- the edge enhancement circuit includes an AZD conversion circuit that converts an analog color video signal (for example, R, G, B signals) into a digital color video signal and outputs the digital color video signal, and an output signal of the A / D conversion circuit.
- a signal processing circuit that performs signal processing such as pixel number conversion and gamma correction and outputs the signal, a Y signal generation circuit that generates a Y signal from the output signal of the signal processing circuit, and a contour that extracts a contour component from the generated Y signal It is characterized by comprising an extraction circuit, and a contour addition circuit for adding the extracted contour component to an output signal of the signal processing circuit to output a contour-enhanced signal.
- the analog color video signal is converted to a digital signal by the AZ D conversion circuit, and then a Y signal is generated.
- the contour component extracted from the Y signal is added to the digital color video signal output from the signal processing circuit and output.
- the edge enhancement component does not exceed the dynamic range of the AZD conversion circuit. For this reason, even when the analog color video signal input to the contour emphasizing circuit of the present invention is a large amplitude signal or when the amount of contour emphasizing is increased, the signal is output from the contour emphasizing circuit of the present invention.
- a signal is output to a display device driven by a digital video signal to display a contour-enhanced image, no blackout or blackout occurs.
- the contour addition circuit is placed after the signal processing circuit, and the contour component is added to the digital video signal after signal processing such as pixel number conversion and gamma correction. This eliminates the effect on the contour components due to signal processing such as gamma correction, and prevents the contour enhancement effect from halving.
- the Y signal generation circuit is not limited to the one that generates the Y signal from the output signal of the signal processing circuit, and may be the one that generates the Y signal from the output signal of the A / D conversion circuit.
- the signal processing circuit may be composed of two signal processing circuits of a pixel number conversion circuit for performing pixel number conversion and a gamma correction circuit for performing gamma correction. It may be constituted by one signal processing circuit.
- a contour extracting circuit is provided for the first and second lines. It consists of a memory, a vertical contour extraction circuit, a contour emphasis frequency setting circuit, a horizontal contour extraction circuit, and a contour synthesis circuit.
- the contour emphasis frequency setting circuit is composed of four 1-dot delay elements connected in series, and a second 1-dot delay element is provided. Output a 2-dot delayed Y signal from the output side, and output a 4-dot delayed Y signal from the output side of the fourth 1-dot delay element.
- a coring circuit for suppressing a contour component below a certain level is provided in the contour extraction circuit.
- a gain controller that adjusts and outputs the size of the contour component extracted by the contour extraction circuit so that the contour enhancement amount can be increased, and a coefficient Kr, Kg, K and a coefficient multiplication circuit for multiplying by b and outputting the result to the contour addition circuit.
- FIG. 1 is a block diagram showing a conventional edge enhancement circuit.
- FIG. 2 shows the problem when the signal obtained by the circuit in Fig. 1 is A / D converted and output to the display device.
- FIG. 7B is a diagram showing that blackouts have occurred
- FIG. 8B is a diagram showing that whiteouts and blackouts have occurred when the edge enhancement amount is increased.
- FIG. 3 is a block diagram showing a case in which a signal processing circuit is added to the final stage of the contour emphasis circuit proposed as a separate application by the present applicant, and the contour emphasis effect is reduced by half.
- FIG. 4 is a waveform diagram of signals input to and output from the contour addition circuits 34 r 34 g and 34 b in FIG. 3, (a) is a waveform diagram of a signal input from the second phase adjustment circuit 33, (b) is a waveform diagram of the contour component input from the coefficient multiplying circuit 42, and (c) is a waveform diagram of the output signal with the contour emphasized.
- FIG. 5 is a signal waveform diagram for explaining the pixel number conversion by the signal processing circuit 35 of FIG. 3, (a) is a waveform diagram of an input signal, and (b) is a case where the number of sampling pixels is one to two. And (c) is a waveform diagram of an output signal.
- FIG. 6 is a signal waveform diagram illustrating gamma correction by the signal processing circuit 35 of FIG. 3, (a) is a waveform diagram of an input signal, (b) is an input / output characteristic diagram for gamma correction, c) is a waveform diagram of the output signal.
- FIG. 7 is a block diagram showing an embodiment of the contour emphasizing circuit according to the present invention.
- FIG. 8 is a block diagram showing an example of the Y signal generation circuit in FIG.
- FIG. 9 is a block diagram showing an example of the contour extraction circuit in FIG.
- FIG. 10 is a characteristic diagram of the coring circuit in FIG.
- FIG. 11A and 11B show signal waveforms related to horizontal edge enhancement.
- FIG. 11A is a waveform diagram of signal 1 in FIG. 9
- FIG. 11B is a waveform diagram of signal 2 in FIG. ) Is the waveform diagram of signal 3 in Fig. 9,
- (d) is the waveform diagram of signal ⁇ in Fig. 9, and
- (e) is the horizontal component of the signal output to output terminal 86r in Fig. 7.
- FIG. 11A is a waveform diagram of signal 1 in FIG. 9
- FIG. 11B is a waveform diagram of signal 2 in FIG. ) Is the waveform diagram of signal 3 in Fig. 9
- (d) is the waveform diagram of signal ⁇ in Fig. 9
- (e) is the horizontal component of the signal output to output terminal 86r in Fig. 7.
- FIGS. 12 and 13 show signal waveforms related to vertical edge enhancement
- FIG. 9, (b) is a waveform diagram of the signal ⁇ in FIG. 9
- (c) is a waveform diagram of the signal ⁇ in FIG. 9
- (d) is a waveform diagram of the signal ⁇ in FIG. 7
- (e) is a waveform diagram of a vertical component of a signal output to the output terminal 86r in FIG. BEST MODE FOR CARRYING OUT THE INVENTION
- FIG. 7 shows an embodiment of the present invention, and the same parts as those in FIG.
- reference numerals 30 r, 30 g, and 30 13 denote a 0 conversion circuit
- 37 denotes a pixel number conversion circuit as an example of a signal processing circuit
- 31 denotes a line memory 31 r and 31 g. , 31b
- 39 is a gamma correction circuit as another example of a signal processing circuit
- 33 is a second phase adjustment circuit
- 34r, 34g, and 34b are contour additions.
- Circuit, 36 is a Y signal generation circuit
- 38 is a contour extraction circuit
- 40 is a contour component gain controller
- 42 is a coefficient multiplication circuit.
- the AZD conversion circuits 30r, 30g, and 30b respectively convert the analog R, G, and B signals input to the input terminals 44r, 44g, and 44b into digital signals with a resolution of 8 bits. It is configured to convert to R, G, B signals and output.
- the pixel number conversion circuit 37 is configured to output a signal obtained by performing a pixel number conversion on the output signals of the A / D conversion circuits 30r, 30g, and 30B. This pixel number conversion is performed by sampling the digital R, G, and B signals output from the A / D converter circuits 30r, 30g, and 30b in order to match the number of sampling pixels to the number of display pixels of the display device. Represents signal processing for performing rate conversion of numbers.
- the line memories 31 r, 31 g, and 31 b of the first phase adjustment circuit 31 output signals obtained by delaying the output signal of the pixel number conversion circuit 37 by one line, respectively. Is configured.
- the gamma correction circuit 39 is configured to output a signal obtained by performing gamma correction on the output signal of the first phase adjustment circuit 31. This gamma correction represents signal processing for correcting the display characteristics of the display device.
- the second phase adjustment circuit 33 is configured to adjust the phase of the output signal of the gamma correction circuit 39 and output the signal to one input side of the contour addition circuits 34 r, 34 g, and 34 b. .
- the phase adjustment processing by the first phase adjustment circuit 31 and the second phase adjustment circuit 33 includes the delay time required for the gamma processing of the gamma correction circuit 39, the Y signal generation circuit 36, the contour extraction circuit 38, and the gain. This represents a process of adjusting a delay difference between the controller 40 and the delay time required for signal processing in the coefficient multiplying circuit 42.
- the Y signal generation circuit 36 is configured to generate a Y (luminance) signal from digital R, G, and B signals output from the A / D conversion circuits 30 r, 30 g, and 3 Ob.
- the signal generation circuit 36 stores, for example, a ROM (Read Only Memory).
- the R, G, and B signals can be mixed at the mixing ratio specified by the NTSC (National Television System Commi 11 ee) standard to satisfy the following equation (5).
- NTSC National Television System Commi 11 ee
- This is realized by a method of obtaining a Y signal by addition, or a method of obtaining an approximate value of a ⁇ signal satisfying the following equation (6) by bit shift addition as shown in FIG.
- the contour extraction circuit 38 extracts a contour component from the ⁇ signal generated by the ⁇ signal generation circuit 36. And output it.
- the contour extraction circuit 38 is specifically configured as shown in FIG.
- 46 is a ⁇ signal input terminal
- 48 and 50 are first and second line memories as one-line delay elements
- 52 is a vertical contour extraction circuit
- 54 is a contour emphasis frequency setting circuit
- 56 Is a horizontal contour extraction circuit
- 58 is a vertical contour component gain controller
- 60 is a horizontal contour component gain controller
- 62 is a contour synthesizing circuit
- 64 is a calling circuit
- 66 is a gain controller.
- the first and second line memories 48 and 50 generate and output a ⁇ signal obtained by sequentially delaying the ⁇ ⁇ signal input to the input terminal 46 by one line (one scanning line). Is configured.
- the vertical contour extraction circuit 52 includes an adder 68 that adds and outputs the Y signal input to the input terminal 46 and the two-line delayed Y signal output from the second line memory 50, A multiplier 70 for multiplying the output signal of the adder 68 by a coefficient (1 Z 4) and outputting the result; and a coefficient for the one-line delayed Y signal output from the first line memory 48.
- the multiplier 72 includes a multiplier 72 that multiplies the output signal by (1) and outputs the result, and a subtractor 74 that subtracts the output signal of the multiplier 70 from the output signal of the multiplier 72.
- the contour emphasis frequency setting circuit 54 is a circuit for setting the contour emphasis frequency to a predetermined frequency (for example, 1 Z 2 of the sampling frequency Fs). Specifically, as shown in FIG. It is a 5-tap type consisting of four 1-dot delay elements D 1 to D 4 that sequentially delay the Y signal output from the first line memory 48 by one dot (one pixel). Each of the one-dot delay elements D1 to D4 is composed of, for example, D-FF (D-type flip-flop).
- the outline emphasis frequency setting circuit 54 is not limited to the 5-tap type, but may be a 7-tap type including six 1-dot delay elements D1 to D6 connected in series.
- the horizontal contour extraction circuit 56 adds the Y signal output from the first line memory 48 to the 4-dot delayed Y signal output from the fourth 1-dot delay element D4. 6, a multiplier 78 that multiplies the output signal of the adder 76 by a coefficient (1 4) and outputs a 2-dot delayed Y signal output from the second 1-dot delay element D 2 And a coefficient (1 2), and outputs a multiplier 80, and a subtracter 82 for subtracting the output signal of the coefficient unit 78 from the output signal of the coefficient unit 80.
- the gain controller 58 is configured to multiply the vertical contour component extracted by the vertical contour extraction circuit 52 by an adjustable coefficient KV and output the result.
- the gain controller 60 is configured to multiply the horizontal contour component extracted by the horizontal contour extraction circuit 56 by an adjustable coefficient K h and output the result.
- the outline synthesizing circuit 62 is configured to synthesize and output outline components output from each of the gain controllers 58 and 60.
- the coring circuit 64 receives the contour component output from the contour synthesizing circuit 62 in order to remove noise and minute contour components, and suppresses a contour component of the input contour component below a certain level. And output it.
- the coring circuit 64 is configured to have, for example, input / output characteristics as shown in FIG. More specifically, when the contour component input from the contour synthesizing circuit 62 is large and positive, the output is obtained by adding one ⁇ ( ⁇ is a positive constant) to the original component and outputting it. In this case, the output is obtained by adding + ⁇ to the original component and outputting the result, and when the operation result is equal to or more than 1 ⁇ and equal to or less than + ⁇ , the output is fixed to 0.
- the gain controller 66 is configured to multiply the contour component output from the coring circuit 64 by an adjustable coefficient K 1 and output the result to an output terminal 88.
- the gain controller 40 is configured to multiply the contour component output from the contour extraction circuit 38 by an adjustable coefficient ⁇ 2 and output the result.
- One of the gain controllers 66 and 40 may be omitted as necessary.
- the coefficient multiplying circuit 42 multiplies the contour component ⁇ 6 output from the gain controller 40 by a coefficient !: 1: Kg, Kb to obtain a contour component for R, G, B Yer, Yeg, Yeb. Is composed of 84 r, 84 g, and 84 b.
- the coefficients Kr, Kg, and Kb are not limited to the above, but are equivalent to the coefficients of R, G, and B (FIG. 8) used by the Y signal generation circuit 36 to generate the Y signal.
- the contour addition circuits 34 r, 34 g, and 34 b add R, G, and B signals output from the second phase adjustment circuit 33 to the coefficient multipliers 84 r, 84 g, and 84 of the coefficient multiplication circuit 42.
- the configuration is such that the contour components Yer, Yeg, and Yeb output from b are added and output to a display device via output terminals 86r, 86g, and 86b.
- the Y signal generation circuit 36 generates a Y signal from the digital R, G, and B signals output from the A / D conversion circuits 30r, 30g, and 30B.
- the ⁇ signal generation circuit 36 generates a Y signal from digital R, G, B signals by bit shift addition using the circuit of FIG.
- the contour extraction circuit 38 extracts a contour component composed of a horizontal contour component and a vertical contour component from the ⁇ signal. Next, the operation of extracting a contour component by the contour extraction circuit 38 will be described with reference to FIG.
- the vertical lines S1, S2, S3, S4, and S5 represented by dotted lines in Fig. 11 are the sampling of each pixel that is continuously arranged in the horizontal direction along the scanning line including the pixel to be processed. Represents a point.
- the multiplier 8 of the horizontal contour extracting circuit 56 The signal ⁇ output from 0 is input to the + side of the subtractor 82 as shown in FIG.
- the Y signal output from the first line memory 48 and the Y signal output from the fourth 1-dot delay element D 4 of the contour emphasis frequency setting circuit 54 are added by the adder 76 of the horizontal contour extraction circuit 56.
- the result is multiplied by 1 to 4 by the multiplier 78, and is input to one side of the subtractor 82 as a signal 3 as shown in FIG. 11 (c).
- the signal (2-3) calculated in (2) is multiplied by the coefficient Kh in the gain controller 60, and sent to one input side of the contour synthesis circuit 62 as a signal (2) as shown in (d) of FIG. input.
- Vertical lines S 1, S 2, and S 3 represented by dotted lines in FIG. 12 are pixels on the three scanning lines of the scanning line including the pixel to be processed and the preceding and following scanning lines, and include the pixel to be processed. It represents the sampling points of three pixels arranged along the vertical direction.
- the signal ⁇ ⁇ output from the multiplier 72 of the vertical contour extraction circuit 52 becomes The signal is input to the + side of the subtractor 74 as shown in FIG.
- the Y signal input to the input terminal 46 and the 2-line delayed Y signal output from the second line memory 50 are added by the adder 68 of the vertical contour extraction circuit 52, and the multiplier 70 outputs 1 4 And input it to one side of the subtractor 74 as a signal 7 as shown in FIG. 12 (c).
- the signal (6 ⁇ 7) calculated by the subtractor 74 is multiplied by a coefficient KV in the gain controller 58 to obtain a signal ⁇ ⁇ ⁇ as shown in FIG. To the input side of.
- the signal ⁇ ⁇ representing the horizontal contour component and the signal ⁇ ⁇ representing the vertical contour component are synthesized by the contour synthesizing circuit 62, and the coring circuit 64 suppresses the contour component below a certain level to reduce noise.
- the level is adjusted by multiplying the coefficient K1 by the gain controller 66 and output to the output terminal 88.
- the level is adjusted by multiplying by 2 and the coefficient multiplier 4 is multiplied by the coefficients Kr, Kg, and Kb by the multipliers 84r, 84g, and 84b of 2 to obtain contour components Yer, Yeg for R, G, and B. , Y eb, and input to the other input side of the corresponding contour addition circuit 34 r, 34 g, 34 b. Therefore, the amount of contour enhancement can be increased.
- Rh and Rv indicated by two-dot chain lines in (e) of FIGS. 11 and 12 represent the horizontal component and the vertical component of the R signal output from the signal processing / phase adjustment circuit 32.
- Horizontal and vertical components are also output to output terminal 86 r (R + Y er) signal It is the same as the horizontal and vertical components of.
- the contour emphasis component must exceed the dynamic range of the AZD conversion circuit as in the conventional example shown in Fig. 1. There is no. Therefore, even when the analog R, G, and B signals input to the contour emphasizing circuit of the present invention are large amplitude signals or when the amount of contour emphasis is increased, the signal output from the contour emphasizing circuit of the present invention is converted to a digital R signal. There is no black and white loss when displaying images on a display device driven by G, B signals.
- contour addition circuits 34 r, 34 g, and 34 b are placed after the pixel number conversion circuit 37 and the gamma correction circuit 39 to perform pixel number conversion and gamma correction signal processing. Since the contour components Yer, Yeg, and Yeb are added to the digital R, G, and B signals of, the contour components obtained by pixel number conversion and gamma correction as shown in Figs. 5 and 6 are used. And the effect of edge enhancement can be prevented from halving.
- the gain controller 40 adjusts the size of the contour component extracted by the contour extraction circuit 38 and outputs the adjusted signal, and the coefficient Kr, Kg, Kb (Kr + K g + K b-1) and a coefficient multiplying circuit 42 that outputs to the contour adding circuits 34 r, 34 g, and 34 b to increase the contour emphasis amount for R, G, and B.
- the present invention is not limited to this.
- the gain controller 40 and the coefficient multiplying circuit 42 are omitted, and the output of the contour extracting circuit 38 is directly output to the contour adding circuits 34 r, 34 g, It can be used for output to 34b.
- a coring circuit 64 for suppressing and outputting a certain level or less of the contour component output from the contour synthesizing circuit 62 in the contour extraction circuit 38 is provided so as to eliminate the influence of noise.
- the present invention is not limited to this, and can also be applied to a circuit in which the coring circuit 64 is omitted.
- the contour extraction circuit 38 is composed of the first and second line memories, 48, 50, a vertical contour extraction circuit 52, a contour emphasis frequency setting circuit 54, a horizontal contour extraction circuit 56, and a gain controller. 58, 60 and a contour synthesizing circuit 62 to output a contour component obtained by synthesizing a vertical contour component and a horizontal contour component, but the present invention is not limited to this. 38 may be any circuit that includes at least a contour emphasis frequency setting circuit 54 and a horizontal contour extraction circuit 56 and outputs a horizontal contour component.
- the signal processing circuit includes a pixel number conversion circuit and a gamma correction circuit sequentially coupled to the output side of the AZD conversion circuit, and the Y signal generation circuit generates a Y signal from the output signal of the pixel number conversion circuit.
- the present invention is not limited to this.
- the signal processing circuit consists of a gamma correction circuit and a pixel number conversion circuit sequentially coupled to the output side of the AZ D conversion circuit, and the Y signal generation circuit generates the Y signal from the output signal of the gamma correction circuit It can also be used for those who have done it.
- the present invention can also be applied to a configuration in which a Y signal generation circuit generates a Y signal from an output signal of a gamma correction circuit or a pixel number conversion circuit.
- the contour emphasizing circuit according to the present invention can be applied to a display device (for example, a matrix type display device) driven by a digital color video signal, such as a PDP or an LCD, for converting an analog color video signal.
- the contour emphasis circuit according to the present invention can be used to prevent the contour emphasis effect from being reduced by half.
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Description
Claims
Priority Applications (6)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
EP97908503A EP0973330A4 (en) | 1997-03-25 | 1997-03-25 | CONTOURING CIRCUIT |
KR10-1999-7008665A KR100457043B1 (ko) | 1997-03-25 | 1997-03-25 | 윤곽강조회로 |
US09/402,028 US6433836B1 (en) | 1997-03-25 | 1997-03-25 | Contour emphasizing circuit |
AU20430/97A AU739840B2 (en) | 1997-03-25 | 1997-03-25 | Contour emphasizing circuit |
PCT/JP1997/000997 WO1998043412A1 (fr) | 1997-03-25 | 1997-03-25 | Circuit d'accentuation de contours |
CA002284923A CA2284923C (en) | 1997-03-25 | 1997-03-25 | Contour emphasizing circuit |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
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PCT/JP1997/000997 WO1998043412A1 (fr) | 1997-03-25 | 1997-03-25 | Circuit d'accentuation de contours |
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Publication Number | Publication Date |
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WO1998043412A1 true WO1998043412A1 (fr) | 1998-10-01 |
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Application Number | Title | Priority Date | Filing Date |
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PCT/JP1997/000997 WO1998043412A1 (fr) | 1997-03-25 | 1997-03-25 | Circuit d'accentuation de contours |
Country Status (6)
Country | Link |
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US (1) | US6433836B1 (ja) |
EP (1) | EP0973330A4 (ja) |
KR (1) | KR100457043B1 (ja) |
AU (1) | AU739840B2 (ja) |
CA (1) | CA2284923C (ja) |
WO (1) | WO1998043412A1 (ja) |
Families Citing this family (9)
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JP2000253418A (ja) * | 1999-03-03 | 2000-09-14 | Alps Electric Co Ltd | 映像信号処理回路、ビューファインダ装置、テレビジョンカメラ及び映像モニタ装置 |
JP3538074B2 (ja) * | 1999-08-02 | 2004-06-14 | Necビューテクノロジー株式会社 | 輪郭強調回路および輪郭強調方法 |
JP2003032513A (ja) * | 2001-07-17 | 2003-01-31 | Sanyo Electric Co Ltd | 画像信号処理装置 |
JP4822630B2 (ja) * | 2001-08-14 | 2011-11-24 | キヤノン株式会社 | 色信号処理装置、撮像装置およびそれらの制御方法 |
JP4390506B2 (ja) * | 2003-09-02 | 2009-12-24 | 三洋電機株式会社 | 水平輪郭補正回路 |
JP2005260517A (ja) * | 2004-03-11 | 2005-09-22 | Sanyo Electric Co Ltd | 画像信号処理装置 |
FR2867935A1 (fr) * | 2004-03-17 | 2005-09-23 | Thomson Licensing Sa | Procede de rehaussement des contours dans une image |
JP4398809B2 (ja) * | 2004-06-30 | 2010-01-13 | 株式会社東芝 | 映像信号処理装置及び映像信号処理方法 |
JP2010288150A (ja) * | 2009-06-12 | 2010-12-24 | Toshiba Corp | 固体撮像装置 |
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-
1997
- 1997-03-25 US US09/402,028 patent/US6433836B1/en not_active Expired - Fee Related
- 1997-03-25 KR KR10-1999-7008665A patent/KR100457043B1/ko not_active IP Right Cessation
- 1997-03-25 CA CA002284923A patent/CA2284923C/en not_active Expired - Fee Related
- 1997-03-25 WO PCT/JP1997/000997 patent/WO1998043412A1/ja not_active Application Discontinuation
- 1997-03-25 AU AU20430/97A patent/AU739840B2/en not_active Ceased
- 1997-03-25 EP EP97908503A patent/EP0973330A4/en not_active Withdrawn
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JPH01259464A (ja) * | 1988-04-11 | 1989-10-17 | Konica Corp | 鮮鋭度改善回路 |
JPH03171978A (ja) * | 1989-11-30 | 1991-07-25 | Sony Corp | 固体撮像装置の信号処理回路 |
JPH07143365A (ja) * | 1993-11-15 | 1995-06-02 | Sony Corp | ディジタル信号処理カメラ |
JPH0865548A (ja) * | 1994-08-19 | 1996-03-08 | Canon Inc | 撮像装置 |
JPH08163412A (ja) * | 1994-11-30 | 1996-06-21 | Sony Corp | ビデオカメラ |
Also Published As
Publication number | Publication date |
---|---|
CA2284923C (en) | 2005-08-02 |
KR20010005601A (ko) | 2001-01-15 |
US6433836B1 (en) | 2002-08-13 |
EP0973330A1 (en) | 2000-01-19 |
EP0973330A4 (en) | 2000-01-19 |
AU739840B2 (en) | 2001-10-18 |
AU2043097A (en) | 1998-10-20 |
CA2284923A1 (en) | 1998-10-01 |
KR100457043B1 (ko) | 2004-11-12 |
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