Classifications

• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
  • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
  • H01L29/66007—Multistep manufacturing processes
  • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
  • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
  • H01L29/66409—Unipolar field-effect transistors
  • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
  • H01L29/66666—Vertical transistors
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
  • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
  • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
  • H01L29/76—Unipolar devices, e.g. field effect transistors
  • H01L29/772—Field effect transistors
  • H01L29/78—Field effect transistors with field effect produced by an insulated gate
  • H01L29/7827—Vertical transistors

Definitions

• the invention is therefore based on the problem of specifying a method for producing a vertical MOS transistor in which the high-frequency and logic properties of the vertical MOS transistor can be compared with those of planar MOS transistors.
• a mask with an opening is formed on a main surface of a semiconductor substrate, the main surface of the semiconductor substrate being exposed within the opening.
• a layer sequence is grown by selective epitaxy, each of which has a layer for a lower source / drain region, a channel region and an upper source / drain region.
• facets are formed at the edge of the layer sequence, so that the thickness of the layers at the edge of the opening is less than in the middle.
• Gate dielectric and gate electrode are formed at the edge of the layer sequence.
• This property of selective epitaxy is used to reduce the thickness of the layers at the edge of the layer sequence than to realize in the middle of the layer sequence. It is thereby achieved that the base width of the parasitic bipolar transistor, which forms in the middle of the layer sequence, is larger than the channel width of the vertical MOS transistor, which is formed at the edge of the layer sequence. The channel properties are therefore decoupled from the volume properties in the layer sequence. Since the parasitic bipolar transistor has a larger base width than the channel length of the vertical MOS transistor, the vertical MOS transistor determines the properties of the structure.
• the mask preferably has SiO 2 and / or Si3N4 at least on the surface.
• the thickness ratio between the middle and the edge of the layer sequence can be set between 2 and 3 depending on the growth conditions.
• first insulating layer a conductive layer and a second insulating layer over the entire surface when the mask is formed, in which the opening is produced.
• the gate dielectric is formed on the exposed surface of the conductive layer.
• the gate electrode is formed from the conductive layer.
• the lower source / drain region is preferably grown at such a height that it closes with the first insulating layer at the edge of the opening.
• the channel region is grown in height such that it ends at the edge of the opening with the "conductive layer. In this way the advertising, the parasitic capacitances of the gate electrode is minimized, resulting in a further improvement in high frequency characteristics.
• the gate electrode is formed, for example, by depositing and structuring a conductive layer.
• the mask is preferably formed from insulating material, in this case from a first insulating layer and a second insulating layer.
• the first insulating layer is arranged on the main surface of the substrate.
• the second insulating layer is arranged on the first insulating layer.
• the second insulating layer can be etched selectively with respect to the first insulating layer and the layer sequence.
• the lower source / drain region is grown to such a height that it is flush with the first insulating layer at the edge of the opening.
• an opening is formed in the second insulating layer, which surrounds the channel region in a ring. After the gate dielectric has been formed, the opening is filled with a conductive layer.
• the gate electrode is finally formed by structuring the conductive layer, for example with the aid of planarization steps.
• the opening in the second insulating layer protrude significantly beyond the layer sequence on at least one side of the layer sequence allow.
• the opening has an expansion on at least one side of the layer sequence.
• island-shaped auxiliary structures made of the material of the second insulating layer are arranged.
• the opening in the region of the widening has a lattice-shaped cross section.
• the conductive layer also fills the opening in the area of the expansion.
• the gate electrode also has a grid-shaped cross section, at least in part.
• a contact hole to the gate electrode can subsequently be opened, which can be considerably coarser in its structural fineness than the structures of the opening. In this way, the contact hole can be dimensioned such that electrical properties of the gate contact are optimized.
• a further improvement of the high-frequency properties by minimizing the parasitic capacitances is achieved in that the layer sequence is structured in a ring shape and the ring structure layer sequence is provided with an insulating filling.
• the removal of the semiconductor material in the interior of the layer sequence suppresses the formation of space charge zones, which in turn cause parasitic capacitances.
• FIG. 1 shows a section through a semiconductor substrate with a connection region and a mask.
• FIG. 2 shows the section through the semiconductor substrate after formation of a layer sequence by selective epitaxy.
• FIG. 3 shows the section after the formation of an opening which surrounds the layer sequence in a ring and the formation of a gate dielectric.
• FIG. 4 shows a top view of FIG. 3.
• Figure 5 shows the section shown in Figure 3 after filling the opening with a conductive layer and creating a planarizing insulation layer.
• FIG. 6 shows the section after formation of a gate electrode by structuring the conductive layer.
• Figure 7 shows the section after opening of contact holes.
• FIG. 8 shows the section after the formation of metal silicide connection surfaces, a passivation layer and contacts.
• FIG. 9 shows a section through a semiconductor substrate with a connection region and a mask.
• Figure 10 shows the section after formation of a layer sequence by selective epitaxy.
• FIG. 11 shows the section after forming an opening which surrounds the layer sequence in a ring.
• FIG. 12 shows the section after formation of a gate electrode, a passivation layer and contacts.
• Figure 13 shows a section through a semiconductor substrate having a terminal area and a mask having a conductivity "compatible layer, is formed on the surface of a Ga tedielektrikum.
• FIG. 14 shows the section after formation of a layer sequence by selective epitaxy and deposition and planarization of an insulating layer.
• FIG. 15 shows the section after etching back the insulating layer and forming spacers on the side walls of the mask.
• FIG. 16 shows the section after the layer sequence has been structured in a ring using the spacer as a mask, the surface of the connection region being exposed.
• FIG. 17 shows the section after the annularly structured layer sequence has been provided with an insulating filling and after the formation of contacts.
• a connection region 12 is placed in a substrate 11 made of monocrystalline silicon, for example a monocrystalline silicon wafer or the monocrystalline silicon layer of an SOI substrate, by implantation with arsenic or phosphorus with 5 ⁇ 10 1 ⁇ c 2 # 40 k e y and Subsequent annealing to activate the dopant is formed (see Figure 1).
• a mask 13 is then formed on the substrate 11.
• a silicon nitride layer 131 with a thickness of, for example, 70 nm is applied over the entire surface and a silicon oxide layer 132 with a thickness of, for example, 500 nm is applied thereon.
• the silicon oxide layer 132 and the silicon nitride layer 131 are subsequently patterned by anisotropic etching, an opening 130 being formed.
• the surface of the connection region 12 is exposed within the opening 130.
• a layer sequence 14 is grown by selective epitaxy, which has a first layer 141 for a lower source / drain region, a second layer 142 for a channel region and a third layer 143 for an upper source / drain region (see Figure 2).
• the first layer 141 is grown, for example, from n-doped silicon with a dopant concentration of 5 ⁇ 10 - ⁇ - 9 c ⁇ 3 in a layer thickness of 100 nm.
• the second layer 142 is grown, for example, from p-doped silicon with a dopant concentration of lO 1 ⁇ cm ⁇ 3 in a layer thickness of 100 nm.
• the third layer 143 is of n-doped silicon with a dopant concentration of 5 x lO ⁇ 1 cm ⁇ 3 nm grown in a layer thickness of 200th
• the selective epitaxy is carried out in such a way that facets are formed at the edge of the opening 130.
• the first layer 141, second layer 142 and the third layer 143 have a smaller layer thickness at the edge of the opening 130 than in the center of the opening 130.
• the specified layer thicknesses apply to the center of the opening.
• the selective epitaxy is carried out, for example, using the following process gases Si2H2Cl2 B2H, ASH3, PH3, HC1, H2 in the temperature range between 700 to 950 ° C. and the pressure range between 5 to 20,000 Pa on silicon wafers with a [110] fat orientation .
• the first layer 141 is grown in such a way that its thickness at the edge of the opening 130 approximately corresponds to the thickness of the silicon nitride layer 131.
• an opening 15 is then formed in the silicon oxide layer 132 which covers the side walls of the
• Layer sequence 14 exposed (see Figure 3 and supervision in Figure 4).
• the surface of the silicon nitride layer 131 is exposed in the opening 15.
• the opening 15 has a widening 150 to the side of the layer sequence 14, in which inseil-shaped structures 132 'made of the material of the silicon oxide layer
• the insular structures 132 are arranged (see Figure 4).
• the insular structures 132 ' are arranged in a matrix, so that the opening 15 has a lattice-shaped cross section in the area of the widening 150.
• the opening 15 overlaps the layer sequence 14 laterally. Since the adjustment in lithographic processes is more precise than the minimum structure size, the distance between the layer sequence 14 and the structured silicon oxide layer 132 is less than a minimum structure size.
• the distance between the layer sequence 14 and the silicon oxide layer 132 or the island-shaped structures 132 ′ is, for example, 0.3 ⁇ m.
• the structure size of the island-shaped structures 132 ' is in each case a minimum structure size, for example 0.6 ⁇ m.
• a thermal dielectric is subsequently formed on the exposed surface of the second layer 142 and the third layer 143 from SiO 2 in a layer thickness of 3 to 5 nm.
• a conductive layer 17 is then deposited over the entire surface. The thickness of the conductive layer 17 is adjusted so that the space between the layer sequence 14 and the silicon oxide layer 132 is filled. All materials that are suitable as gate electrodes are suitable for the conductive layer 17, in particular doped polysilicon, metal silicide, metal.
• the conductive layer 17 is formed, for example, from n-doped polysilicon in a layer thickness of 400 nm (see FIG. 5).
• a planarization layer 18 is then formed on the conductive layer 17, for example from photoresist or another spin-on material. The surface of the conductive layer 17 is leveled, for example, by planarization etching or chemical mechanical polishing. Subsequently, the conductive layer 17 is etched highly selectively to SiO 2. It will be from a conductive electrode 170 is formed in the conductive layer 17 (see FIG. 6).
• a further SiO 2 layer is then applied over the entire surface in a layer thickness of, for example, 70 nm and structured with the aid of a photoresist mask 19.
• the surface of the connection region 12, the gate electrode 170 and the third layer 143 are partially exposed (see FIG. 7).
• Self-aligned siliconization for example in a salicide process with titanium, forms silicide connections 110 on the exposed surface of the connection region 12, the gate electrode 170 and the third layer 143 (see FIG. 8).
• the silicide connections 110 each serve to reduce the parasitic series resistances.
• contacts 112 to the connection region 12 are formed by forming a metal layer and structuring the metal layer third layer 143, which forms the upper source / drain region, and to the gate electrode 170.
• the contact hole to the gate electrode 170 is not visible in the section shown in FIG. 8. It is located in the area of the widening 150 (see FIG. 4). Due to the grid-like structure of the gate electrode 170 in the area of the widening 150 (see FIG.
• the contact hole to the gate electrode 170 it is possible to provide the contact hole to the gate electrode 170 with a larger cross section than corresponds to the structure sizes of the gate electrode 170 in this area.
• the contact hole to the gate electrode 170 overlaps one or more of the island-shaped structures 132 '.
• SOI substrate is formed, for example, by masked implantation and subsequent tempering to heal the implantation damage.
• a mask 23 is then formed on the surface of the substrate 21, which has an opening 230 in which the surface of the connection region 22 is exposed (see FIG. 9).
• connection layer 231 a connection layer 231, a silicon nitride layer 232 and a silicon oxide layer 233 are applied to the substrate 21.
• the connection layer 231 is formed, for example, from highly doped polysilicon in a layer thickness of 50 nm. All electrically conductive materials, in particular doped polysilicon, silicide, metal, are suitable for the connection layer 231.
• the silicon nitride layer 232 is applied in a layer thickness of 20 nm.
• the silicon oxide layer 233 is applied in a layer thickness of, for example, 500 nm.
• connection layer 231, the silicon nitride layer 232 and the silicon oxide layer are structured by anisotropic etching, for example with CHF3, O2 (for nitride, oxide) HBr, CI2 He, O2 (for polysilicon).
• the opening 230 is thereby formed.
• Silicon oxide spacers 234 are subsequently formed on the side walls of the connection layer 231, the silicon nitride layer 232 and the silicon oxide layer 233 facing the opening 230 by conformal deposition and anisotropic etching back.
• the silicon oxide spacers have a width of 10 nm (see FIG. 9).
• a layer sequence " 24 is grown in the opening 230, which has a first layer 241 for a lower source / drain region, a second layer 242 for a channel region and a third layer 243 for an upper source / drain region (see FIG 10) .
• Layer 312 contacts 312 to the gate electrode 370, to the polysilicon layer 35 and to the connection region 32 are subsequently formed.

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• Engineering & Computer Science (AREA)
• Microelectronics & Electronic Packaging (AREA)
• Power Engineering (AREA)
• Physics & Mathematics (AREA)
• Ceramic Engineering (AREA)
• Condensed Matter Physics & Semiconductors (AREA)
• General Physics & Mathematics (AREA)
• Computer Hardware Design (AREA)
• Manufacturing & Machinery (AREA)
• Thin Film Transistor (AREA)
• Electrodes Of Semiconductors (AREA)
• Insulated Gate Type Field-Effect Transistor (AREA)

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• 1997
  • 1997-03-19 DE DE1997111481 patent/DE19711481A1/de not_active Withdrawn
• 1998
  • 1998-03-03 TW TW87103048A patent/TW392254B/zh not_active IP Right Cessation
  • 1998-03-11 WO PCT/EP1998/001405 patent/WO1998042015A1/de active Application Filing

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