WO1998006134A1 - Groupement de diodes electroluminescentes utilise dans une structure matricielle - Google Patents

Groupement de diodes electroluminescentes utilise dans une structure matricielle Download PDF

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Publication number
WO1998006134A1
WO1998006134A1 PCT/DE1997/001625 DE9701625W WO9806134A1 WO 1998006134 A1 WO1998006134 A1 WO 1998006134A1 DE 9701625 W DE9701625 W DE 9701625W WO 9806134 A1 WO9806134 A1 WO 9806134A1
Authority
WO
WIPO (PCT)
Prior art keywords
led array
layer
conductive layer
leds
array according
Prior art date
Application number
PCT/DE1997/001625
Other languages
German (de)
English (en)
Inventor
Ernst Nirschl
Walter Wegleiter
Original Assignee
Siemens Aktiengesellschaft
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Siemens Aktiengesellschaft filed Critical Siemens Aktiengesellschaft
Priority to JP10507475A priority Critical patent/JP2000516035A/ja
Priority to EP97936580A priority patent/EP0917736A1/fr
Publication of WO1998006134A1 publication Critical patent/WO1998006134A1/fr

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/15—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components having potential barriers, specially adapted for light emission
    • H01L27/153—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components having potential barriers, specially adapted for light emission in a repetitive configuration, e.g. LED bars
    • H01L27/156—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components having potential barriers, specially adapted for light emission in a repetitive configuration, e.g. LED bars two-dimensional arrays
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B41—PRINTING; LINING MACHINES; TYPEWRITERS; STAMPS
    • B41J—TYPEWRITERS; SELECTIVE PRINTING MECHANISMS, i.e. MECHANISMS PRINTING OTHERWISE THAN FROM A FORME; CORRECTION OF TYPOGRAPHICAL ERRORS
    • B41J2/00—Typewriters or selective printing mechanisms characterised by the printing or marking process for which they are designed
    • B41J2/435—Typewriters or selective printing mechanisms characterised by the printing or marking process for which they are designed characterised by selective application of radiation to a printing material or impression-transfer material
    • B41J2/447—Typewriters or selective printing mechanisms characterised by the printing or marking process for which they are designed characterised by selective application of radiation to a printing material or impression-transfer material using arrays of radiation sources
    • B41J2/45—Typewriters or selective printing mechanisms characterised by the printing or marking process for which they are designed characterised by selective application of radiation to a printing material or impression-transfer material using arrays of radiation sources using light-emitting diode [LED] or laser arrays
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05552—Shape in top view
    • H01L2224/05554—Shape in top view being square

Definitions

  • the invention relates to an LED array with a plurality of rows and S columns, of LEDs on a semiconductor substrate, the LEDs being individually controllable and for this purpose a common electrical connection via a first conductive layer in the semiconductor substrate.
  • LEDs Light E itting Diode
  • luminescent diodes in matrix arrangements
  • Such LED arrays can be found, for example, in LED screens and LED printer applications.
  • the LEDs are produced on a semiconductor substrate and a common electrical connection is implemented via a conductive layer in the semiconductor substrate.
  • each LED is also connected individually with a bond connection. A large number of wire bond connections are therefore required for this technology, which leads to extreme demands on the LED contacts and the bond technology. These difficulties also limit the yield.
  • the invention is based on the objective of creating an LED array on a semiconductor substrate of the type mentioned at the outset, which manages with the smallest possible number of bond connections and is particularly easy to produce.
  • an at least semi-insulating layer is arranged below the first conductive layer in the semiconductor substrate, the first conductive layer is interrupted by trenches in such a way that the trenches extend to the at least semi-insulating layer such that the first conductive layer underneath Formation of conductor tracks in longitudinal strips for row-wise electrical connection of the LEDs is divided that each conductor track of the first conductive Layer is connected to an electrical connection contact, so that for the column-wise connection of the LEDs there is a second electrically conductive layer running on the semiconductor substrate, which is subdivided into transverse strips to form further separate conductor tracks, that between the second electrically conductive one running on the semiconductor substrate Layer and the first conductive layer in the semiconductor substrate, an insulating layer is arranged.
  • the basic idea of the invention is therefore to enable individual LEDs to be controlled by two interconnect levels.
  • the one below the conductor track level is divided into the required individual tracks by trench isolation. In this way, the number of bond connections required is greatly reduced and an LED array with particularly small dimensions is created.
  • the LED array is preferably designed such that the first conductive layer in the semiconductor substrate forms p-contacts for the LEDs and the second conductive layer on the semiconductor substrate forms n-contacts for the LEDs. This assignment can be realized particularly easily by the properties of the layers used in the semiconductor.
  • the second conductive layer on the semiconductor substrate is preferably metallic, since on the one hand a metallization lying on the semiconductor substrate is easy to produce and on the other hand can be used particularly advantageously as an n-contact.
  • the insulating layer between the conductive layer on the semiconductor substrate and the first conductive layer in the semiconductor substrate is preferably formed as an oxide layer. A1 2 0 3 is used for this purpose, for example. As an alternative to this, Si3 4 can also be used, for example.
  • the semiconductor substrate is on gallium arsenide (GaAs)
  • the second conductive layer in the semiconductor substrate is p-doped GaAs
  • the at least semi-iso- layer undoped semi-insulating GaAs there is also the possibility of designing the LED array using silicon technology.
  • the trenches for separating the second conductive layer in the semiconductor substrate are preferably produced using a separation etch.
  • the subsequently generated insulating layer between the conductive layers follows the course of the trenches.
  • the second conductive layer on the semiconductor substrate can also follow the course of the trenches, but it is preferred to fill the trenches with a filling technique and to execute the second conductive layer over the trenches.
  • connection contacts of the first conductive layer in the semiconductor are produced using a via-hole technique.
  • any number of connections can be made via the back of the chip.
  • the connections can be made on one side to the LED side either via the rear or via parallel electrical connections.
  • the at least semi-insulating layer is produced using buried isolation layer technology.
  • the LED arrays according to the invention can be used for screens and a large number of other applications.
  • a particularly preferred use of the LED arrays according to the invention is, however, use in an LED printer with two rows of LEDs, the rows forming a print line.
  • the two rows of LEDs are preferably arranged offset to one another in order to compensate for the geometrical spacing of the LEDs in a row and to be able to produce a continuous pressure line.
  • the two connection contacts per LED pair required for the two rows are preferably arranged on opposite sides of an LED array, since in this way a particularly simple routing of the connection contacts is possible. In this application, the number of wire bond connections required is reduced by 50% + 2 wire bond connections.
  • FIG. 1A shows a plan view of an LED array according to the invention produced with a separation etching according to a first example
  • Fig. 1B is a cross section through the LED array according to 'Fig. 1A;
  • FIG. 2A shows a plan view of an LED array according to the invention produced with a filling technology according to a second example
  • Fig. 2B shows a cross section through the LED array
  • 3A shows a plan view of a LED according to the invention manufactured using a via-hole technique
  • Fig. 3B shows a cross section through the LED array
  • FIG. 4A shows a plan view of an LED array produced using a buried isolation layer technology according to a fourth example
  • FIG. 4B is a cross-sectional view of the LED array according ⁇ Fig. 4A.
  • LEDs 1 to 6 are shown, the LEDs 1, 3 and 5 forming a first row and the LEDs 2, 4 and 6 forming a second row. Adjacent LEDs of the parallel rows are each connected by a common n-type metallization, which has an n-type contact 7 at one end. Furthermore, p-connection contacts 8 and 9 are provided, which are arranged on opposite sides of the LED array. A potential A becomes the first row of LEDs (LED 1, LED 3, LED 5) via the p-connector 8 and a potential B becomes the second row of LEDs (LED 2, LED 4) via the second p-connector 9 , LED 6).
  • FIG. 1B shows a cross section along a line through LEDs 1 and 2 of the LED array shown in FIG. 1A.
  • a conductive layer which consists of p-doped GaAs, is arranged on a semi-insulating GaAs layer 14.
  • a trench 10 separates the p-doped GaAs layer into two regions, the p-doped GaAs layer 12 being at a potential A and the p-doped GaAs layer 13 being at a potential B.
  • Above the p-doped GaAs layer are n-doped GaAs regions 15 which form pn junctions with the p-doped GaAs layer and which form the LEDs 1 and 2.
  • the metal layer 16 is separated from the underlying p-doped GaAs layer by an oxide layer 11. As a result, the contact takes place exclusively at the LEDs 1 and 2.
  • the p-terminal contact 8 serves to apply a potential A to the p-doped GaAs region 12.
  • the p-terminal contact 9 serves to apply a potential B to the p-doped GaAs - Area 13.
  • a p-doped GaAs is first epitaxially placed on the semi-insulating GaAs layer 14.
  • FIGS. 2A and 2B show a top view of an LED array which is produced using separation etching and filling technology.
  • the meaning is analogous to the reference symbols used in FIGS. 1A and 1B.
  • a filling technique was first carried out here in the trench 10 after the oxide deposition, the trench having been filled with a filler 17, so that the metallization and structuring of the metal layer 16 to form the columns Contacts is particularly easy to carry out.
  • a region 18 has also been preserved on which the n-contact 7 is formed.
  • the connection contact 7 with the LEDs 1 and 2 is at the same level.
  • the resulting small trench 19 is also filled with the backfill technology, so that the n-metallization is performed on one level over its entire length.
  • the metallization also ends in the region of the LEDs 2, 4 and 6 and does not extend beyond them, as is the case, for example, in the embodiment described in FIGS. 1A and 1B.
  • the p-terminal contacts 8 and 9 are arranged in a plane on opposite sides of the LED array and in direct contact with the underlying conductive layer 12, 13. Another form of contacting, in particular when used of an array with more than two rows of LEDs is necessary, a contact hole technique (via-hole technique) shown in FIG. 3A.
  • the p-terminal contacts 8 and 9 are arranged on the same side of the LED array, but at different levels.
  • the p-terminal contact 9 for the potential B is guided by means of a via-hole technique through a via-hole 20 through the semi-insulating GaAs layer 14 and is on the back of the semiconductor substrate with an electrical layer 21 or path to the p-doped GaAs Layer 13 performed.
  • the electrically conductive layer 21 on the back of the chip is protected by a back passivation 25 made of aluminum oxide or silicon nitride.
  • the electrical conductor is guided through the semi-insulating GaAs layer 14 into an additionally p'-doped GaAs layer 23, 24. This is in direct connection with the p-doped GaAs layer 13.
  • the additional p + -doped GaAs layer 24 is introduced for better contact with the electrical conductor 21 via the via-hole 22 and is exactly like the p-doped GaAs Layer 13 interrupted by trench 10.
  • the p * -doped GaAs layer 23 is at the potential A and the p "-doped GaAs layer 24 is at the potential B. If several rows of LEDs are provided, different electrically conductive ones must be parallel to each other on the back of the chip Lanes 21 are produced which each contact the corresponding row of LEDs via via-holes In addition to the p-connection contact 9 for the potential B, a number of further p-connection contacts are then necessary on the semi-insulating GaAs 14. Alternatively, the connection contacts could be used can also be created directly through the via holes on the back of the chip.
  • FIGS. 4A and 4B Another embodiment of the LED array according to the invention is shown in FIGS. 4A and 4B.
  • ISA / EP least semi-insulating GaAs layer formed as a buried insulation layer and not as a substrate as in the previous examples.
  • a p-doped GaAs substrate 26 is used, on which an undoped semi-insulating GaA ⁇ layer 14 is grown epitaxially.
  • This is followed in the usual way by a p- or p + -doped GaAs layer 12, 13 and an n-doped GaAs layer 15.
  • These layers are also grown epitaxially.
  • the semi-insulating GaAs layer 13 has been produced here as a buried insulation layer.
  • the p-terminal contact 8 contacts the p + -doped GaAs layer 12 and thus forms the p-contact for the LED 1.
  • the p-terminal contact 9 for the potential B is at a lower level directly on the p-doped GaAs substrate 26 arranged, which serves as a conductor and makes contact with the LED 2. This takes place via a p-doped diffusion region 27, which connects the p-doped GaAs substrate 26 and the p + -doped GaAs layer 13 and thereby bridges the semi-insulating GaAs layer 14.

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  • Power Engineering (AREA)
  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Optics & Photonics (AREA)
  • Health & Medical Sciences (AREA)
  • General Health & Medical Sciences (AREA)
  • Toxicology (AREA)
  • Led Devices (AREA)
  • Printers Or Recording Devices Using Electromagnetic And Radiation Means (AREA)
  • Devices For Indicating Variable Information By Combining Individual Elements (AREA)

Abstract

L'invention concerne un groupement de diodes électroluminescentes monté sur un substrat semiconducteur, s'utilisant en particulier dans le domaine des imprimantes et permettant de commander facilement de façon individuelle les diodes électroluminescentes. A cet effet, ces dernières sont raccordées par une couche électrique située sur le substrat semiconducteur et divisée en tracés conducteurs sous forme de colonnes. La commande par rangée s'effectue par l'intermédiaire d'une couche électrique (12, 13) située dans le substrat semiconducteur et divisée en tracés conducteurs individuels par des tranchées (10).
PCT/DE1997/001625 1996-08-07 1997-07-31 Groupement de diodes electroluminescentes utilise dans une structure matricielle WO1998006134A1 (fr)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP10507475A JP2000516035A (ja) 1996-08-07 1997-07-31 マトリックス装置構成のｌｅｄアレイ
EP97936580A EP0917736A1 (fr) 1996-08-07 1997-07-31 Groupement de diodes electroluminescentes utilise dans une structure matricielle

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
DE19631907A DE19631907A1 (de) 1996-08-07 1996-08-07 LED-Array in Matrixanordnung
DE19631907.2 1996-08-07

Publications (1)

Publication Number Publication Date
WO1998006134A1 true WO1998006134A1 (fr) 1998-02-12

Family

ID=7802052

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/DE1997/001625 WO1998006134A1 (fr) 1996-08-07 1997-07-31 Groupement de diodes electroluminescentes utilise dans une structure matricielle

Country Status (5)

Country Link
EP (1) EP0917736A1 (fr)
JP (1) JP2000516035A (fr)
CN (1) CN1231769A (fr)
DE (1) DE19631907A1 (fr)
WO (1) WO1998006134A1 (fr)

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE10011318A1 (de) * 2000-03-13 2001-09-20 Visicontrol Ges Fuer Elektroni Vorrichtung zur Prüfung und/oder Vermessung von Prüflingen
GB0302580D0 (en) 2003-02-05 2003-03-12 Univ Strathclyde MICRO LEDs
US7994524B1 (en) * 2007-09-12 2011-08-09 David Yaunien Chung Vertically structured LED array light source
CN103700682A (zh) * 2012-05-04 2014-04-02 奇力光电科技股份有限公司 发光二极管结构及其制造方法
TW201347141A (zh) * 2012-05-04 2013-11-16 Chi Mei Lighting Tech Corp 發光二極體結構及其製造方法
CN104218133B (zh) * 2014-08-26 2017-04-26 华灿光电股份有限公司 一种发光二极管芯片及其制造方法

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0011418A1 (fr) * 1978-11-20 1980-05-28 THE GENERAL ELECTRIC COMPANY, p.l.c. Fabrication de dispositifs d'affichage électroluminescents
US5160492A (en) * 1989-04-24 1992-11-03 Hewlett-Packard Company Buried isolation using ion implantation and subsequent epitaxial growth
US5449926A (en) * 1994-05-09 1995-09-12 Motorola, Inc. High density LED arrays with semiconductor interconnects

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH04336260A (ja) * 1991-05-14 1992-11-24 Eastman Kodak Japan Kk 発光ダイオードプリンタヘッド

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0011418A1 (fr) * 1978-11-20 1980-05-28 THE GENERAL ELECTRIC COMPANY, p.l.c. Fabrication de dispositifs d'affichage électroluminescents
US5160492A (en) * 1989-04-24 1992-11-03 Hewlett-Packard Company Buried isolation using ion implantation and subsequent epitaxial growth
US5449926A (en) * 1994-05-09 1995-09-12 Motorola, Inc. High density LED arrays with semiconductor interconnects

Also Published As

Publication number Publication date
CN1231769A (zh) 1999-10-13
EP0917736A1 (fr) 1999-05-26
JP2000516035A (ja) 2000-11-28
DE19631907A1 (de) 1998-02-12

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