WO1998001967A2 - Schaltungsanordnung zur detektion von analogen vermittlungs- und prüfsignalen - Google Patents
Schaltungsanordnung zur detektion von analogen vermittlungs- und prüfsignalen Download PDFInfo
- Publication number
- WO1998001967A2 WO1998001967A2 PCT/AT1997/000151 AT9700151W WO9801967A2 WO 1998001967 A2 WO1998001967 A2 WO 1998001967A2 AT 9700151 W AT9700151 W AT 9700151W WO 9801967 A2 WO9801967 A2 WO 9801967A2
- Authority
- WO
- WIPO (PCT)
- Prior art keywords
- detection
- detectors
- digital
- inputs
- analog
- Prior art date
Links
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04M—TELEPHONIC COMMUNICATION
- H04M3/00—Automatic or semi-automatic exchanges
- H04M3/005—Interface circuits for subscriber lines
Definitions
- the invention relates to a circuit arrangement for the detection of analog switching and test signals on one or more transmission lines of a message transmission system, in particular a telephone system, via which transmission lines subscribers can be connected to a central point, the transmission lines in each case, preferably with the interposition of a signal attenuator, with the inputs of various detectors for the detection and processing of switching and test signals, e.g. for call detection, subscriber supply voltage detection, polarity detection, charge pulse detection, for test signal detection etc. are connected.
- a number of detectors which are constructed as individual function blocks and predominantly with discrete components, are provided for the detection of switching signals, such as ringing voltage, charge pulses, supply voltage, polarity and signals for testing the transmission line, of branch exchange systems or apron facilities of a telephone system. These detectors recognize the switching signals and carry out an evaluation of the amplitude, frequency, polarity, signal duration or the like. in accordance with international standards and national regulations.
- the disadvantage of such known circuit arrangements is that the individual detector circuits are sometimes very complex and can therefore only be implemented with great effort.
- the object of the invention is to provide a circuit arrangement which allows detection of the switching and test signals in a very small space.
- Another object of the invention is to standardize all switching and test signals evaluating circuits and to reduce the circuitry for them.
- the detectors for detecting and processing switching and test signals are designed as digital detectors with digital inputs and outputs, in that at least one analog / digital between the transmission line (s) and the inputs of the detectors -Converter for converting the analog to digital switching and test signals is switched, and that the analog / digital converter is integrated with the detectors.
- Another feature of the invention may be that the transmission lines are connected to the inputs of a multiplexer circuit, a demultiplexer circuit is connected at the output of each detector, and that the multiplexer and demultiplexer circuit integrated with the A / D converter and the detectors is. As a result, a large number of transmission lines can be monitored without the number of detectors increasing compared to a circuit arrangement for only one transmission line.
- the digital detectors perform a time evaluation, e.g. debounce the processed signals.
- the digital detector is connected to a control channel over which predeterminable values, e.g. the response threshold, adjustable or measured values, e.g. the frequency of a voltage that can be output.
- the determined frequency of a detected voltage can also be output via a suitable control channel and the time evaluation of a signal can be set.
- 1 shows a block diagram of a part of a message transmission system
- 2 shows an embodiment of a circuit arrangement according to the invention
- 3 show further exemplary embodiments of a circuit arrangement according to the invention.
- FIG. 1 shows the schematic arrangement of part of the various functional blocks of a conventional message transmission system, here a telephone system.
- a central point 1 which is designed as a PSTN
- one or more subscribers can be connected via transmission lines 2 to, for example, private branch exchanges or apron devices 6.
- the signals arriving from the transmission line 2 are transmitted on the one hand via a speech interface 5 and on the other hand via an attenuator 3 led to a signal interface with detector circuits. Since the two interfaces are designed with high impedance, the different types of signals can be separated and processed without influencing each other.
- the attenuator 3 reduces the switching and test signals to a value suitable for further processing. In principle, it represents a voltage divider which, for example, maps the subscriber line voltage to a suitable input voltage range for the detectors.
- the detectors have the task of differentiating and evaluating the various switching and test signals.
- the detectors for detecting and processing switching and test signals are designed as digital detectors 8, 9, 10, 11, 12 with digital inputs and outputs and an analog / digital converter 7 is connected between the transmission line or the transmission lines 2 and the inputs of the detectors 8, 9, 10, 1 1, 12 for converting the analog to digital switching and test signals, the analog / digital converter 7 is integrated with the detectors 8, 9, 10, 1 1, 12. This allows a considerable reduction in the amount of circuitry to be achieved and a very large reduction in the size of the entire detector unit.
- the detector 8 is used for the ringing voltage detection, the presence of a ringing voltage being reported at the output of the detector 8 from a predeterminable level, which can optionally have a hysteresis. For increased error security, the signal can be debounced, the frequency of the ringing voltage also being determined and forwarded to the output of the detector 8.
- the detector supply voltage detection can be carried out with the detector 9, with a hysteresis optionally being possible when defining the detector level.
- the detector 10 it is in turn possible to recognize the polarity of the subscriber supply voltage from a predeterminable value, likewise optionally with a hysteresis.
- the detector 1 1 is responsible for the detection of the charge pulses above a certain level, which can optionally be provided with a hysteresis, the charge pulse frequency also being determined and forwarded to the output of the detector 1 1.
- An input voltage at the detector 12 which is greater than the subscriber voltage and above a further predeterminable level, which can optionally have a hysteresis, is recognized in the detector 12 for test purposes and displayed at the output.
- a time evaluation by means of a debouncing function is provided.
- the invention is not limited to the types of detectors described above and also includes detectors for all other switching and test signals for a communication system.
- the integration of the digital detectors with the A / D converter simplifies the circuit arrangement and significantly reduces the overall structure.
- the binary inputs and outputs of the detectors are either processed on an integrated circuit, routed to a ⁇ P or PCM bus, or routed as individual signals to the connections of another integrated circuit.
- 3 has provided two A / D converters 7, 7 "in the signaling interface 4, which have a different input sensitivity.
- the A / D converter 7 ' is designed for higher input voltages and connected to the inputs of the detectors 8, 9, 10, 12 and the A / D converter 7 "is designed for smaller input voltages and with the input of the meter detector 1 1 connected.
- 4 shows an interface according to the invention, in which several transmission lines 2 ', 2 ", 2"' ... are led to the inputs of a multiplexer circuit 13, the output of which are connected to the input of the A / D converter 7. The output of the A / D converter is again connected to the inputs of the various detectors 8, 9, 10, 1 1, 12.
- each output of a detector 8, 9, 10, 11, 12 is connected to the input of a demultiplexer circuit, not shown.
- Multiplexer and demultiplexer circuit are integrated together with the A / D converter 7 and the detectors 8, 9, 10, 1 1, 12. This allows the detectors to be used multiple times.
- the embodiment of the invention shown in FIG. 5 includes a control channel 13 for each detector, via which a predetermined value, e.g. the response threshold, preferably with a hysteresis range, of the detectors 8, 9, 10, 1 1, 12 is adjustable.
- the control channels 13 lead to a central control, not shown, by means of which the predeterminable values can be entered digitally.
- the control channels 13 according to the wishes of the operator or the national requirements, e.g. the response threshold of the individual detectors can be adapted appropriately.
- measured values e.g. the frequency of a voltage to be output to the central controller.
- time evaluation of the detector output voltage for example for debouncing, can be set.
Landscapes
- Engineering & Computer Science (AREA)
- Signal Processing (AREA)
- Monitoring And Testing Of Exchanges (AREA)
- Arrangements For Transmission Of Measured Signals (AREA)
Abstract
Description
Claims
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
AU33281/97A AU3328197A (en) | 1996-07-03 | 1997-07-03 | Circuit configuration for detection of analogue switching and check signals |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
AT0117796A AT406534B (de) | 1996-07-03 | 1996-07-03 | Schaltungsanordnung zur detektion von analogen vermittlungs- und prüfsignalen |
ATA1177/96 | 1996-07-03 |
Publications (2)
Publication Number | Publication Date |
---|---|
WO1998001967A2 true WO1998001967A2 (de) | 1998-01-15 |
WO1998001967A3 WO1998001967A3 (de) | 1998-04-09 |
Family
ID=3508282
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
PCT/AT1997/000151 WO1998001967A2 (de) | 1996-07-03 | 1997-07-03 | Schaltungsanordnung zur detektion von analogen vermittlungs- und prüfsignalen |
Country Status (3)
Country | Link |
---|---|
AT (1) | AT406534B (de) |
AU (1) | AU3328197A (de) |
WO (1) | WO1998001967A2 (de) |
Families Citing this family (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6104802A (en) | 1997-02-10 | 2000-08-15 | Genesys Telecommunications Laboratories, Inc. | In-band signaling for routing |
Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
GB2056092A (en) * | 1979-08-07 | 1981-03-11 | Standard Telephones Cables Ltd | Line signal monitor |
US4345115A (en) * | 1979-12-13 | 1982-08-17 | Standard Telephones And Cables Limited | Telephone line interface |
US5109409A (en) * | 1989-12-15 | 1992-04-28 | Alcatel Na, Inc. | Apparatus and method to detect telephony signaling states |
US5390231A (en) * | 1993-04-01 | 1995-02-14 | Northern Telecom Limited | Protection and recovery of telephone line interface circuits |
-
1996
- 1996-07-03 AT AT0117796A patent/AT406534B/de not_active IP Right Cessation
-
1997
- 1997-07-03 AU AU33281/97A patent/AU3328197A/en not_active Abandoned
- 1997-07-03 WO PCT/AT1997/000151 patent/WO1998001967A2/de active Application Filing
Patent Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
GB2056092A (en) * | 1979-08-07 | 1981-03-11 | Standard Telephones Cables Ltd | Line signal monitor |
US4345115A (en) * | 1979-12-13 | 1982-08-17 | Standard Telephones And Cables Limited | Telephone line interface |
US5109409A (en) * | 1989-12-15 | 1992-04-28 | Alcatel Na, Inc. | Apparatus and method to detect telephony signaling states |
US5390231A (en) * | 1993-04-01 | 1995-02-14 | Northern Telecom Limited | Protection and recovery of telephone line interface circuits |
Also Published As
Publication number | Publication date |
---|---|
ATA117796A (de) | 1999-10-15 |
WO1998001967A3 (de) | 1998-04-09 |
AU3328197A (en) | 1998-02-02 |
AT406534B (de) | 2000-06-26 |
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