WO1998001806A1 - Processeur d'informations - Google Patents

Processeur d'informations Download PDF

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Publication number
WO1998001806A1
WO1998001806A1 PCT/JP1996/001839 JP9601839W WO9801806A1 WO 1998001806 A1 WO1998001806 A1 WO 1998001806A1 JP 9601839 W JP9601839 W JP 9601839W WO 9801806 A1 WO9801806 A1 WO 9801806A1
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WO
WIPO (PCT)
Prior art keywords
data
memory
error detection
address
access
Prior art date
Application number
PCT/JP1996/001839
Other languages
English (en)
Japanese (ja)
Inventor
Yoshimichi Sato
Shoji Yoshida
Shigeya Tanaka
Takashi Hotta
Yuji Sugaya
Original Assignee
Hitachi, Ltd.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi, Ltd. filed Critical Hitachi, Ltd.
Priority to JP50501698A priority Critical patent/JP3643601B2/ja
Priority to PCT/JP1996/001839 priority patent/WO1998001806A1/fr
Publication of WO1998001806A1 publication Critical patent/WO1998001806A1/fr

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Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
    • G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
    • G06F11/1008—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices
    • G06F11/1044—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices with specific ECC/EDC distribution

Definitions

  • the present invention relates to an information processing apparatus requiring high performance and high reliability, and particularly relates to memory control of an embedded controller system.
  • DRAM with ED0 mode DRAM with ED0 mode
  • SDRAM Synchronous DRAM
  • Synchronous SRAM Synchronous SRAM
  • microcomputers Recently, recent advances in semiconductor technology have made microcomputers widely applicable. In the field of controllers, which are embedded in various devices and perform control functions, small and high performance are realized by embedded microcomputers.
  • a representative embedded microcomputer is Hitachi SH microcomputer (SH-2, SH-3).
  • the SH microcomputer has a normal single access interface function (access only one data per one nosle cycle) and a burst access interface function, so that it is possible to set which interface to use for each user system. It has been In particular, the burst access interface is an interface that can directly connect the SDRAM without an external additional circuit, and is suitable for reducing the size of the device S.
  • the ECC function is, for example, for attaching a 7-bit error correction code to 32-bit data, thereby performing 1-bit error correction and 2-bit error detection.
  • the basic operation when the memory has the ECC function will be described.
  • When writing 32 bits of data to memory it generates 7 bits of ECC error correction code and writes it with the data in a 39-bit width.
  • ECC error correction codes ECC bits
  • ECC bits must be generated only for 32 bits of data. In other words, when writing 32 bits of data, it is sufficient to simply add the ECC bit and write the data. However, the following procedure is required when writing in units of bytes.
  • writing in byte units is called a partial write, and the operation at that time is called a read modify write.
  • the first problem is that it is desired to perform memory access using the burst access interface function to increase the speed, but partial writing (write operation in byte units) cannot be performed.
  • the second problem is that it is possible to use the single access interface function to enable partial writing, but the high-speed burst transfer mode of the memory cannot be used, and high-speed memory access cannot be performed. Is a point.
  • g-leaves “assert sserU” and “negate” are used in various places. This is because the signal has "active-high” and “active- ⁇ ow” signals to prevent confusion when handling them in a mixed manner. Active and low signals are indicated by prefixing their names with " A ":
  • An object of the present invention is to provide an information processing apparatus that can achieve both high reliability by FCC and high-speed memory access.
  • the present invention provides a first data transfer interface for transferring data by a predetermined method, and a second data transfer interface for transferring data by a method different from the predetermined method.
  • CPU having a data transfer interface, first error detection control means corresponding to the first data transfer interface, and second error detection control corresponding to the second data transfer interface Means for controlling the reading and writing of data between the memory and the CPU, and the first error detection control means and the second error detection control means are respectively different from each other.
  • the memory is accessed by the first or second error detection control means.
  • the first data transfer interface is for transferring data by a burst access method
  • the second data transfer interface is for transferring data by a single access method. It is a thing.
  • the first error detection means and the second error detection means both have an ECC control function, and in particular, the second error detection control means is provided for data having a width smaller than n bits. First, data at the ⁇ -bit boundary is read from the memory, write data smaller than n-bit width is embedded in the read data, and an error correction code is added on the read data (execute partial write). .
  • the burst access interface and the single access interface are appropriately selected and high reliability is provided by ECC, a high-speed burst access interface is usually used, and a single access interface is used only when necessary. The average speed of the memory access can be increased by using.
  • FIG. 1 is a block diagram showing a schematic configuration of an embodiment of the present invention.
  • FIG. 2 is a map showing address space allocation.
  • FIG. 3 is a block diagram showing an address decoding method.
  • FIG. 4 is a map showing address space allocation.
  • FIG. 5 is a block diagram showing an address decoding method.
  • FIG. 6 is a block diagram showing the internal configuration of the MC.
  • FIG. 5 is a block diagram showing a simplified internal configuration of the MCU.
  • FIG. 8 is a wiring diagram showing a connection relationship between CPU, MC, and SDRAM.
  • FIG. 9 is a block diagram showing a configuration of a data path inside the MCU.
  • FIG. 10 is a block diagram showing a configuration of a control unit inside the MC controller.
  • FIG. 11 is a block diagram showing a latency setting method.
  • FIG. 12 is a time chart showing a read operation by burst access.
  • FIG. 13 is a timing chart showing a write operation by burst access.
  • FIG. 14 is a timing chart showing a read operation by single access.
  • FIG. 15 is a time chart showing a 32-bit write operation by single access.
  • FIG. 16 is a timing chart showing a partial light operation by Singel access.
  • FIG. 17 is a time chart showing the operation of the error address latch.
  • FIG. 18 is a block diagram showing one embodiment of the present invention.
  • FIG. 19 is a block diagram showing one embodiment of the present invention.
  • FIG. 20 is a block diagram showing one embodiment of the present invention.
  • FIG. 21 is a block diagram showing a system configuration.
  • FIG. 22 is a block diagram showing a connection method with a system bus. BEST MODE FOR CARRYING OUT THE INVENTION
  • FIG. 1 is a block diagram showing an outline of an embodiment of the present invention.
  • CP Central Processing Unit, Central Processing Unii
  • MC Memory Control Unit
  • the CPU 101 has a cache memory 104 therein.
  • a cache memory 104 When executing a data transfer instruction between the internal register of the CP and the memory, or when fetching an instruction, and there is no copy in the cache memory (cache miss).
  • To the external memory 103 Access operation is started (internal I / F112).
  • To access the external memory 103 select the burst access I / F function 106 or the single access I function 107-The selection is determined by the decoding circuit 105.
  • the decoding circuit 105 identifies the address space based on some addresses 113 of the internal I / F 112: burst access : / F function 106 input / output for external memory 1 1 4 and single access I / F function 1 107 External memory human output 1 1
  • MCL'102 is for the purpose of sabotaging ECC and has the features of the present invention. It has an ECC control function 109 for burst access and an ECC control function 110 for single access.
  • the ECC control function for burst access 109 is for continuously transferring 32 bits of data by pipeline operation, and performs error detection and ECC generation for each 32 bits of data.
  • the ECC control function for single access 110 performs reading and writing in 32-bit units and writing in 16-bit and 8-bit units (partial write) with ECC. The selection of these two E C.C control functions must correspond to the inside of CPU 101.
  • the selection unit 1 1 1 which has a function to select the ECC control function for burst access 109 for external memory I / O 1 19 and the ECC control function for single access 110 for external memory I / O 1 2 0 Is selected by the output 1 16 of the decoding circuit 105.
  • the selected one appears outside the MCU 102 (external memory IZF 1 2 1).
  • the A WA IT output 1 1 8 is a cycle extension request signal supports only ECC control function 1 1 0 for single access, to realize a cycle extension that occurs when performing partial Rye Bok.
  • the memory 103 has a high-speed burst transfer function and is composed of DRAM, SDRAM, and the like.
  • the decoding circuit 105 has a function of allocating an area for burst access (partial write not possible) and an area for single access (partial write possible) to the address space.
  • FIG. 2 shows an embodiment of address space allocation.
  • FIG. 3 shows a configuration in which the assignment method shown in FIG. 2 is realized by the decoding circuit 105.
  • the address 113 is m bits indicating a byte address
  • the memory 103 has a capacity of (2 n) bytes.
  • the specific byte address in the area of memory 103 (202 in FIG. 2) is specified by LSB.
  • Area ⁇ is identified by the circuit of decode A302.
  • area B is identified by the circuit of decode B303.
  • the address space is divided into 128 8-megabyte address areas. Normally, the power of allocating the space of the memory 103 to one area In this embodiment, the only memory is allocated from the two areas A and B so that each can be accessed as an 8-Mbyte address area.
  • area A200 is an area for performing burst access (partial write is impossible)
  • area B201 is an area for performing single access (partial write is possible).
  • copy-back cache memory is used, and cache Areas where only burst access transfer occurs in units of 16 bytes (such as in units of 16 bytes) are designated as area A200, and the cache must be turned off and writing in units of 16 bits or 8 bits is necessary.
  • the area to be set is area B201. Use these two areas properly with software.
  • FIG. 8 shows the connection relationship between the SDRAM, the CPU 101, and the MCU 102 when the memory 103 in FIG. 1 is constituted by an SDRAM.
  • SDRAMs of 16 Mbits (1048576 words x 8 bits x 2 links) are used, and 4 (82 22 to 825) have a data width of 32 bits and 8 Mbytes.
  • One (826) has a configuration that allocates 7-bit ECC data.
  • the addition of a 7-bit ECC bit to a 32-bit data is based on a method generally called SECDED (Single bit Error Correction / Double bit Error Detection).
  • SECDED Single bit Error Correction / Double bit Error Detection
  • the SECDED system has a 1-bit error correction function and a 2-bit error detection function.
  • cycle extension can be requested.
  • ADDR (601) The operation of ADDR (601) differs between burst access and single access.
  • Figure 6 shows the internal configuration of the MCU.
  • the inside of the ECC control function for burst access 109 is roughly divided into a data path A 608 and a control unit 609.
  • the inside of the data path A 608 receives the address 601, manipulates it, and outputs it (631).
  • the ECC control function 1 i 0 for single access is roughly composed of a data path B 610 and a control unit B 611.
  • the inside of the data path B610 receives the address 611, manipulates it, and outputs it (632).
  • the “address operation unit 13” 615 and inputs data at the time of reading (626).
  • "Error detection correction section B” 616 which detects and corrects errors by ECC and outputs (630), and inputs data at writing (607) to generate the ECC bit It consists of “ECC generator B” 617 to be output (634).
  • the same data is output to the ECC generator 617 at the same time as the output 630 from the "error detection Z corrector B" 616 (6337).
  • This data output 637 is a data path for merging data once read from the memory with the write data (607) when performing a partial write.
  • the selection section 111 has a selection function corresponding to address, data read, data write, and control signals.
  • Selection function 6 19 selects address outputs 6 3 1 and 6 3 2.
  • the selection function 6 18 selects data 6 29 and G 30 for data reading.
  • the selection function 620 selects data 633 and 634 for writing.
  • Selection function 6 21 selects control signals 635 and 6 36.
  • the external input / output I / F 117 with the CPU 101 has an address 601, data 602, and other control signals 603.
  • the memory interface signal 121 consists of the address 622, data 623, and other control signals 624.
  • buffer output 6 2 5, buffer output 6 2 6, selection section output 6 06, buffer 6 ⁇ 4 are used, and buffer 605, buffer output 607, selection section output 6 are used for writing.
  • the configuration shown in FIG. 6 is a case where the basic concept of the present invention is applied as it is, and this can be simplified to reduce the hardware cost.
  • the “error detection Z correction section B” 6 16 can be the same as the “error detection correction section A” 6 13 and the “P CC generation section B” (; 17 is the “ECC generation section”).
  • the difference from AJ 6 14 can be only the presence or absence of the merge function.Therefore, these can be shared and need not be provided separately.When shared, the output selection section is also omitted. it can.
  • Fig. 6 shows a simplified version of the configuration shown in Fig. 6 by sharing functions.
  • the merge function is used only when performing a partial write according to the instruction of the control unit B.
  • FIG. 9 is a diagram showing the configuration of the data path inside the MCU, and shows the data path 706 in FIG. 7 in accordance with the connection section shown in FIG.
  • Address operation section A 6 1 2 operates the address during burst access It is for.
  • the function required by the address operation unit A612 is to delay the timing of giving the column address to SDRAM by one cycle in order to generate ECC during writing (described later). Therefore, when the column address at the time of writing is given to the SD RAiM, the output 902 of the column address latch 901 is selected (selector 903), and otherwise, ADDR [13: 2]. Is output as it is (631).
  • the output 6 3 1 selector 6 1 becomes effective when the lambda C S_A 8 0 1 of Figure 8 is veers Bok c
  • the address operation section B 6 15 is used to operate the address at the time of single access.
  • the line address (A D D R ) At the time of single access, the line address (A D D R )
  • the output 632 is made effective by the selection unit 619 when CS-13802 in FIG. 8 is asserted.
  • the “error detection Z correction unit AB” 701 includes an error detection and correction function 911 and an error address holding unit 904.
  • Error detection and correction function 911 performs error detection and correction of read data using the SECDED method.
  • the read data is transferred to the CPU 101 through the error detection and correction function 919 during both burst access and single access.
  • the error address holding unit 904 holds the address when an error is detected in the read data so that the data can be read later from the CPUIOI.
  • an error is detected in data, it is only necessary to notify CP 01 by generating an interrupt or setting a flag in a specific register.
  • the internal configuration of the error address holding section 904 will be described. It consists of a row address latch 908, a column address latch 909, and an error address latch 910 that receives the outputs 911 of these two latches as inputs. By reconstructing the address from the output of selection 6 19, it can be used commonly for both burst access and single access.
  • the selector 913 selects and outputs (704) the output 9] 2 of the error address latch 910 only when reading the error address. Otherwise, error detection and correction is performed. Function 9 1 9 Output 7 0 3 Selective output
  • the ECC generation unit A Bj 702 has a merge function 9 15, and the output data 7 0 3 of the “error detection Z correction unit ⁇ B” 7 0 1 and the write data 6 7 Merging is possible.
  • the merge function is used only when reversal writing is performed according to the instruction of the control unit ⁇ .
  • the control unit ⁇ reads out the 32-bit data of the address to be rewritten from the memory.
  • the write data of the partial write (from 607) is embedded in the read data (from 703) and read so as to be output (910): ⁇ —
  • the merge function is It simply outputs (916) all inputs 6 07 as they are.
  • the ECC generator 917 has a function of generating a 7-bit ECC bit for the 32-bit data 916.
  • the temporary latch 918 holds data one cycle at a time in accordance with the delay time at which the ECC generation 917 generates the ECC bit.
  • FIG. 10 is a block diagram showing the configuration of the control unit inside the MC unit.
  • the control unit A609 controls the burst access, and basically outputs the control signal of the CPU 101 at the time of the burst access as it is.
  • the exceptional case is when the column address and write data are output at the time of writing-it is necessary to delay the column address and write data by one cycle in accordance with the delay time for generating the ECC bit. Because there is.
  • Two latches (10 (H, 1002 is for that.
  • the control unit B 6 11 1 controls the single access.
  • CP 01 does not output the direct control signal of SDRAM by 'RAS806 and' CAS807. Therefore, at the time of single access, the control unit B 611 must generate them (RASZCAS generation 1004). In addition, it is necessary to adjust the timing of each type of control (1005) and control the partial light (1006).
  • Selection 6 21 selects the control signal output of the control section A 609 and the control section B 6 11.
  • the control signal output of the control section B 611 is selected only when the assertion of “CS—B 8 () 2” is performed, and the control signal output of the control section ⁇ 609 is selected when the negative state is selected. I did it.
  • the SDRAM (822 to 826) specifies the number of cycles after the column address is given to ADDR622 for data output (812 to 816) during reading (called Cas and atency). Can be set to an internal register ( ⁇ cycle).
  • MCL'102 in order to secure the delay time of the "error detection / correction unit” 701, burst access of a W cycle larger than the IV cycle of the SDRAM IZF function 10 Set to Cas Latency on the 6 side. Then, the delay time of the “error detection / correction unit” 70 1 can be secured (M cycles.
  • M is set to 3 cycles and N is set to 2 cycles, and the delay time (M ⁇ N) of the “error detection / correction unit” 701 is 1 cycle.
  • the operation of the configuration shown in Fig. 8, Fig. 9 and Fig. 10 will be explained using time charts (Figs. 12 to 17).
  • FIG. 12 is a time chart showing a read operation by burst access.
  • FIG. 13 is a timing chart showing a write operation by burst access.
  • FIG. 14 is a timing chart showing a read operation by single access.
  • FIG. 15 is a timing chart showing a 32-bit write operation by single access.
  • FIG. 16 is a timing chart showing a partial write operation by single access.
  • FIG. 1 is a time chart showing an operation example of the error address holding unit 904 shown in FIG.
  • FIG. 12 is a time chart showing a memory read operation by burst access.
  • the CPU 101 reads data four times for each burst transfer.
  • the CP 101 used in the present embodiment adopts a method in which the CPU 101 updates the address by specifying the column address four times.
  • the values of the row address and the column address are output so that the SDRAiM can be directly connected to the lower part ([13: 2]) of the address (60i).
  • r Indicates that the row address appears in one cycle and r3 to r6 appear in the column address in order.
  • the MCn 02 that receives the error is output to SDRAM without performing any particular operation (622, r, 1 to r6). This can be realized by selecting and using the address operation unit A 612 inside the MCU 102. .
  • the read data from SDR ⁇ appears in r ⁇ ) to r8 cycles (8 12 to 8 16). These correspond to the column addresses issued in r3 to r6, and the cycle delay follows the value "2" specified by the Cas Latency.
  • the MCU 102 receives the read data, detects an error in the internal “error detection and correction function” 919, and corrects a 1-bit error when detected (over r5 to r9 cycles).
  • control signal The following is a description regarding the control signal.
  • MCU02 recognizes that it is a burst access cycle by asserting 'CSA (801)'. 'If CS — A (800) is asserted, then' CS — B (802) is not asserted.
  • the control unit A G09 is selected and used inside the MCU 102, and a control signal is output.
  • CPUIOI is A RAS806 the 'CAS807 time even reading produced outputs to as SDR AM (8 1 8, 8 1 9).
  • D QM X x / 'W En (808 to 811) are all at the oral level.
  • FIG. 13 is a timing chart showing a write operation to a memory by burst access.
  • CP'101 writes data four times per burst transfer.
  • the address is updated by specifying the column address every four times.
  • the row address and column address values are output so that SDRAM can be directly connected to the lower part of the address (601).
  • w indicates that the row address appears in one cycle
  • w3 to w6 indicate the column address appears sequentially.
  • the MCU 102 that receives this outputs the column address to the SDR @ M with one cycle delay in accordance with the delay of data transfer by one cycle for ECC generation (622, w4 to w7).
  • Data 602 written to the SDRAM appears in w3 to w6 cycles. These also correspond to the column addresses issued in w3 to w6.
  • the MCU 102 receives the write data, and generates an ECC bit in the internal “ECC generation j 917”.
  • the data and the ECC bit are output from the MCU 102 to the SDRAM in the period of w4 to w7 cycles with a delay of one cycle (812 to 816)
  • control signal The following is a description regarding the control signal.
  • the MCL'102 recognizes that the cycle of the burst access has been reached by asserting ⁇ CS-A (801). If A CS— A (800) is asserted, A CS— ⁇ 3 (802) is not asserted.
  • the control unit A609 is selected and used inside the MCU102, and a control signal is output.
  • the RAS806 created by the CPU 101 can be output to the SDRAM as it is as in the case of reading ('ras818).
  • the mouth level is output with a one-cycle delay ('cas819) according to the data (812 to 816).
  • DQMxxWen (808 to 811) are all at low level.
  • FIG. 14 is a timing chart showing a memory read operation by single access.
  • the address (601) from the CPUIOI simply outputs the value directly to bits [22 : 2].
  • the row address is output to SDRAM sequentially in the R2 cycle, and the column address is output to the SDRAM in the R4 cycle (622). This is realized by selecting the address operation unit B 6 15 inside the MCU 102.
  • the read data from the SDRAM appears in the R6 cycle (812 to 816). These correspond to the column addresses issued in the R4 cycle, and the cycle delay follows the value specified by the Cas Latency.
  • the MCU 102 receives the read data, detects an error in the internal “error detection and correction function” 919, and corrects the error if detected (R6 to R7 cycles).
  • the data is finally output from the MCU 102 to the CPU 101 (602) in the R7 cycle.
  • MCl; 102 recognizes that it is a single access cycle by asserting 'CS—B (802).
  • the control unit B611 is selected and used inside the MCU102, and a control signal is output.
  • AIT1 I8 is sampled by CPU 10i from the rising edge of the clock at the beginning of R3 cycle.
  • the data force 02 is controlled so as to make an assertion in R2 to R6 cycles.
  • FIG. 15 is a time chart showing the operation of writing 32 bits of data to the memory by single access.
  • the row address is sequentially output to SDRAM in the W2 cycle
  • the column address is sequentially output to the SDRAM in the W4 cycle (622). This can be realized by selecting and using the address operation section B 6 15 inside the MCU 102.
  • the write data 602 from the CPU 101 is output in the same manner as the address 601.
  • the MCU 102 receives the write data 602 and generates an ECC bit in the internal “ECC generation” 917.
  • control signal The following is a description regarding the control signal.
  • the MCU 102 recognizes that the cycle is a single access cycle by asserting 'CS_B (802).
  • the control unit B61i is selected and used inside the MCU 102 to output a control signal.
  • To the SDRAM 'CS (8 2 7) is' veers to me with the cycle of the W 2 ⁇ W 4 according to the ras818 and ⁇ cas819.
  • 'we 817' to the SDRAM In response to the output of CPL'lOl RD WR 805 becoming low level, indicating a write operation, 'we 817' to the SDRAM also outputs a mouth level in W4 cycles in accordance with 'cas .
  • DQM X x / 'WE n 808 to 81 1) is all at the mouth level.
  • the MCU 102 controls to make an assertion in W2 to W3 cycles.
  • FIG. 16 is a time chart showing a partial write operation to a memory by single access.
  • the address (601) from the CPU 101 simply outputs the value directly to bits [22: 2].
  • the row address is output to SDRAM in two PW cycles
  • the column address is output to SDRAM in four PW cycles.
  • the column address is output to the SD RAM in the PW 8 cycle for the procedure c (622). The above is realized by selecting the address operation unit B 6 15 inside the MC 102.
  • the read data from the SDRAM appears in 6 cycles of PW (812 to 816). These correspond to the column addresses issued in four cycles of PW, and the cycle delay follows the value specified by the Cas Latency.
  • the MCU 102 receives the read data, detects an error in the internal “error detection and correction function” 919, and corrects the error if detected (PW6 to PW7 cycles) (step a)).
  • the CPU 101 outputs the write data 602 in the same manner as the address 601.
  • the data that has passed through the "error detection and correction function” 911 and the write data 602 from the CPU 101 are merged (step 9) (step b)).
  • the ECC bit is generated in the “ECC generation” 911 of the merged data, and finally the data is output from the MCU 102 to the SDRAM (812 to 816) in eight PW cycles.
  • the byte position to be merged is determined by DQMxx / ⁇ ', ⁇ (808 to 811).
  • control signal The following is a description regarding the control signal.
  • the MCU 102 recognizes that the cycle is a single access cycle by asserting ⁇ CS—B (802).
  • the control unit ⁇ 6 1 1 is selected and used inside the MCU 102 and a control signal is output.
  • 'we 8 17 to SDRA ⁇ 1 also outputs a low level in PW 8 cycles in accordance with' cas.
  • the CPU101 does not output 'RAS806' and 'CAS807', so 'ras818' and ':: 819 are generated by the control unit B611 inside the MCU102 (PW2, PW4, PW8 cycles)-D during partial light operation QM xx / WE n (808 to 811) indicates the write byte position, and the control section B 611 controls the partial write if at least one of them is at a high level.
  • No. 118 is sampled by the CPU IOi from the start-up of the first three cycles of PW.
  • the MCU 102 controls so as to make an assertion on PW2 to PW7 cycles.
  • Fig.17 is shown in Fig.9 5 is a time chart showing an operation example of an error address holding unit 904. Shows the case where an error was detected in the memory read operation by single access.
  • the row address is sequentially output to the SDRAM in the R2 cycle
  • the column address is sequentially output in the R4 cycle.
  • Error detection is performed in the “Error detection and correction function” 9 19 over the R 6 to R 7 cycles. If an error is detected, control is performed so that the values of the above two latches (908 and 909) are taken into the error address latch (Err. Addr—Latch 910) (R8 cycle).
  • FIG. 21 is a block diagram when the present invention is configured as a system.
  • Module 2 1 () 6 consists of:
  • the CPU 101, MCU 102, and memory (SDRAM) 103 have been described above. Furthermore, I / ⁇ IF (2 1 0 1) for exchanging information and controlling equipment by connecting 2 1 7 to sensor 2 11 5 through the system bus 2 1 0 0 ) And SCS 1 1 F '(2 1 ⁇ ⁇ 2) for exchanging information by connecting with the hard disk device S 2 11 1 1 and connecting to the oral network 2 1 1 2 2 Then, the LANIF (2103) for exchanging information with other core modules, the PRM (210, Programablo Read Only Memory) with a boot program, and the -It is composed of serial JF (2105) for serial connection 2111 to interface with user.
  • serial JF 2105
  • FIG. 22 shows a method of connecting the MCU 102 to the system bus 210 by the system configuration shown in FIG. 2i.
  • a device on the system bus accesses memory 103 via the MCU 102.
  • a selector 222 is newly added. At the time of access (a), control is performed so that the output 1 i ⁇ of the decoding circuit 105 is selected.
  • the external input / output I / F 1 17 of the CPU iOl Also used to access devices on the system bus.
  • the external input / output IZF 117 is connected to the slave input / output unit 221 3 of the bus interface 220, and devices on the system bus can be accessed through this route.
  • Access from the CPU 101 uses the single access I function 107.
  • a WAIT2217 from the slave input / output unit 2 21 3 is transmitted to the single access function] 07 via the selector 2 15 and responds to the difference in data transfer speed for each device on the system bus.
  • Access from the device on the system bus to the memory 103 is performed through the master input / output unit 222 of the bus interface unit 210.
  • the access from the master input / output unit 222 to the memory 103 is the same as when the access from the CPU 101 to the memory 103 occurs.
  • the access to the memory 103 is performed by the burst access 1 / F function 2201 or Single access I ZF function 2202 is selected.
  • the decision of the selection is made by the decoding circuit 222.
  • the decoding circuit 222 identifies the address space based on a part of the address 222 of the I / F2204.
  • the selection unit 2203 with the function to select the burst access I / F function 2201 input / output 2207 and the single access I / F function 2202 human output 2202 is a decoding circuit 2 Select one of them with the output of 2 0 2 2 0 6.
  • the selected input / output is connected to the input / output IZF117 of CPU101. Cycle extension request signal
  • ⁇ WAIT2216 supports only single access IZF function 107. In this way, devices on the system bus access memory 103. When accessing, it is possible to select between burst access and single access as needed.
  • Fig. 4 shows another example of address space allocation.
  • FIG. 5 shows a configuration in which the assignment method shown in FIG. 4 is realized by the decoding circuit 105.
  • the address 113 is m bits indicating a byte address, and the memory 103 has a capacity of (2 n) bytes.
  • the specific byte address of the memory 103 area (202 in FIG. 4) is specified by bits 3 from b0 to b (n-1) of the LSB (least significant bit). It is 0 1. It is bit 300 from bn to b (m-1) that specifies the combined area of area A400 and area B401. Identify “area A or area B” in the circuit of decode A or B (502).
  • the circuit of decode (A) 501 identifies the area A in the area of memory 103 (202 in FIG. 4), and the b (n-1) bits of address 113 are identified. Input the lower-order bit (only the required number of bits) 500 from the input.
  • the output of the logical product (AND, 507) of the output 503 of the decode (A) 50] and the output 504 of the decode A or B (502) indicates the area A.
  • Logical product of the output 506 of the decoded (A) 501 output 503 inverted (N0T, 505) and the output 504 of the decode A or B (502)
  • the output of (AND, 507) points to area B.
  • the memory space to be used can be suppressed within the actual memory area 202.
  • FIG. 1S is a configuration block diagram showing an outline of another embodiment of the tree invention.
  • the difference from the configuration shown in Fig. 1 is the method of selecting burst access and single access.
  • the selection is determined by the program means, and the register 1800 is set to which one to select.
  • the output 180 0 of the register 180 0 gives an instruction to the selector 1 108 and the selector 1 i 1.
  • the memory mapping does not need to be identified in the address space.
  • register 1800 is set to select fast burst access in normal operation. If it is determined that a partial write is required, set the register 1800 to select single access and then execute the partial write. After that, set to register 1800 to select burst access, and then return to normal operation.
  • FIG. 19 is an improved example of the configuration shown in FIG.
  • a register 190 which is equivalent to the register 180, is provided inside the MCU 102.
  • the selection instruction to the selection unit 1U of the MCU 102 is made by the output 1901 of the register $ 900. According to the second configuration Then, there is an advantage that the CPU 101 does not need to output the output 1801 of the register 1801 to the outside.
  • FIG. 0 is a configuration block diagram showing an outline of another embodiment of the present invention.
  • CPU has TLB (Translation Lookaside Buffer, 2000) for performing virtual memory ( e )
  • TLB Translation Lookaside Buffer, 2000
  • This TLB converts logical addresses to physical addresses in units of 4 Kbyte pages
  • An address conversion table is included in the entry, and an “I / F selection bit” is newly provided for each address conversion table of this TLB, and the output value 2 0 1
  • the instruction is given to 08 and the selection unit 1 1 1.
  • the “I / F select bit” may be set so as to select single access.

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Quality & Reliability (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Techniques For Improving Reliability Of Storages (AREA)

Abstract

Dans un processeur d'informations pourvu d'un ordinateur central, d'une mémoire et d'une section de commande de mémoire, une interface à accès continu à travers laquelle des données peuvent être transférées extrêmement rapidement et une interface à accès unique à travers laquelle une écriture partielle peut être effectuée sont présentes dans l'ordinateur central et une section de commande de code correcteur d'erreur (ECC) pour l'accès continu et une autre section de commande de ECC pour l'accès unique sont présentes dans la section de commande de mémoire. Il est, de ce fait, possible de sélectionner à la fois l'accès continu et l'accès unique, d'améliorer la fiabilité du processeur d'informations par le code correcteur d'erreur (ECC) et d'accéder à la mémoire extrêmement rapidement.
PCT/JP1996/001839 1996-07-03 1996-07-03 Processeur d'informations WO1998001806A1 (fr)

Priority Applications (2)

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JP50501698A JP3643601B2 (ja) 1996-07-03 1996-07-03 情報処理装置
PCT/JP1996/001839 WO1998001806A1 (fr) 1996-07-03 1996-07-03 Processeur d'informations

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PCT/JP1996/001839 WO1998001806A1 (fr) 1996-07-03 1996-07-03 Processeur d'informations

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US09202561 A-371-Of-International 1998-12-17
US09/925,606 Continuation US20020029365A1 (en) 1998-12-17 2001-08-10 Information processing apparatus

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Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7428686B2 (en) 2002-12-06 2008-09-23 Fanuc Ltd Error detection/correction system, and controller using this system
JP2012252558A (ja) * 2011-06-03 2012-12-20 Sony Corp 不揮発性メモリ、メモリコントローラ、不揮発性メモリのアクセス方法、およびプログラム
WO2016017287A1 (fr) * 2014-07-28 2016-02-04 ソニー株式会社 Contrôleur mémoire, système de mémoire et système de traitement d'informations
JP2016134167A (ja) * 2015-01-21 2016-07-25 株式会社東芝 メモリシステムおよび処理装置
US9465691B2 (en) 2012-06-28 2016-10-11 Mitsubishi Electric Corporation Read request processing apparatus

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01246651A (ja) * 1988-03-29 1989-10-02 Toshiba Corp Ｅｃｃ機構付メモリモジュールにおけるデータ書換え装置
JPH04253236A (ja) * 1991-01-29 1992-09-09 Fujitsu Ltd アクセス制御方式
JPH07248976A (ja) * 1994-03-10 1995-09-26 Nec Corp 記憶制御装置
JPH07281948A (ja) * 1994-04-06 1995-10-27 Mitsubishi Electric Corp メモリ制御装置

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01246651A (ja) * 1988-03-29 1989-10-02 Toshiba Corp Ｅｃｃ機構付メモリモジュールにおけるデータ書換え装置
JPH04253236A (ja) * 1991-01-29 1992-09-09 Fujitsu Ltd アクセス制御方式
JPH07248976A (ja) * 1994-03-10 1995-09-26 Nec Corp 記憶制御装置
JPH07281948A (ja) * 1994-04-06 1995-10-27 Mitsubishi Electric Corp メモリ制御装置

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7428686B2 (en) 2002-12-06 2008-09-23 Fanuc Ltd Error detection/correction system, and controller using this system
JP2012252558A (ja) * 2011-06-03 2012-12-20 Sony Corp 不揮発性メモリ、メモリコントローラ、不揮発性メモリのアクセス方法、およびプログラム
US9465691B2 (en) 2012-06-28 2016-10-11 Mitsubishi Electric Corporation Read request processing apparatus
WO2016017287A1 (fr) * 2014-07-28 2016-02-04 ソニー株式会社 Contrôleur mémoire, système de mémoire et système de traitement d'informations
JP2016134167A (ja) * 2015-01-21 2016-07-25 株式会社東芝 メモリシステムおよび処理装置

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