WO1997020350A2 - Element a semiconducteur avec contact schottky et son procede de fabrication - Google Patents

Element a semiconducteur avec contact schottky et son procede de fabrication Download PDF

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Publication number
WO1997020350A2
WO1997020350A2 PCT/DE1996/002285 DE9602285W WO9720350A2 WO 1997020350 A2 WO1997020350 A2 WO 1997020350A2 DE 9602285 W DE9602285 W DE 9602285W WO 9720350 A2 WO9720350 A2 WO 9720350A2
Authority
WO
WIPO (PCT)
Prior art keywords
layer
guard ring
silicon
metal silicide
passivation
Prior art date
Application number
PCT/DE1996/002285
Other languages
German (de)
English (en)
Other versions
WO1997020350A3 (fr
Inventor
Hubert Werthmann
Original Assignee
Siemens Aktiengesellschaft
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Siemens Aktiengesellschaft filed Critical Siemens Aktiengesellschaft
Publication of WO1997020350A2 publication Critical patent/WO1997020350A2/fr
Publication of WO1997020350A3 publication Critical patent/WO1997020350A3/fr

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66083—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by variation of the electric current supplied or the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. two-terminal devices
    • H01L29/6609—Diodes
    • H01L29/66143—Schottky diodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/47—Schottky barrier electrodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
    • H01L29/861—Diodes
    • H01L29/872—Schottky diodes

Definitions

  • the invention relates to a semiconductor component with at least one Schottky contact, in which a guard ring is formed in a silicon layer, in which a first passivation layer is arranged over the silicon layer, the first passivation layer lying outside the guard ring and covers an outer edge region of the guard ring and in which a metal silicide layer is arranged in a contact zone of the silicon layer within the guard ring, a first part thickness of which is embedded in the silicon layer and a second part thickness projects beyond the silicon layer and extends into the guard ring.
  • Such a semiconductor component is known for example from EP 111 364-A1.
  • a Schottky contact is described therein, in which a metal silicide layer is arranged in a window of a passivation layer, which layer is partly embedded in a silicon layer and partly projects beyond the surface of the silicon layer.
  • the metal silicide layer is enclosed by a guard ring in the silicon layer.
  • the Schottky contact described in EP 111 364-A1 has the disadvantage that, due to an underdiffusion of the passivation layer during the production of the metal silicide layer, whereby the metal silicide layer grows under the passivation layer, the boundary between the metal silicide layer and the silicon layer (ie guard ring) and passivation layer runs extremely close to the outer edge of the guard ring. As a result, the risk of a short In the end, an early breakthrough or channel formation at the Schottky contact is very large.
  • the object of the present invention is to develop a semiconductor component of the type mentioned at the outset which has an improved Schottky contact.
  • a second passivation layer which covers a further partial region of the guard ring lying within the outer edge region and has a contact window, the edge of which runs on the guard ring.
  • the second passivation layer thus shifts a boundary between the metal silicide layer, silicon layer and surface passivation in the direction of the guard ring center.
  • the first partial thickness of the metal silicide layer is greater than the second partial thickness.
  • the first passivation layer consists essentially of silicon dioxide and the second passivation layer essentially consists of silicon nitride.
  • the first step is a first passivation layer is applied to a silicon layer produced on a substrate.
  • a guard ring in the silicon layer at least one window is subsequently formed in the first passivation layer, which essentially has the shape of the surface of the guar ring.
  • the guard ring is then generated through this window.
  • a second passivation layer is applied at least to the free surface of the silicon layer and thus also to the free surface of the guard ring.
  • the free surface of the first passivation layer can also be partially or completely covered with the second passivation layer.
  • At least one contact window is subsequently produced in the second passivation layer, in which a metal layer is then applied to the silicon layer.
  • a tempering step follows, in which a metal silicide layer is produced in the contact window. In this siliconization, part of the silicon layer and at least a large part of the metal layer is converted to metal silicide. Subsequently, a metal silicide which has not been converted into metal silicide is optionally converted
  • the above-mentioned method has the particular advantage that impurities on the contact zone, such as dust particles, are embedded in the metal silicide layer during siliconization, thereby becoming electrically ineffective and consequently not being able to cause malfunctions. Contamination particles at the interface between metal and semiconductor can namely lead to an increase in the reverse current.
  • FIGS. 1 and 2 show it: 1 shows a schematic representation of a cross section through the exemplary embodiment and FIG. 2 shows a schematic representation of a process sequence for producing a plurality of semiconductor components in accordance with the exemplary embodiment
  • a silicon epitaxial layer 1 for example n-doped with phosphorus, is applied to a substrate 10.
  • the substrate 10 consists, for example, of arsenic or antimony n-doped silicon and is provided with a contact metallization 14 on its side opposite the silicon epitaxial layer 1.
  • the contact metallization 14 consists, for example, of an AuAs-an AuSb alloy and another metallic material known to the person skilled in the art to be suitable.
  • a guard ring 6 is formed in the silicon epitaxial layer 1, which is of the opposite conductivity type as the silicon epitaxial layer 1.
  • the guard ring 6 can be produced, for example, by means of boron doping.
  • a first passivation layer 15, for example consisting of silicon dioxide, is applied to the silicon epitaxial layer 1 and covers a partial area of the silicon epitaxial layer 1 lying outside the guard ring 6, including an outer edge area of the guard ring 6.
  • the second passivation layer 16 has a contact window 13 which is smaller than a window defined by the first passivation layer 15 and the edge of which extends on the guar ring 6.
  • the edge of the contact window 13 is closer to the inner edge of the guar dringe ⁇ 6 as on its outer edge.
  • a metal silicide layer 2 is arranged in the contact window 13, a first partial thickness of which is embedded in the silicon epitaxial layer 1 and a second partial thickness projects into the contact window 13 and is delimited on the side face 4 by the second passivation layer 16.
  • the metal silicide layer 2 consequently extends into the guard ring 6. It consists, for example, of molybdenum silicide, platinum silicide or palladium silicide and the first partial thickness is, for example, two thirds of the total thickness of the metal silicide layer 2.
  • the contact window 13 is dimensioned such that the boundary between metal silicide layer 2, silicon epitaxial layer 1 (ie guard ring 6) and surface passivation (here consisting of first and second passivation layer 15, 16) is as far as possible in the middle between the outer and inner edge of the guard ring 6 lies.
  • a metal layer 17 is applied as the last layer on the metal silicide layer 2 and on an edge region of the second passivation layer 16 around the contact window 13. This is composed, for example, of a Ti layer (thickness, for example 240 nm), a Pt layer (thickness, for example 170 nm) and an Au layer (thickness, for example 600 nm).
  • the substrate 10 and the silicon epitaxial layer 1 are n-type.
  • these two components are p-type.
  • the doping of the other components must then be adjusted accordingly. All dopants known to those skilled in the art to be suitable can be used for doping. It is also conceivable that instead of two passivation layers 15, 16 even more different types of passivation layers are applied.
  • a silicon epitaxial layer 1 is first applied to a substrate wafer 18. Subsequently, a silicon dioxide layer 15 is formed on the silicon epitaxial layer 1 as the first passivation layer, for example by vapor deposition or oxidation. A plurality of windows 19 are produced in this silicon dioxide layer 15 in accordance with a predetermined grid, for example by means of photolithography and subsequent etching.
  • a plurality of guard rings 6 and a plurality of scoring tracks 12 are formed, for example, by implanting and diffusing a dopant in the silicon epitaxial layer 1.
  • a dopant in the silicon epitaxial layer 1.
  • boron can be used for this purpose.
  • a silicon nitride layer 16 is now applied to the silicon epitaxial layer 15 and to the free surface 11 of the silicon epitaxial layer 1 (guard rings 6 + scoring lines 12), for example by means of vapor deposition, as a second passivation layer.
  • This is then provided with a plurality of contact windows 13, for example by means of photolithography and etching, in such a way that those located on the contact zones 7 of the silicon epitaxial layer 1 to be contacted later Subregions 20 of the silicon dioxide layer 15 are exposed.
  • the scoring tracks 12 are also exposed again in this step.
  • the subregions 20 of the silicon dioxide layer 15 are subsequently removed, for example by means of etching.
  • Etching solutions for etching the passivation layers are known in semiconductor technology and are therefore not explained in more detail here.
  • a metal layer 8 is then applied in each case to the contact zones 7 and to the edge region of the silicon nitride layer 16 towards the contact windows 13 such that an overlap 9 is produced between the metal layer 8 and the silicon nitride layer 16.
  • the metal layers 8 have a thickness of 100 nm, for example, consist, for example, of molybdenum or another suitable metal and are produced, for example, by means of vapor deposition or sputtering.
  • the next step in the process is an annealing process which has the effect that a metal silicide layer 2 is produced in the region of the contact zones 7.
  • a metal layer 8 made of molybdenum is used, a tempering phase is suitable, for example, in which the pane is kept in a hydrogen atmosphere at approximately 510 ° C. for two hours. This tempering process is used to produce metal silicide layers 2 in the area of the contact window 13.
  • a first partial thickness of the metal silicide layers 2 is embedded in the silicon epitaxial layer 1, a second partial thickness projects into the contact window 13 and is on the side surfaces 4 enclosed by the silicon nitride layer 16.
  • the partial regions of the metal layers 8 which have not been converted to metal silicide, in particular at the overlap 9, are removed, for example by means of selective etching.
  • an etching solution e.g. B. a mixture of phosphoric acid and nitric acid can be used.
  • a metal layer 17 is applied to the metal silicide layers 2 and to partial regions of the silicon nitride layers 16.
  • this metal layer 17 consists, for example, of a layer sequence of Ti, Pt and Au.
  • the wafer is finally separated into individual semiconductor components 3, for example by means of sawing.
  • the contact metallization 14 can alternatively also be applied before the process steps described above.

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Ceramic Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Electrodes Of Semiconductors (AREA)

Abstract

L'invention concerne un élément à semiconducteur présentant un contact Schottky sur une couche de silicium (1), ledit contact comportant une couche de siliciure métallique (2) formée dans une fenêtre de contact (13) d'une passivation de surface (5). Cette passivation de surface (5) est constituée d'une première couche de passivation (15) et d'une seconde couche de passivation (16) qui définit la fenêtre de contact (13). La seconde couche de passivation (16) permet de déplacer la limite entre la couche de siliciure métallique (2), l'anneau de garde (6) et la passivation de surface en direction du milieu de l'anneau de garde. Ceci permet d'accroître la résistance aux courts-circuits, de réduire le risque d'un claquage prématuré ou d'une formation de canal.
PCT/DE1996/002285 1995-11-28 1996-11-28 Element a semiconducteur avec contact schottky et son procede de fabrication WO1997020350A2 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
DE19544326.8 1995-11-28
DE1995144326 DE19544326A1 (de) 1995-11-28 1995-11-28 Halbleiterbauelement mit Schottkykontakt

Publications (2)

Publication Number Publication Date
WO1997020350A2 true WO1997020350A2 (fr) 1997-06-05
WO1997020350A3 WO1997020350A3 (fr) 1997-07-03

Family

ID=7778606

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/DE1996/002285 WO1997020350A2 (fr) 1995-11-28 1996-11-28 Element a semiconducteur avec contact schottky et son procede de fabrication

Country Status (2)

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DE (1) DE19544326A1 (fr)
WO (1) WO1997020350A2 (fr)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9472687B2 (en) 2011-03-31 2016-10-18 Semikron Elektronik Gmbh & Co., Kg Schottky diode and method for making it

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE19653457C2 (de) * 1996-12-20 1999-03-25 Gen Semiconductor Ireland Macr Schottky-Diode sowie Verfahren zu ihrer Herstellung
DE10015884A1 (de) * 2000-03-30 2001-10-11 Philips Corp Intellectual Pty Schottky-Diode
DE102011122091A1 (de) * 2011-12-22 2013-06-27 Diotec Semiconductor Ag Schottky-Halbleiterprozess
CN113871467B (zh) * 2021-09-28 2023-08-04 吉林华微电子股份有限公司 一种肖特基二极管及其制造方法

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3753807A (en) * 1972-02-24 1973-08-21 Bell Canada Northern Electric Manufacture of bipolar semiconductor devices
EP0182088A1 (fr) * 1984-10-26 1986-05-28 Siemens Aktiengesellschaft Contact Schottky à la surface d'un semi-conducteur et son procédé de réalisatioN

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0111364B1 (fr) * 1982-12-08 1989-03-08 Koninklijke Philips Electronics N.V. Dispositif semi-conducteur comportant au moins un redresseur de type Schottky à hauteur de barrière contrôlable

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3753807A (en) * 1972-02-24 1973-08-21 Bell Canada Northern Electric Manufacture of bipolar semiconductor devices
EP0182088A1 (fr) * 1984-10-26 1986-05-28 Siemens Aktiengesellschaft Contact Schottky à la surface d'un semi-conducteur et son procédé de réalisatioN

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9472687B2 (en) 2011-03-31 2016-10-18 Semikron Elektronik Gmbh & Co., Kg Schottky diode and method for making it

Also Published As

Publication number Publication date
WO1997020350A3 (fr) 1997-07-03
DE19544326A1 (de) 1997-06-05

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