WO1997009717A1 - Circuit de commande a vitesse lineaire constante pour appareil a disque optique - Google Patents

Circuit de commande a vitesse lineaire constante pour appareil a disque optique Download PDF

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Publication number
WO1997009717A1
WO1997009717A1 PCT/JP1995/001787 JP9501787W WO9709717A1 WO 1997009717 A1 WO1997009717 A1 WO 1997009717A1 JP 9501787 W JP9501787 W JP 9501787W WO 9709717 A1 WO9709717 A1 WO 9709717A1
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WO
WIPO (PCT)
Prior art keywords
signal
clv control
optical disk
clv
wobble
Prior art date
Application number
PCT/JP1995/001787
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English (en)
Japanese (ja)
Inventor
Akihiro Arisaka
Original Assignee
Kabushiki Kaisha Kenwood
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority to JP7062163A priority Critical patent/JPH07287931A/ja
Priority claimed from JP7062163A external-priority patent/JPH07287931A/ja
Application filed by Kabushiki Kaisha Kenwood filed Critical Kabushiki Kaisha Kenwood
Priority to PCT/JP1995/001787 priority patent/WO1997009717A1/fr
Publication of WO1997009717A1 publication Critical patent/WO1997009717A1/fr

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Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11B—INFORMATION STORAGE BASED ON RELATIVE MOVEMENT BETWEEN RECORD CARRIER AND TRANSDUCER
    • G11B19/00—Driving, starting, stopping record carriers not specifically of filamentary or web form, or of supports therefor; Control thereof; Control of operating function ; Driving both disc and head
    • G11B19/20—Driving; Starting; Stopping; Control thereof
    • G11B19/24—Arrangements for providing constant relative speed between record carrier and head
    • G11B19/247—Arrangements for providing constant relative speed between record carrier and head using electrical means

Definitions

  • the present invention relates to a CLV control circuit for an optical disk device, and more particularly to a CLV control circuit for an optical disk device that ensures stable operation even when a wobble signal is lost due to a scratch, dust, or the like.
  • the CLV control for maintaining and controlling an optical disc (hereinafter, referred to as a disc) at a constant linear velocity (CLV) is performed based on a wobble signal obtained by detecting pregroove information engraved on the disc by an optical big-up.
  • FIG. 9 is a block diagram showing a configuration example of a CLV control circuit of a conventional optical disc device.
  • the rotation of the disk 1 is controlled by the motor 2 and the information stored in the disk 1 detected by the optical pickup 3 is converted into a wobble signal by the wobble detector 4 based on the pre-group engraved on the disk.
  • a ' is detected.
  • the CLV controller 5 generates a CLV control signal based on the detected wobble signal A ′ and the reference clock signal from the reference clock generator 6 and controls the motor 2. Disclosure of the invention
  • the above-described CLV control circuit is capable of controlling the CLV even when there is a long-time loss of the wobble signal due to abnormal recording or the like, or even when there is a short-time loss of the wobble signal due to small scratches or dust.
  • the control was disturbed. That is, the conventional optical disk CLV control circuit performs CLV control based on the optical signal A 'detected from the pre-group of the optical disk.
  • the conventional optical disk CLV control circuit performs CLV control based on the optical signal A 'detected from the pre-group of the optical disk.
  • a scratch or dust is present on the disc, as shown in FIG. 17, a pebble signal cannot be detected, and a missing portion of the period t 'occurs.
  • the output signal 0 'of the ⁇ control unit 5 sticks to the acceleration side with a delay of time t ⁇ .
  • the output signal D' is positive at the time of acceleration error centering on 0V.
  • the voltage signal is output as a negative voltage signal at the time of the decompression error, and the CLV control unit 5 divides the frequency of the cobble signal A 'and compares it with the reference clock signal.
  • the disk does not have a constant linear velocity during the missing period, and the linear velocity further increases. After that, even if the wobble signal A 'is detected after passing through the missing part, the signal 1)' sticks to the deceleration side and tries to return to the constant linear velocity state because the disk is rotating at high speed.
  • the servo operation becomes stable only after a lapse of a time t longer than the missing period t 'of the wobble signal A' due to scratches or dust, and it is difficult to quickly perform a stable operation.
  • the time t 'is t' 1 x 10-3 / 1.4, that is, about 0.7 ms, and the servo is disturbed.
  • the time t which depends on the servo system and the radial position of the track, can reach about 2 ms.
  • such small scratches and dust may be attached to a large number of discs, and in this case, a continuous loss of the wobble signal occurs. At this time, for example, if the wobble signal is lost again during the time t described above, the servo has been disturbed for a longer time.
  • an object of the present invention is to provide a CLV control circuit of an optical disk device that suppresses noise and enables quick and stable disk rotation even if a wobble signal is lost due to scratches or dust. It is in.
  • a CLV control circuit of an optical disk device is a CLV control circuit of an optical disk device for controlling a constant linear velocity (CLV) of an optical disk.
  • a wobble detection unit for detecting a wobble signal obtained from the optical disc
  • a PLL circuit section for performing PLL processing on the wobble signal
  • a lock detector that determines that the lock state is established when the frequency of the wobble signal is within a predetermined range
  • a selector unit for selecting and outputting a wobble signal when the whacking detection unit determines that the whipping state is not set, and selectively outputting an output signal from the PLL circuit unit when determining that the whipping state is determined;
  • a CLV control circuit of an optical disc device includes: In the CLV control circuit of the optical disk device for controlling the constant linear velocity (CLV) of the optical disk,
  • a wobble detection unit that detects a wobble signal obtained from an optical disc; a PLL circuit unit that performs a PLL process on the wobble signal;
  • a lock detection unit that determines that the wobble signal is not in the hooking state when there is a predetermined number of consecutive missing of the wobble signal
  • a selector unit for selecting and outputting a wobble signal when the mouthpiece detection unit determines that the mouthpiece is not in a hooking state and an output signal from the PLL circuit unit when determining that the mouthpiece is in the mouthpiece state;
  • a wobbled detector for detecting a wobbled signal obtained from an optical disc; a PLL circuit for PLL-processing the wobbled signal;
  • An mouth detection unit that determines that the locked state is not established when the wobble signal is missing for a predetermined time
  • a selector unit for selecting and outputting a wobble signal when the whacking detection unit determines that the whipping state is not set, and selectively outputting an output signal from the PLL circuit unit when determining that the whipping state is determined;
  • a CLV control circuit of the optical disc device includes:
  • a wobble detection unit that detects a wobble signal obtained from an optical disc; a PLL circuit unit that performs a PLL process on the wobble signal;
  • the wobble signal and the signal from the PLL circuit are selected and output to the CLV control unit. Selector part to be
  • the selector unit is configured to select a wobble signal at the start of disk rotation, and then select a signal from the PLL circuit unit.
  • a PLL circuit unit that runs on its own center frequency can be used.
  • the locked state when the frequency of the pebble signal obtained from the optical disk is within a predetermined range, it is determined that the locked state is established.
  • the output signal from the PLL circuit that performs the PLL process on the signal is selectively output, and the CLV control is performed based on the selected output signal.
  • the determination of the locked state it can be determined that the locked state is not established when the missing of the pebble signal is continuously performed a predetermined number of times, or that the locked state is not determined when the missing of the pebble signal is present for a predetermined time.
  • the selector section selects a wobble signal at the start of disk rotation, and then selectively outputs a signal from the PLL circuit section.
  • FIG. 1 is a block diagram showing an embodiment of a CLV control circuit of an optical disk device according to the present invention.
  • FIG. 2 is a diagram showing a configuration example of a PLL circuit unit in FIG.
  • FIG. 3 is a diagram showing the input / output logic of the phase comparator 81 in FIG.
  • FIG. 4 is a timing chart of the signals of the respective parts in FIG. 1 when a flaw of about several hundreds / zm is present on the disk and the wobble signal is lost.
  • FIG. 5 is a time chart for explaining a problem when the PLL circuit section 8 is continued without switching the selector 7 to a wobble signal in the unlocked state in FIG.
  • FIG. 6 is a timing chart of the signals of the various parts when the missing of the wobble signal continues for several hundred msec due to abnormal recording or the like.
  • FIG. 7 is a timing chart of signals of various parts showing a pull-in operation of the CLV control from a state where the motor is stopped.
  • FIG. 8 shows the configuration of a second embodiment of the CLV control circuit of the optical disk device according to the present invention. It is a block diagram.
  • FIG. 9 is a timing chart of signals of the respective units when the center frequency of the PLL circuit unit 8 in FIG. 8 is offset.
  • FIG. 10 is a configuration block diagram of a third embodiment of the CLV control circuit of the optical disk device according to the present invention.
  • FIG. 11 is a configuration block diagram showing another embodiment of the present invention.
  • FIG. 11 is a flowchart showing the operation procedure of the embodiment shown in FIG.
  • FIG. 12 is a flowchart showing the operation procedure of the embodiment shown in FIG.
  • FIG. 13 is a flowchart showing the operation procedure of the embodiment shown in FIG.
  • FIG. 14 is a timing chart for explaining a state when a wobble signal is lost due to a fine scratch on a disk in the embodiment of the present invention.
  • FIG. 15 is a timing chart for explaining a state in which the loss of the wobble signal continues for several hundreds ms due to abnormal recording or the like in the embodiment of the present invention.
  • FIG. 16 is a block diagram showing a configuration example of a CLV control circuit of a conventional optical disc device.
  • FIG. 17 is a timing chart of various signals in the CLV control circuit of the conventional optical disk device shown in FIG.
  • FIG. 1 is a block diagram showing an embodiment of a CLV control circuit of an optical disk device according to the present invention.
  • components denoted by the same reference numerals as those in FIG. 16 are components having the same function.
  • the reference clock generator 6 sends a 1/8 frequency-divided clock of 16.9344 MHz clock from the crystal oscillator to the lock detector 9 and a 1/1024 frequency-divided clock to the CLV controller 5.
  • Output to The CLV controller 5 receives the output signal from the selector 7, compares the signal obtained by dividing the input by 1/8 with the clock supplied from the reference clock generator 6, and outputs a CLV control error signal D. And drive control of motor 2.
  • the PLL circuit section 8 includes a phase comparator 81, a low-pass filter (LPF) 82, and a voltage-controlled oscillator (VCO) 83.
  • the input / output logic of the phase comparator 81 is shown in FIG.
  • the output signal E becomes a signal with a duty of 50%
  • the input of the VC083 becomes the midpoint potential
  • the output signal of the VCO 83 B will run at the center frequency.
  • the selector 7 selects and outputs the wobble signal A and the output signal B of the PLL circuit unit 8 according to the output signal from the lock detection unit 9. In other words, the selector 7 supplies the wobble signal A to the CLV controller 5 when in the unlock state and the output signal B of the PLL circuit section 8 when in the unlock state.
  • FIG. 4 shows a timing chart of the signals of the respective parts in FIG. 1 when a small flaw of about several hundreds of micrometers exists on the disk and the pebble signal A is lost only for a short time.
  • the linear velocity is V [m / s] and the scratch width is w [m]
  • the lock detection unit has the above-described 3.6 ms ec determination delay time until the unlock state is detected, and thus holds the lock state “L” until that time. Therefore, the output signal from the PLL circuit section 8 is continuously selected by the selector 7 in the CLV control section 5. Therefore, since the frequency of the output signal from the selector 7 is 22.05 kHz, the CLV control unit 5 applies the error voltage (0 V) at the middle point to the motor 2. Since 0V voltage, that is, no energy is supplied to the motor 2, the motor 2 is in an inertia state without being accelerated or decelerated, and there is no servo disturbance.
  • the double signal A is detected again within 3.6 ms e above. Then, since the PLL circuit unit 8 can perform the PLL process on the frequency of the detected wobble signal A, the stable control can be restarted without causing the servo disturbance.
  • the time chart of FIG. 5 shows the problem that occurs when the loss of the cobble signal A continues for more than 6 ms ec, that is, when the PLL circuit 8 is continued without switching the selector 7 to the cobble signal in the unlocked state. It will be described based on the following. As described above, the output signal of the PLL circuit section 8 outputs the center frequency of 22.05 kHz during the period when there is no input of the wobble signal (period in FIG. 5).
  • the pebble signal starts to be detected at a frequency considerably lower than 22.05 kHz because the rotation speed of the motor 2 is reduced.
  • the output of the PLL controller can only output a frequency in the range close to the PLL lock range, so it depends on the PLL setting, but it is roughly 1/2 to 2 times 22.5 kHz. The degree is limited.
  • the signal output from the PLL control unit is about 11 kHz. Therefore, the output of the CLV control unit 5 does not reach the maximum acceleration error value, the motor 2 can be driven only at a considerably low acceleration value, and the subsequent convergence takes time.
  • FIG. 5 is a timing chart of signals of respective parts showing a pull-in operation of the CLV control from a state where the motor is stopped. Until the PLL lock range is reached, CLV control is performed by the wobble signal, so that the servo can be quickly pulled in without limiting the D range of the PLL. At the time when the lock detecting section 9 determines the long state, the servo operation is not adversely affected because the lock detecting section 9 is within the PLL lock range.
  • FIG. 8 is a block diagram of a second embodiment of the CLV control circuit of the optical disk device according to the present invention.
  • the micro combination 10 receives the output signal from the lock detection unit 9 and controls the operation of the selector 7. At this time, the center frequency of the PLL circuit section 8 is not set to 22.05 kHz, but offset by a predetermined amount from 22.05 kHz during the period of the cobble signal loss in order to apply a bias voltage to the module 2 be able to.
  • FIG. 9 shows a timing chart of signals of each section when the center frequency of the PLL circuit section 8 is offset.
  • the center frequency is set to about 20 kHz
  • a signal of 20 kHz is input to the CLV control unit 5 during the period of the loss of the pebble signal in the locked state, and the output D of the CLV control unit 5 becomes
  • the error signal on the acceleration side is equivalent to the offset of 2.05 kHz. Therefore, the motor 2 can be driven not by inertia but by a predetermined voltage to maintain the rotation speed. This example is effective when the moment of inertia of the rotating mechanism system including the motor is small.
  • the PLL circuit section 8 in the absence of a pebble signal may be configured to run by itself at the minimum frequency of the VCO.
  • the output of the VC083 drops to the set minimum frequency of the VCO during the period of the loss of the pebble signal.
  • the motor is driven to the acceleration side and the rotation speed is maintained.
  • the range of the PLL circuit section 8 should be appropriately set, for example, to 22.05 kHz. If the range is 0 kHz to 24 kHz, the PLL output frequency during the missing period will be 20 kHz, and the same effect as the offset described above will be obtained.
  • FIG. 10 is a configuration block diagram.
  • the configuration is such that the frequency signal 11 of the frequency signal A of the frequency signal detector 4 is frequency-divided by the frequency divider 11 and the frequency-divided signal E is input to the microcombiner 10. It has become.
  • the microcomputer 10 measures the period of the frequency-divided signal E by using a counter and a timer inside the microcomputer, and sends a lock / unlock detection signal C to the selector 7.
  • the process of detection of the lock / unlock detection is executed by two interrupt processing programs that use the divided wobble signal E and the end of the timer set at 3.6 ms ec as the interrupt generation signals. Is done.
  • the counter is configured by 16 bits in this embodiment.
  • the reference clock to be used is 1 MHz generated by dividing the frequency of the oscillation clock of the crystal oscillator (not shown) of the micro combination 10. Therefore, the minimum measurement time is, and the maximum measurement time is 65.535 ms ec, where the 16-bit count is hexadecimal "FFFFH". When counting is performed up to this "FFFFH", the count operation ends in the state of "FFFFH”.
  • the period of the frequency-divided signal E is measured at the above count, and if the count value is greater than or equal to 1613 hexadecimal “013BH” (decimal 315) and less than “01ABH” (decimal 427), it is possible. It can be detected that the signal A is within ⁇ 15% of the specified frequency.
  • the timer since the above-mentioned timer is set to 3.6 ms ec, an interrupt is generated when 3.6 ms ec has elapsed since the start of the timer.
  • the microcombination 10 is programmed so that every time a divided signal is input, Detects wake-up and wake-up. If it is in the wake-up state, it outputs a signal "L”, resets the timer each time, and starts anew. On the other hand, in the unlocked state, the timer does not reset and start, and outputs the signal "H" as an unlock signal on the interrupt program due to the end of timer counting. As a result, the signal "H" can be output as the unlocked state if the locked state is not continued during the 3.6 ms ec period.
  • FIG. 11 shows an interrupt process in which an interrupt occurs at the edge of the divided signal E (S100).
  • S101 the 16-bit count value of the counter is taken into the AX register, which is a 16-bit register (S102).
  • the counter is reset to "000H” and the counting operation is started further.
  • it is checked whether or not the value of the register AX is in the range from “0 13 BH” to “01 ABH”, that is, whether or not the frequency-divided signal E is in the speech range (S 104).
  • step S104 If it is determined in step S104 that it is out of the lock range, the process skips steps S105 and S106 described above, performs interrupt permission (S107), and ends the interrupt processing.
  • FIG. 13 is a flowchart showing a pull-in operation of the CLV control from the motor stop state.
  • FIG. 14 illustrates a case where, in FIG. 11 described above, once determined to be NO in S104, but again determined to be YES in S104 within 3.6 ms ec. This can be rephrased as the case where the micro signal is determined to be in a locked state even though the signal of the wobbled signal is lost.
  • a signal A indicates an output signal of the cobble detection unit 4 and a signal B indicates an output signal of the PLL circuit unit 8.
  • the count indicates the count-up operation of the 16-bit count configured in the microcomputer 10, and the set time is set to 3.6 ms ec set in the microphone computer 10. In the evening, the timer operation is shown.
  • the signal C is a signal output from the micro combination 10 to the selector 7, the signal D is the output signal of the CLV control unit 5, and the signal E is the output signal of the frequency divider.
  • the microcomputer 10 inputs the frequency-divided signal E, which is input as an interrupt signal, so that an interrupt process occurs at the rising edge. That is, an interrupt is generated at the positions 1 to 5 shown in FIG.
  • the interruption by this frequency-divided signal is S100 in FIG. 11 described above, from which the flowchart processing in FIG. 11 is started.
  • the wobble signal A is missing, but the signal “L” indicating the locked state is output from the microcomputer overnight 10 to the selector 7. That is, a signal from the PLL control unit is input to the CLV control unit 5.
  • the PLL circuit section outputs the center frequency of 22.05 kHz to the CLV control section 5 since the PLL circuit section lacks the cobble signal as in the first embodiment described above.
  • the CLV control unit 5 applies 0 V as the error voltage at the middle point without outputting the acceleration / deceleration signal to the module 2. Since no voltage is supplied to motor 2, an inertial circuit state occurs. In general, the inertia of the motor is large, and it rotates with the disk, so the rotation speed does not change in this time (several ms e c). Therefore, no servo disturbance occurs.
  • 16 FH is fetched into the register AX in S102, the count is reset in S103, and the counting operation is restarted.
  • the signal A has returned to the normal state, so that it is detected in S104 that the cycle of the frequency-divided signal is within the lock range. Then, a signal “L” is output to the selector 7 (S 105), the timer is reset, and the clock is restarted. It is opened (S106). At this time, it is assumed that the time counted by the timer is 1.55 ms ec. In this case, since the timer set value has not reached 3.6 ms ec, the interrupt processing program shown in FIG. 12 is not executed. That is, in the case shown in FIG. 14, the output signal to the selector 7 does not become “H” and remains “L”, so that the CLV controller 5 It is controlled by this signal.
  • FIG. 15 shows the first
  • the location (1) indicates the start of the process of S100 in FIG. 11c.
  • the counter value is taken into the register AX (S102). ), The counter is reset and the counter operation is restarted (S103). Then, in S104, assuming that the value in the mouth area has been taken into AX, the process proceeds to S105, and a signal “L” indicating the locked state is output to the selector 7. Then, the timer is reset in S106, and the timing operation starts.
  • the timer ends at the preset 3.6 ms e c. Then, the interrupt processing shown in FIG. 12 occurs (S200, S201).
  • the microcomputer 10 outputs a signal "H" to the selector 7, and ends the program processing. Note that the time t from the point at which the wobble signal is lost to the point at which the selector 7 is switched is the time set by the timer, that is, 3.6 ms e c.
  • the selector 7 switches its input signal from the PLL circuit unit 8 to the cobble detection unit 4.
  • a signal from the cobble detector 4 is input to the CLV controller 5.
  • the signal input to the CLV control unit 5 is also missing because the signal A is in a missing state. Therefore.
  • the CLV control unit 5 drives the motor 2 with the maximum acceleration error value.
  • the CLV controller 5 keeps holding the maximum acceleration error value during the period during which the wobble signal is missing, the motor 2 generally stops at the maximum rotation speed. It will be rotated by a number. Therefore, since the disk can be quickly passed through the abnormal recording part of the disk, the signal A can be read again promptly.
  • the point where the wobble signal A is read again is indicated by the point 3 in the figure. Since the rising edge of the frequency-divided signal E occurs in the simple case of (3), the microphone port computer 10 can execute the flowchart processing of FIG. During this processing, FFFFH is taken into the register AX in S102. Therefore, it is determined that the locked state is not established in S104, and the unlock signal "H" is continuously output to the selector 7. That is, at this point, the selector 7 has not been switched yet, and the coble signal A is still supplied to the CLV control circuit 5.
  • the CLV control unit 5 compares the signal obtained by internally dividing the frequency of the pebble signal A by 8 with the reference clock obtained from the reference clock generation unit 6, and detects that the motor 2 is rotating beyond the specified speed. And outputs a deceleration error signal to motor 2.
  • Mo In the evening 2, the motor decelerates in response to the deceleration error signal and starts to return to the specified speed. Thereafter, the rotation speed of the motor 2 approaches the specified rotation speed under the control of the CLV control unit 5, and the frequency of the fob signal read from the disk falls within 15% of the specified frequency 22.05 kHz. Becomes
  • the CLV control circuit of the optical disk device of the present invention even if a wobble signal is lost due to a scratch or dust on the disk, noise is significantly suppressed as compared with the conventional case. This enables quick and stable disk rotation control. In particular, when there is no input signal, use of a PLL circuit that runs at the center frequency does not impede the pull-in performance of the servo.

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Abstract

Cette invention concerne un appareil de commande à vitesse linéaire constante pour lecteur de disque optique, lequel appareil permet d'éliminer le bruit dans le cas d'une perte de niveau des signaux d'oscillation due à la poussière, etc., et facilite la rotation rapide et stable du disque. Le circuit de commande va considérer l'état de fonctionnement comme un état bloqué lorsque la fréquence du signal d'oscillation provenant d'un disque optique se trouve dans une gamme prédéterminée. Le circuit va ensuite sélectionner le signal d'oscillation lorsqu'il considère que l'état ne correspond pas à l'état bloqué, puis sélectionner et émettre un signal de sortie depuis un circuit à verrouillage de phase (PLL) pour le signal d'oscillation lorsqu'il estime que l'état correspond à l'état bloqué, et, enfin, exécuter une commande à vitesse linéaire constante en fonction du signal de sortie sélectionné. L'état bloqué peut être confirmé lorsque les répétitions de pertes de niveau des signaux d'oscillation atteignent un nombre prédéterminé, ou encore, en mesurant une durée prédéterminée de perte de niveau. Une partie sélection va choisir le signal d'oscillation pendant la rotation du disque, puis sélectionner et émettre le signal depuis une partie circuit à verrouillage de phase (PLL).
PCT/JP1995/001787 1994-02-25 1995-09-08 Circuit de commande a vitesse lineaire constante pour appareil a disque optique WO1997009717A1 (fr)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP7062163A JPH07287931A (ja) 1994-02-25 1995-02-24 光ディスク装置のｃｌｖ制御回路
PCT/JP1995/001787 WO1997009717A1 (fr) 1995-02-24 1995-09-08 Circuit de commande a vitesse lineaire constante pour appareil a disque optique

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP7062163A JPH07287931A (ja) 1994-02-25 1995-02-24 光ディスク装置のｃｌｖ制御回路
PCT/JP1995/001787 WO1997009717A1 (fr) 1995-02-24 1995-09-08 Circuit de commande a vitesse lineaire constante pour appareil a disque optique

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0872837A2 (fr) * 1997-04-15 1998-10-21 Ricoh Company, Ltd. Unité de disque et dispositif de commande de moteur de rotation pour unité de disque enregistrable

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5975453A (ja) * 1982-10-22 1984-04-28 Akai Electric Co Ltd ドロツプアウト補償サ−ボ装置
JPH02294288A (ja) * 1989-05-02 1990-12-05 Nec Ibaraki Ltd 位相ロックループ回路
JPH04265523A (ja) * 1991-02-19 1992-09-21 Pioneer Electron Corp 追記形光ディスクの回転速度制御方法および装置
JPH07130086A (ja) * 1993-10-29 1995-05-19 Kenwood Corp 光ディスク装置のスピンドル制御回路

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5975453A (ja) * 1982-10-22 1984-04-28 Akai Electric Co Ltd ドロツプアウト補償サ−ボ装置
JPH02294288A (ja) * 1989-05-02 1990-12-05 Nec Ibaraki Ltd 位相ロックループ回路
JPH04265523A (ja) * 1991-02-19 1992-09-21 Pioneer Electron Corp 追記形光ディスクの回転速度制御方法および装置
JPH07130086A (ja) * 1993-10-29 1995-05-19 Kenwood Corp 光ディスク装置のスピンドル制御回路

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0872837A2 (fr) * 1997-04-15 1998-10-21 Ricoh Company, Ltd. Unité de disque et dispositif de commande de moteur de rotation pour unité de disque enregistrable
EP0872837A3 (fr) * 1997-04-15 1999-09-22 Ricoh Company, Ltd. Unité de disque et dispositif de commande de moteur de rotation pour unité de disque enregistrable
US6128261A (en) * 1997-04-15 2000-10-03 Ricoh Company, Ltd. Disk unit and rotating motor control apparatus for recordable optical disk unit
US6333903B1 (en) 1997-04-15 2001-12-25 Ricoh Company, Ltd. Disk unit and rotating motor control apparatus for recordable optical disk unit

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