WO1997009717A1

WO1997009717A1 - Clv control circuit of optical disk apparatus

Info

Publication number: WO1997009717A1
Application number: PCT/JP1995/001787
Authority: WO
Inventors: Akihiro Arisaka
Original assignee: Kabushiki Kaisha Kenwood
Priority date: 1995-02-24
Filing date: 1995-09-08
Publication date: 1997-03-13

Abstract

A CLV control apparatus for an optical disk drive, which can suppress noise in the event of dropout of wobble signals due to dust, etc, and facilitates quick and stable disk rotation. The control circuit judges the operation state as a lock state when the frequency of the wobble signal obtained from an optical disk is withing a predetermined range, selects the wobble signal when the state is not judged as the lock state, selects and outputs the output signal from a PLL circuit for the wobble signal when the state is judged as the lock state, and executes the CLV control on the basis of this selection output signal. The lock state may be confirmed by counting a predetermined number of repeats of dropout of wobble signals or detecting a predetermined duration of dropout. A selector portion selects the wobble signal during the rotation of the disk and thereafter selects and outputs the signal from a PLL circuit portion.

Description

Specification

CLV control circuit of optical disk device

Technical field

The present invention relates to a CLV control circuit for an optical disk device, and more particularly to a CLV control circuit for an optical disk device that ensures stable operation even when a wobble signal is lost due to a scratch, dust, or the like.

d

Landscape technology

The CLV control for maintaining and controlling an optical disc (hereinafter, referred to as a disc) at a constant linear velocity (CLV) is performed based on a wobble signal obtained by detecting pregroove information engraved on the disc by an optical big-up.

FIG. 9 is a block diagram showing a configuration example of a CLV control circuit of a conventional optical disc device. The rotation of the disk 1 is controlled by the motor 2 and the information stored in the disk 1 detected by the optical pickup 3 is converted into a wobble signal by the wobble detector 4 based on the pre-group engraved on the disk. A 'is detected. The CLV controller 5 generates a CLV control signal based on the detected wobble signal A ′ and the reference clock signal from the reference clock generator 6 and controls the motor 2. Disclosure of the invention

However, the above-described CLV control circuit is capable of controlling the CLV even when there is a long-time loss of the wobble signal due to abnormal recording or the like, or even when there is a short-time loss of the wobble signal due to small scratches or dust. The control was disturbed. That is, the conventional optical disk CLV control circuit performs CLV control based on the optical signal A 'detected from the pre-group of the optical disk. However, if a scratch or dust is present on the disc, as shown in FIG. 17, a pebble signal cannot be detected, and a missing portion of the period t 'occurs. As a result, (the output signal 0 'of the ¥ control unit 5 sticks to the acceleration side with a delay of time t〃. In FIG. 10, the output signal D' is positive at the time of acceleration error centering on 0V. The voltage signal is output as a negative voltage signal at the time of the decompression error, and the CLV control unit 5 divides the frequency of the cobble signal A 'and compares it with the reference clock signal. There is a delay due to the built-in filter. Therefore, the disk does not have a constant linear velocity during the missing period, and the linear velocity further increases. After that, even if the wobble signal A 'is detected after passing through the missing part, the signal 1)' sticks to the deceleration side and tries to return to the constant linear velocity state because the disk is rotating at high speed. However, the servo operation becomes stable only after a lapse of a time t longer than the missing period t 'of the wobble signal A' due to scratches or dust, and it is difficult to quickly perform a stable operation. For example, when the linear velocity of the disk is 1.4 m / s and there is a lmm scratch, the time t 'is t' = 1 x 10-3 / 1.4, that is, about 0.7 ms, and the servo is disturbed. The time t, which depends on the servo system and the radial position of the track, can reach about 2 ms. Incidentally, such small scratches and dust may be attached to a large number of discs, and in this case, a continuous loss of the wobble signal occurs. At this time, for example, if the wobble signal is lost again during the time t described above, the servo has been disturbed for a longer time.

Accordingly, an object of the present invention is to provide a CLV control circuit of an optical disk device that suppresses noise and enables quick and stable disk rotation even if a wobble signal is lost due to scratches or dust. It is in.

In order to solve the above-mentioned problems, a CLV control circuit of an optical disk device according to the present invention is a CLV control circuit of an optical disk device for controlling a constant linear velocity (CLV) of an optical disk.

A wobble detection unit for detecting a wobble signal obtained from the optical disc;

A PLL circuit section for performing PLL processing on the wobble signal;

A lock detector that determines that the lock state is established when the frequency of the wobble signal is within a predetermined range;

A selector unit for selecting and outputting a wobble signal when the whacking detection unit determines that the whipping state is not set, and selectively outputting an output signal from the PLL circuit unit when determining that the whipping state is determined;

And performing the CLV control based on an output signal from the selector unit.

A CLV control circuit of an optical disc device according to another aspect of the present invention includes: In the CLV control circuit of the optical disk device for controlling the constant linear velocity (CLV) of the optical disk,

A wobble detection unit that detects a wobble signal obtained from an optical disc; a PLL circuit unit that performs a PLL process on the wobble signal;

A lock detection unit that determines that the wobble signal is not in the hooking state when there is a predetermined number of consecutive missing of the wobble signal;

A selector unit for selecting and outputting a wobble signal when the mouthpiece detection unit determines that the mouthpiece is not in a hooking state and an output signal from the PLL circuit unit when determining that the mouthpiece is in the mouthpiece state;

A CLV control circuit of an optical disc device according to still another aspect of the present invention,

In the CLV control circuit of the optical disk device for controlling the constant linear velocity (CLV) of the optical disk,

A wobbled detector for detecting a wobbled signal obtained from an optical disc; a PLL circuit for PLL-processing the wobbled signal;

An mouth detection unit that determines that the locked state is not established when the wobble signal is missing for a predetermined time;

And configured to perform the CLV control based on an output signal from the selector unit.

A CLV control circuit of the optical disc device according to another aspect of the present invention includes:

The wobble signal and the signal from the PLL circuit are selected and output to the CLV control unit. Selector part to be

The selector unit is configured to select a wobble signal at the start of disk rotation, and then select a signal from the PLL circuit unit.

Here, in the absence of a pebble signal, a PLL circuit unit that runs on its own center frequency can be used.

According to the present invention, when the frequency of the pebble signal obtained from the optical disk is within a predetermined range, it is determined that the locked state is established. When the judgment is made, the output signal from the PLL circuit that performs the PLL process on the signal is selectively output, and the CLV control is performed based on the selected output signal. In the determination of the locked state, it can be determined that the locked state is not established when the missing of the pebble signal is continuously performed a predetermined number of times, or that the locked state is not determined when the missing of the pebble signal is present for a predetermined time. The selector section selects a wobble signal at the start of disk rotation, and then selectively outputs a signal from the PLL circuit section.

BRIEF DESCRIPTION OF THE FIGURES

FIG. 1 is a block diagram showing an embodiment of a CLV control circuit of an optical disk device according to the present invention.

FIG. 2 is a diagram showing a configuration example of a PLL circuit unit in FIG.

FIG. 3 is a diagram showing the input / output logic of the phase comparator 81 in FIG. FIG. 4 is a timing chart of the signals of the respective parts in FIG. 1 when a flaw of about several hundreds / zm is present on the disk and the wobble signal is lost.

FIG. 5 is a time chart for explaining a problem when the PLL circuit section 8 is continued without switching the selector 7 to a wobble signal in the unlocked state in FIG.

FIG. 6 is a timing chart of the signals of the various parts when the missing of the wobble signal continues for several hundred msec due to abnormal recording or the like.

FIG. 7 is a timing chart of signals of various parts showing a pull-in operation of the CLV control from a state where the motor is stopped.

FIG. 8 shows the configuration of a second embodiment of the CLV control circuit of the optical disk device according to the present invention. It is a block diagram.

FIG. 9 is a timing chart of signals of the respective units when the center frequency of the PLL circuit unit 8 in FIG. 8 is offset.

FIG. 10 is a configuration block diagram of a third embodiment of the CLV control circuit of the optical disk device according to the present invention.

FIG. 11 is a configuration block diagram showing another embodiment of the present invention.

FIG. 11 is a flowchart showing the operation procedure of the embodiment shown in FIG. FIG. 12 is a flowchart showing the operation procedure of the embodiment shown in FIG. FIG. 13 is a flowchart showing the operation procedure of the embodiment shown in FIG. FIG. 14 is a timing chart for explaining a state when a wobble signal is lost due to a fine scratch on a disk in the embodiment of the present invention.

FIG. 15 is a timing chart for explaining a state in which the loss of the wobble signal continues for several hundreds ms due to abnormal recording or the like in the embodiment of the present invention. FIG. 16 is a block diagram showing a configuration example of a CLV control circuit of a conventional optical disc device.

FIG. 17 is a timing chart of various signals in the CLV control circuit of the conventional optical disk device shown in FIG.

BEST MODE FOR CARRYING OUT THE INVENTION

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of a CLV control circuit of an optical disk device according to the present invention. In FIG. 1, components denoted by the same reference numerals as those in FIG. 16 are components having the same function.

For example, the reference clock generator 6 sends a 1/8 frequency-divided clock of 16.9344 MHz clock from the crystal oscillator to the lock detector 9 and a 1/1024 frequency-divided clock to the CLV controller 5. Output to The CLV controller 5 receives the output signal from the selector 7, compares the signal obtained by dividing the input by 1/8 with the clock supplied from the reference clock generator 6, and outputs a CLV control error signal D. And drive control of motor 2.

The lock detector 9 divides the frequency of the pebble signal by 1/8 and generates the divided signal as a reference clock. Compare with the output clock from the generator 6 (16.9344MHz / 8/8-2 168MHz). Then, it is determined whether or not the frequency of the wobble signal is within a standard frequency of 22.05 KHZ, for example, within ± 15%. If at least one time is within the above ± 15%, it is determined to be in the lock state and the "L" signal is output. As described above, since the unlocked state is not output unless it is determined to be consecutive 10 times, there is a delay from the loss of the first pebble signal to the output of the unlocked state determination signal "H". Time exists. In the example of the Rongk detector 9 in this embodiment, the delay time t is t = 8 × 10 / (22.05 × 10 ³ ), that is, approximately 3.6 ms ec.

As shown in FIG. 2, the PLL circuit section 8 includes a phase comparator 81, a low-pass filter (LPF) 82, and a voltage-controlled oscillator (VCO) 83. The input / output logic of the phase comparator 81 is shown in FIG. In this embodiment, when the input signal A is lost and the state of "L" is maintained, the output signal E becomes a signal with a duty of 50%, the input of the VC083 becomes the midpoint potential, and as a result, the output signal of the VCO 83 B will run at the center frequency.

The selector 7 selects and outputs the wobble signal A and the output signal B of the PLL circuit unit 8 according to the output signal from the lock detection unit 9. In other words, the selector 7 supplies the wobble signal A to the CLV controller 5 when in the unlock state and the output signal B of the PLL circuit section 8 when in the unlock state.

FIG. 4 shows a timing chart of the signals of the respective parts in FIG. 1 when a small flaw of about several hundreds of micrometers exists on the disk and the pebble signal A is lost only for a short time. Assuming that the linear velocity is V [m / s] and the scratch width is w [m], the wobble signal A is dropped during the time t = w / v [s]. Since the PLL circuit section 8 has a configuration as shown in FIG. 2, a signal B having a center frequency of 22.05 kHz of the VC083 is output while the signal A is missing.

As described above, the lock detection unit has the above-described 3.6 ms ec determination delay time until the unlock state is detected, and thus holds the lock state “L” until that time. Therefore, the output signal from the PLL circuit section 8 is continuously selected by the selector 7 in the CLV control section 5. Therefore, since the frequency of the output signal from the selector 7 is 22.05 kHz, the CLV control unit 5 applies the error voltage (0 V) at the middle point to the motor 2. Since 0V voltage, that is, no energy is supplied to the motor 2, the motor 2 is in an inertia state without being accelerated or decelerated, and there is no servo disturbance.

In this case, since it is a small flaw, the double signal A is detected again within 3.6 ms e above. Then, since the PLL circuit unit 8 can perform the PLL process on the frequency of the detected wobble signal A, the stable control can be restarted without causing the servo disturbance.

Next, a description will be given of an example in which the loss of the pebble signal A continues for several hundred ms ec or more due to abnormal recording or the like, that is, for 3.6 ms ec or more. 3. The time chart of FIG. 5 shows the problem that occurs when the loss of the cobble signal A continues for more than 6 ms ec, that is, when the PLL circuit 8 is continued without switching the selector 7 to the cobble signal in the unlocked state. It will be described based on the following. As described above, the output signal of the PLL circuit section 8 outputs the center frequency of 22.05 kHz during the period when there is no input of the wobble signal (period in FIG. 5). Becomes 0V, and no voltage is applied in the motor mode. For this reason, during the period in which the wobble signal is missing, the rotation speed of the motor 2 decreases, and the motor 2 approaches a stopped state. At this time, if the missing period is long enough, it is possible that Mo2 will stop.

As described above, when the long period of the short period of the pebble signal ends, the pebble signal starts to be detected at a frequency considerably lower than 22.05 kHz because the rotation speed of the motor 2 is reduced. However, the output of the PLL controller can only output a frequency in the range close to the PLL lock range, so it depends on the PLL setting, but it is roughly 1/2 to 2 times 22.5 kHz. The degree is limited.

For this reason, even if the actually obtained wobble signal is several hundred Hz, the signal output from the PLL control unit is about 11 kHz. Therefore, the output of the CLV control unit 5 does not reach the maximum acceleration error value, the motor 2 can be driven only at a considerably low acceleration value, and the subsequent convergence takes time.

On the other hand, in the present embodiment, the loss of the wobble signal due to abnormal recording or the like is several hundred ms. If ec continues, as shown in the timing chart of Fig. 6, the lock detector 9 outputs the unlocked state "H" after the determination delay of t0 = 3.6ms ec. Select a wobbled signal instead of circuit section 8. Therefore, since the wobbled signal is input to the CLV control unit 5, the servo is quickly pulled in.

FIG. 5 is a timing chart of signals of respective parts showing a pull-in operation of the CLV control from a state where the motor is stopped. Until the PLL lock range is reached, CLV control is performed by the wobble signal, so that the servo can be quickly pulled in without limiting the D range of the PLL. At the time when the lock detecting section 9 determines the long state, the servo operation is not adversely affected because the lock detecting section 9 is within the PLL lock range.

FIG. 8 is a block diagram of a second embodiment of the CLV control circuit of the optical disk device according to the present invention. FIG.

In this embodiment, the micro combination 10 receives the output signal from the lock detection unit 9 and controls the operation of the selector 7. At this time, the center frequency of the PLL circuit section 8 is not set to 22.05 kHz, but offset by a predetermined amount from 22.05 kHz during the period of the cobble signal loss in order to apply a bias voltage to the module 2 be able to. FIG. 9 shows a timing chart of signals of each section when the center frequency of the PLL circuit section 8 is offset. For example, if the center frequency is set to about 20 kHz, a signal of 20 kHz is input to the CLV control unit 5 during the period of the loss of the pebble signal in the locked state, and the output D of the CLV control unit 5 becomes The error signal on the acceleration side is equivalent to the offset of 2.05 kHz. Therefore, the motor 2 can be driven not by inertia but by a predetermined voltage to maintain the rotation speed. This example is effective when the moment of inertia of the rotating mechanism system including the motor is small. In the second embodiment, the PLL circuit section 8 in the absence of a pebble signal may be configured to run by itself at the minimum frequency of the VCO. In this case, the output of the VC083 drops to the set minimum frequency of the VCO during the period of the loss of the pebble signal. As a result, the motor is driven to the acceleration side and the rotation speed is maintained. At this time, the range of the PLL circuit section 8 should be appropriately set, for example, to 22.05 kHz. If the range is 0 kHz to 24 kHz, the PLL output frequency during the missing period will be 20 kHz, and the same effect as the offset described above will be obtained.

Next, a third embodiment will be described with reference to FIGS. 10 to 15. FIG. 10 is a configuration block diagram. In this embodiment, the configuration is such that the frequency signal 11 of the frequency signal A of the frequency signal detector 4 is frequency-divided by the frequency divider 11 and the frequency-divided signal E is input to the microcombiner 10. It has become. The microcomputer 10 measures the period of the frequency-divided signal E by using a counter and a timer inside the microcomputer, and sends a lock / unlock detection signal C to the selector 7. The process of detection of the lock / unlock detection is executed by two interrupt processing programs that use the divided wobble signal E and the end of the timer set at 3.6 ms ec as the interrupt generation signals. Is done. The counter is configured by 16 bits in this embodiment. The reference clock to be used is 1 MHz generated by dividing the frequency of the oscillation clock of the crystal oscillator (not shown) of the micro combination 10. Therefore, the minimum measurement time is, and the maximum measurement time is 65.535 ms ec, where the 16-bit count is hexadecimal "FFFFH". When counting is performed up to this "FFFFH", the count operation ends in the state of "FFFFH". The specified frequency of the Woburu signal A are the 22. 05 kH, 1 period of the divided signal E after divided by 8 is a ^{1Z (22. 05x l 0 3/} 8) = 362. 8 zs ec. Also, one cycle of the divided signal of ± 15% of the specified frequency is

1 / (22.05 E 3 * 1.15 / 8) = 315.5 s e c

1 / (22.05 E 3 * 1.85 / 8) = 426.8 z S E C

Becomes

Therefore, the period of the frequency-divided signal E is measured at the above count, and if the count value is greater than or equal to 1613 hexadecimal “013BH” (decimal 315) and less than “01ABH” (decimal 427), it is possible. It can be detected that the signal A is within ± 15% of the specified frequency.

Furthermore, since the above-mentioned timer is set to 3.6 ms ec, an interrupt is generated when 3.6 ms ec has elapsed since the start of the timer. The microcombination 10 is programmed so that every time a divided signal is input, Detects wake-up and wake-up. If it is in the wake-up state, it outputs a signal "L", resets the timer each time, and starts anew. On the other hand, in the unlocked state, the timer does not reset and start, and outputs the signal "H" as an unlock signal on the interrupt program due to the end of timer counting. As a result, the signal "H" can be output as the unlocked state if the locked state is not continued during the 3.6 ms ec period.

First, an example of a flowchart of this program will be described with reference to FIGS. 11 to 13. FIG. 11 shows an interrupt process in which an interrupt occurs at the edge of the divided signal E (S100). First, with interrupts disabled (S101), the 16-bit count value of the counter is taken into the AX register, which is a 16-bit register (S102). Next, the counter is reset to "000H" and the counting operation is started further. Then, it is checked whether or not the value of the register AX is in the range from “0 13 BH” to “01 ABH”, that is, whether or not the frequency-divided signal E is in the speech range (S 104). Here, if it is within the lock range, it is determined that the micro combination is in a locked state, and a signal “L” is output to the selector 7 (S 105), and the timer 3.6 ms ec setting is reset. The measurement is started (S106). Then, after the interruption is enabled (S107), the process returns to S100 again (S108).

If it is determined in step S104 that it is out of the lock range, the process skips steps S105 and S106 described above, performs interrupt permission (S107), and ends the interrupt processing.

At this time, if it is checked in S104 that the lock is out of the lock range, the process of resetting the image (S106) is skipped as described above. Here, in the event that the receiver determines that the frequency-divided signal E is out of the lock range for 3.6 ms ec continuously (when it is determined that N 0 in S 104 for 3.6 ms ec continuous) As shown in FIG. 12, an interrupt process started from S200 is performed.

That is, first, after interrupts are disabled in S201, the microcomputer 10 sends a signal "H" indicating an unlocked state to the selector 7. Then, interrupt permission is executed (S203), and the interrupt processing ends. FIG. 13 is a flowchart showing a pull-in operation of the CLV control from the motor stop state.

Here, after passing through S1 and S2 as shown in the figure, "0 000 H" of the 16-bit counter is reset and the count operation is started. Then, the microcomputer 10 outputs an unlock signal “H” to the selector 7 to start the CLV control (S5). Then, since the rotation control of the disk motor 2 is performed, the control of the optical pickup 3 can be started (S6). At this point, since a wobble signal can be obtained, interrupt processing is enabled (S7).

Then, with the completion of the pull-in of the CLV control, processing such as reproduction / recording of the disc can be performed (S8).

Here, with reference to the timing chart of FIG. 14, a description will be given of a state when a wobble signal is missing due to a fine scratch on the disk. FIG. 14 illustrates a case where, in FIG. 11 described above, once determined to be NO in S104, but again determined to be YES in S104 within 3.6 ms ec. This can be rephrased as the case where the micro signal is determined to be in a locked state even though the signal of the wobbled signal is lost.

In the figure, a signal A indicates an output signal of the cobble detection unit 4 and a signal B indicates an output signal of the PLL circuit unit 8. Also, the count indicates the count-up operation of the 16-bit count configured in the microcomputer 10, and the set time is set to 3.6 ms ec set in the microphone computer 10. In the evening, the timer operation is shown. The signal C is a signal output from the micro combination 10 to the selector 7, the signal D is the output signal of the CLV control unit 5, and the signal E is the output signal of the frequency divider.

The microcomputer 10 inputs the frequency-divided signal E, which is input as an interrupt signal, so that an interrupt process occurs at the rising edge. That is, an interrupt is generated at the positions 1 to 5 shown in FIG. The interruption by this frequency-divided signal is S100 in FIG. 11 described above, from which the flowchart processing in FIG. 11 is started.

At point ① in Fig. 14, "16 BH" is taken into the register AX (S102). After that, the counter is reset in S103, and the counting operation is restarted. Further, in S104, it is detected that the cycle of the frequency-divided signal is within the lock range, and the signal "L" is output to the selector. Thereafter, the timer is reset to start timing (S106), and the interrupt processing ends (S107, S108).

Subsequently, an interrupt is performed at the point (2), but the progress of this processing is the same as the processing at the point (2). It is assumed that, after the interrupt processing at the point (1), the cobble signal A within 3.6 ms e has been lost as shown in the figure.

Then, in the interrupt at the point (3), 4A1H is taken into the register AX (S102). After that, the counter is reset in S103, and the counting operation is resumed. Then, in S104, since it is detected that the cycle of the frequency-divided signal E is out of the lock range, the timer is not reset and the time measurement is not started. That is, the counting operation started at the time of the interruption at the point (2) is continued. Note that the output from the microcombiner 10 to the selector 7 keeps the output "L" because the previous logic is continued.

Therefore, between the point (1) and the point (3), the wobble signal A is missing, but the signal “L” indicating the locked state is output from the microcomputer overnight 10 to the selector 7. That is, a signal from the PLL control unit is input to the CLV control unit 5. As a result, the PLL circuit section outputs the center frequency of 22.05 kHz to the CLV control section 5 since the PLL circuit section lacks the cobble signal as in the first embodiment described above. Then, the CLV control unit 5 applies 0 V as the error voltage at the middle point without outputting the acceleration / deceleration signal to the module 2. Since no voltage is supplied to motor 2, an inertial circuit state occurs. In general, the inertia of the motor is large, and it rotates with the disk, so the rotation speed does not change in this time (several ms e c). Therefore, no servo disturbance occurs.

Next, as for the interrupt at the point ④, 16 FH is fetched into the register AX in S102, the count is reset in S103, and the counting operation is restarted.

At this point, as shown in the drawing, the signal A has returned to the normal state, so that it is detected in S104 that the cycle of the frequency-divided signal is within the lock range. Then, a signal “L” is output to the selector 7 (S 105), the timer is reset, and the clock is restarted. It is opened (S106). At this time, it is assumed that the time counted by the timer is 1.55 ms ec. In this case, since the timer set value has not reached 3.6 ms ec, the interrupt processing program shown in FIG. 12 is not executed. That is, in the case shown in FIG. 14, the output signal to the selector 7 does not become “H” and remains “L”, so that the CLV controller 5 It is controlled by this signal.

Next, with reference to the timing chart of FIG. 15, a description will be given of a state in which the loss of the wobble signal continues for several hundred ms ec due to abnormal recording or the like. FIG. 15 shows the first

This is to explain a case where it is determined that NO is equal to or more than 3.6 ms e in S104 of FIG. It can be said that this is the case where it is determined from the micro combination 10 that the microphone is in the unlocked state due to the lack of the pebble signal for a long time. Here, the reference numerals in the figure are basically the same as those described in FIG. 14, and the description thereof will be omitted. However, the points ① to ④ are the interrupt start positions in the flowchart of FIG. 11 described above. It does not indicate.

First, the location (1) indicates the start of the process of S100 in FIG. _{11c. In} this case, similarly to the description in FIG. 14, the counter value is taken into the register AX (S102). ), The counter is reset and the counter operation is restarted (S103). Then, in S104, assuming that the value in the mouth area has been taken into AX, the process proceeds to S105, and a signal “L” indicating the locked state is output to the selector 7. Then, the timer is reset in S106, and the timing operation starts.

In principle, if the signal A is lost, the frequency-divided signal E does not change, and the frequency-divided signal holds the level of "L" or "H". That is, in the case of FIG. 15, it is kept at the “H” level. Also, the signal C from the microphone opening combination 10 to the selector 7 remains at the "L" or "H" level. Therefore, in the case of Fig. 15, after the point (1) has passed, since the signal A is lost, the microcombination 10 maintains the level of "L". In this case, if the loss of the wobble signal A continues, Since the rising edge of the signal E which is the interrupt signal does not come as described above, the processing of the flowchart in FIG. 11 is not executed.

Therefore, the timer ends at the preset 3.6 ms e c. Then, the interrupt processing shown in FIG. 12 occurs (S200, S201). Here, in S202, the microcomputer 10 outputs a signal "H" to the selector 7, and ends the program processing. Note that the time t from the point at which the wobble signal is lost to the point at which the selector 7 is switched is the time set by the timer, that is, 3.6 ms e c.

Here, the selector 7 switches its input signal from the PLL circuit unit 8 to the cobble detection unit 4. In other words, a signal from the cobble detector 4 is input to the CLV controller 5. Then, the signal input to the CLV control unit 5 is also missing because the signal A is in a missing state. Therefore. The CLV control unit 5 drives the motor 2 with the maximum acceleration error value.

Although the CLV controller 5 keeps holding the maximum acceleration error value during the period during which the wobble signal is missing, the motor 2 generally stops at the maximum rotation speed. It will be rotated by a number. Therefore, since the disk can be quickly passed through the abnormal recording part of the disk, the signal A can be read again promptly.

The point where the wobble signal A is read again is indicated by the point ③ in the figure. Since the rising edge of the frequency-divided signal E occurs in the simple case of (3), the microphone port computer 10 can execute the flowchart processing of FIG. During this processing, FFFFH is taken into the register AX in S102. Therefore, it is determined that the locked state is not established in S104, and the unlock signal "H" is continuously output to the selector 7. That is, at this point, the selector 7 has not been switched yet, and the coble signal A is still supplied to the CLV control circuit 5.

Therefore, the CLV control unit 5 compares the signal obtained by internally dividing the frequency of the pebble signal A by 8 with the reference clock obtained from the reference clock generation unit 6, and detects that the motor 2 is rotating beyond the specified speed. And outputs a deceleration error signal to motor 2. Mo —In the evening 2, the motor decelerates in response to the deceleration error signal and starts to return to the specified speed. Thereafter, the rotation speed of the motor 2 approaches the specified rotation speed under the control of the CLV control unit 5, and the frequency of the fob signal read from the disk falls within 15% of the specified frequency 22.05 kHz. Becomes

In such a state, if the rising edge of the frequency-divided signal E indicated by a point ④ in the figure occurs, the processing of the flowchart in FIG. 11 is repeatedly executed. Is determined as YES, the microcomputer 10 outputs the signal “L” to the selector 7. Therefore, the selector 7 is switched to the PLL circuit section 8. Thus, even if a long pebble signal over several hundred msec or more is lost, it is possible to quickly control the rotation of the disk.

As described above, according to the CLV control circuit of the optical disk device of the present invention, even if a wobble signal is lost due to a scratch or dust on the disk, noise is significantly suppressed as compared with the conventional case. This enables quick and stable disk rotation control. In particular, when there is no input signal, use of a PLL circuit that runs at the center frequency does not impede the pull-in performance of the servo.

Claims

The scope of the claims

1. In the CLV control circuit of the optical disk device for controlling the constant linear velocity (CLV) of the optical disk,

CLV control circuit for an optical disk device, comprising: performing the CLV control based on an output signal from the selector unit.

2. In the CLV control circuit of the optical disk device for controlling the constant linear velocity (CLV) of the optical disk,

A lock detection unit that determines that the wobble signal is not in the hooking state when the number of missing of the wobble signal is a predetermined number of times continuously;

A selector unit for selecting and outputting a wobble signal when the hooking detection unit determines that the hooking state is not present;

A CLV control circuit for an optical disc device, comprising: performing the CLV control based on an output signal from the selector unit.

3. In the CLV control circuit of the optical disk device for controlling the constant linear velocity (CLV) of the optical disk,

A wobble detection unit that detects a wobble signal obtained from an optical disc; a PLL circuit unit that performs PLL processing of the wobble signal;

An mouth detection unit that determines that the locked state is not established when the wobble signal is missing for a predetermined time; A selector unit for selecting and outputting a wobble signal when the mouthpiece detection unit determines that the mouthpiece is not in the mouthpiece state, and selectively outputting an output signal from the PLL circuit unit when determining that the mouthpiece is in the mouthpiece state;

CLV control circuit for an optical disc device, comprising: performing the CLV control based on an output signal from the selector unit.

4. In the CLV control circuit of the optical disk device for controlling the constant linear velocity (CLV) of the optical disk,

A wobbled detection unit that detects a wobbled signal obtained from an optical disc; a PLL circuit unit that performs a PLL process on the wobbled signal;

A selector unit that selects the wobble signal and a signal from the PLL circuit and outputs the selected signal to a CLV control unit;

CLV control circuit for an optical disc device, characterized in that the selector section selects a wobble signal at the start of rotation of the disc, and then selects a signal from a PLL circuit section.

5. The CLV control circuit for an optical disk device according to claim 1, wherein a PLL circuit section that runs at a center frequency when there is no signal is used.