JPH0260483A - Revolution controller for magnetic disk - Google Patents

Abstract

PURPOSE:To shorten the rise time by controlling the number of revolution by a speed control circuit on the rise of a spindle motor, by a phase control circuit after stationary revolution is brought and by a voltage signal transmitted to the spindle motor on stationary revolution at the time of transfer. CONSTITUTION:The revolution signal of a spindle motor is transmitted to a speed control circuit 6 and a phase control circuit 4. Since an N frequency dividing circuit 2a is in the state of locking on rise, an output Vf from the speed control circuit 6 is output as a control signal. When the output Vf from the speed control circuit 6 becomes equalized to a signal Vc at the time of stationary revolution, a changeover circuit 11 outputs the signal Vc as a control signal. The locking or the N frequency dividing circuit 2a is released simultaneously. When an output Vp from the phase control circuit 4 becomes equalized to Vc, the output Vp from the phase control circuit 4 is output as a control signal.

Description

DETAILED DESCRIPTION OF THE INVENTION [Object of the Invention] (Industrial Application Field) The present invention relates to a rotational speed control device for a magnetic disk for recording or reproducing information, for example.

(Prior Art) Conventionally, this type of magnetic disk device rotates a disk-shaped magnetic disk at high speed with a spindle motor, and tracks concentrically formed on the surface of this high-speed rotating magnetic disk. By approaching and driving a magnetic head as a recording/reproducing means, information is recorded on the track and information recorded on the track is reproduced.

In such a magnetic disk device, the rotation speed of the spindle motor that rotates the magnetic disk is controlled by, for example, the fourth motor.
This is performed by a rotation speed control circuit using a PLL circuit (phase locked loop circuit) as shown in FIGS.

In FIG. 4, reference oscillator 1 is composed of, for example, a crystal oscillator, and generates an accurate reference clock CK. This reference clock CK is supplied to the N frequency divider circuit 2. The N frequency divider circuit 2 divides the frequency of the reference clock CK to generate an N frequency divided reference clock NCR. This N-divided reference clock NCK is supplied to one input of the phase control circuit 4. 3 is a rotational speed detector which outputs a frequency signal FRQ according to the rotational speed of a spindle motor (not shown). This frequency signal FRQ is supplied to the other input of the phase control circuit 4. Reference numeral 4 denotes a phase control circuit (APC) using a digital PLL, which inputs the N-divided reference clock NCR and the frequency signal FRQ, and outputs a voltage signal Vp according to the phase difference between them as a digital value. The voltage signal Vp output from the phase control circuit 4 is converted into an analog signal by a D/A converter 5, and is supplied to a spindle motor (not shown) as a rotational speed control signal Ep. The spindle motor is accelerated or decelerated by this rotational speed control signal Ep, and is controlled to keep the rotational speed constant.

FIG. 7 shows how the rotational speed changes when the spindle motor is started up by the rotational speed control circuit shown in FIG. 4 above. As is clear from the figure, once steady rotation is reached, the rotational speed fluctuates little and a stable rotational speed can be obtained, but it has the disadvantage that it takes a long time to rise until steady rotation is reached.

On the other hand, FIG. 5 shows a circuit in which a speed control circuit is used in place of the phase control circuit 4 shown in FIG. 4 to control the rotational speed of a spindle motor. Components that are the same as those in FIG. 4 are given the same reference numerals and explanations will be omitted.

In the figure, 6 is a speed control circuit (AFC) using a digital PLL.
) inputs the N-divided reference clock NCK and the frequency signal FRQ, and outputs a voltage signal vf as a digital value according to the frequency difference between them. The voltage signal Vf output from the speed control circuit 6 is converted into an analog signal by the D/A converter 7, and the rotation speed control signal Ep
It is designed to be supplied to a spindle motor (not shown). The spindle motor is accelerated or decelerated by this rotational speed control signal Ep, and is controlled to keep the rotational speed constant.

FIG. 8 shows how the rotational speed changes when the spindle motor is started up by the rotational speed control circuit shown in FIG. 5 above. As is clear from the figure, although the start-up time until steady rotation is reached is short, the rotation speed fluctuates greatly after steady rotation is reached, and the rotation speed is unstable.

The circuit shown in FIG. 6 has been proposed to eliminate the drawbacks of the rotational speed control circuits shown in FIGS. 4 and 5. That is, the startup characteristics of the speed control circuit 6,
This system takes advantage of both the stability of the rotation speed during steady rotation of the phase control circuit 4, and controls the rotation speed of the spindle motor by switching and driving the speed control circuit 6 and the phase control circuit 4. be.

In FIG. 6, parts that are the same as those shown in FIGS. 4 and 5 are given the same reference numerals, and their explanations will be omitted. Addition circuit 8
, which adds the analog signals output from the D/A converters 5 and 7 and outputs it as the rotation speed control signal Ep.
'p controls the rotation speed to be kept constant. Also,
Lock range detection signal L output from speed control circuit 6
K is a signal indicating that the frequency signal FRQ output from the rotational speed detector 3 has entered the lock range, and this causes a switch from speed control to phase control.

However, in controlling the rotation speed of the spindle motor using the rotation speed control signal Ep output from the rotation speed control circuit shown in FIG. 6, as shown in FIG. Although this method has excellent performance, it has the disadvantage that there is a large disturbance in the rotational speed when switching from the speed control to the phase control.

(Problem to be Solved by the Invention) As described above, this invention has a problem in that, as described above, the startup time is long in the case where the rotation speed of the spindle motor is controlled by the phase control circuit. The spindle motor's rotation speed is unstable during steady rotation, and the spindle motor's rotation speed is controlled by switching the phase control circuit and speed control circuit. This was done to eliminate the disadvantage of large turbulence, and reduce the start-up time until the spindle motor reaches steady rotation, and
It is an object of the present invention to provide a rotational speed control device for a magnetic disk that can obtain a stable rotational speed with little fluctuation in the rotational speed immediately after reaching steady rotation.

[Structure of the Invention] (Means for Solving the Problems) In order to achieve the above object, a magnetic disk rotation speed control device of the present invention includes a rotation speed detection system that detects the rotation speed of a spindle motor that rotates a magnetic disk. a speed control circuit that outputs a frequency difference signal between the output signal of the rotation speed detector and a first clock signal of a predetermined frequency; and a speed control circuit that outputs a frequency difference signal between the output signal of the rotation speed detector and a second clock signal of a predetermined frequency. a phase control circuit that outputs a phase difference signal from the speed control circuit; a storage means that stores a voltage signal to be supplied to the spindle motor during steady rotation of the spindle motor; and a storage means that stores the frequency difference signal from the speed control circuit. outputs the frequency difference signal while the voltage signal is less than the voltage signal stored in the voltage signal;
The voltage signal is output when the frequency difference signal from the speed control circuit becomes equal to the voltage signal stored in the storage means, and the phase difference signal from the phase control circuit is stored in the storage means. a switching circuit that switches and outputs the phase difference signal when the voltage signal becomes equal to a voltage signal; and a rotation speed control means that controls the rotation speed by supplying an output signal of the switching circuit to the spindle motor. It is characterized by what it did.

(Function) This invention controls the rotation speed by a speed control circuit when starting up the spindle motor, and after reaching steady rotation, controls the rotation speed by a phase control circuit, and shifts from the above startup to steady rotation. The rotational speed is controlled by a voltage signal stored in a storage means. As a result, the start-up time of the spindle motor is short, a stable rotational speed is obtained during steady rotation, and a smooth transition from start-up to steady rotation can be achieved.

(Example) Hereinafter, an example of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing the main parts of a spindle motor rotation speed control circuit according to the present invention.

In the figure, reference oscillator 1 is constructed of, for example, crystal oscillation and generates an accurate reference clock CK, as in the conventional example.

This reference clock CK is supplied to N frequency divider circuits 2a and 2b. The lock state of the N frequency divider circuit 2a is released by a reset signal R8TB outputted from the shift circuit]2, which will be described later, and the N frequency divider circuit 2a switches the reference clock CK to N.
A frequency-divided n-shift N-divided reference clock (second clock signal of a predetermined frequency) is generated. This n-shifted N-divided reference clock is supplied to one input of the phase control circuit 4. In addition, the N frequency dividing circuit 2b
generates an N-divided reference clock NCK (a first clock signal of a predetermined frequency) obtained by dividing the reference clock CK by N. This N-divided reference clock NCK is
The signal is supplied to one input of the speed control circuit 6.

3 is a rotation speed detector similar to that shown in the conventional example, which outputs a frequency signal F corresponding to the rotation speed of a spindle motor (not shown).
It outputs RQ. This frequency signal FRQ is
The signal is supplied to the other input of the phase control circuit 4 and the speed control circuit 6, respectively. 4 is digital PLL
The above N frequency dividing circuit 2a is a phase control circuit (APC) according to
It outputs the n-shifted N-divided reference clock and the rotational speed structure as digital values. The voltage signal Vp output from this phase control circuit 4 is applied to a switching circuit 1 which will be described later.
1.

6 is a speed control circuit (AFC) using a digital PLL,
The frequency is the N-divided reference clock NCK from the N-divided circuit 2b and the frequency from the rotation speed detector 3.

The voltage signal Vf output from the speed control circuit 6 is also supplied to a switching circuit 11, which will be described later.

A memory (storage means) 10 stores a voltage value (voltage signal) Vc that is a condition for switching from the speed control system to the phase control system. This voltage value Vc is the same voltage as the voltage that should be applied to the spindle motor as a rotational speed control signal when the spindle motor is in steady rotation. The voltage signal Vc from this memory 10 is supplied to a switching circuit]1.

The switching circuit 11 is composed of a comparison circuit, a switch circuit, etc., and in an initial state, the voltage signal Vf from the speed control circuit 6 is applied to its output terminal.

Then, the voltage signal Vc from the memory 10 and the voltage signal Vf from the speed control circuit 6 are compared, and when these two pressure signals Vc and Vf become equal, the reset signal R is
3TA, and also outputs the voltage signal Vc from the memory 10 in place of the voltage signal Vf from the speed control circuit 6. Furthermore, the voltage signal Vc from the memory 10 and the output signal Vp from the phase control circuit 4 are also compared, and when these two pressure signals Vc and Vp become equal, the voltage signal from the memory 10 is The voltage signal Vp from the phase control circuit 4 is output in place of Vc]2.

The shift circuit 2 shifts the reset signal R8TA outputted from the switching circuit 11 by an amount corresponding to the low clock of the reference clock CK and outputs it as a reset signal RSTB. The value n that defines the number of shifts is stored in advance in a table built into the control circuit 13.

The control circuit (rotational speed control means) 13 stores a table including a value n that defines the number of shifts of the shift circuit 2 described above, and also stores the memory 10, the switching circuit 11, and the shift circuit 1.
This controls the operations of the second class. A control signal output by this control circuit is shown by a dotted line.

Further, the D/A converter (rotation speed control means) 14 converts the rotation speed control signal outputted by the switching circuit 11 as a digital value into an analog signal, and the spindle motor
The rotation speed is controlled to be kept constant by the rotation speed control signal Ep output from the D/A converter 14.

Next, the operation of the above configuration will be explained with reference to the timing chart of FIG. First, when a command to start a spindle motor (not shown) is issued, rotation of the spindle motor is started and the number of rotations is gradually increased. The rotational speed of the spindle motor is detected by a rotational speed detector 3 and supplied to a speed control circuit 6 and a phase control circuit 4 as a frequency signal FRQ. On the other hand, the reference oscillator 1 is in an oscillating state, and as shown in FIG. 2(a), the reference clock CK
is occurring. This reference clock CK is N
N is supplied to the frequency dividing circuit 2b, as shown in FIG.
A frequency-divided N-frequency reference clock NCR is generated.

However, since the N frequency divider circuit 2a is in a locked state by the reset signal R8TB, it does not operate even if the reference clock CK is supplied. By supplying the N-divided reference tarlock NCK and the frequency signal FRQ to the speed control circuit 6, a voltage signal Vf corresponding to the frequency difference is output. At this time, the switching circuit 11 is switched by a control signal from the control circuit 13 so as to output the voltage signal Vf as it is, so that the voltage signal Vf is converted into an analog signal by the D/A converter 4 as it is. It is converted and supplied to the spindle motor to control the rotation speed of the spindle motor.

In this way, when starting up the spindle motor, PLL control is performed using the speed control circuit 6, so that sharp start-up characteristics can be obtained, as explained in the conventional example shown in FIG. .

On the other hand, in the switching circuit 11, in parallel with the above operation, the voltage signal Vf from the speed control circuit 6 and the memory 10
It is in a state where it is being compared with the voltage signal Vc stored in the. Then, the voltage signal Vf and the voltage signal Vc become equal, that is, the voltage signal V from the speed control circuit 6
When f reaches the voltage indicated during steady rotation, the switching circuit 11
The voltage signal Vc from the memory 10 is output in place of the voltage signal Vf currently being output. This prevents the rotational speed of the spindle motor from changing significantly.

Further, when the voltage signal Vf and the voltage signal Vc become equal, the switching circuit 11 outputs a reset signal R8TA as shown in FIG. 2(C). This reset signal R8TA
is input to the shift circuit 12, and a shift corresponding to n reference clocks CK is performed by a control signal from the control circuit 13.

Then, as shown in FIG. 2(d), the reset signal R3
It is output as TB. This reset signal R8TB is N
By being supplied to the frequency dividing circuit 2a, the N frequency dividing circuit 2a
Then, an n-shifted N-divided reference clock obtained by frequency-dividing the reference clock CK by N is outputted and supplied to the phase control circuit 4.

The above shift is to shift the N-divided reference clock output from the N-divided circuit 2a so that the voltage signal Vc from the memory 10 and the voltage signal Vp output from the phase control circuit 4 have the same voltage value. , the number of shifts (time) is calculated in advance and stored in the table of the control circuit 13 as the number of shift clocks n. Then, when the reset signal R8TA is output from the switching circuit 11, the contents of this table are referred to, and based on the contents, the reset signal R3TA is shifted by n clocks and is supplied as the reset signal R3TB to the N frequency divider circuit 2a. In the N frequency divider circuit 2a, the locked state is released by the reset signal R3TB, and the n shift N frequency divided reference clock is output.

Next, when the voltage signal Vp output by the phase control circuit 4 becomes equal to the voltage signal Vc, that is, when the output from the N frequency divider circuit 2a starts, the output of the switching circuit 1 changes from the current output. The phase control circuit 4 outputs the voltage signal Vp in place of the voltage signal Vc. The output signal from this switching circuit 11 is converted into an analog signal by a D/A converter 14, and is used as a rotation speed control signal Ep of the spindle motor.

As described above, when starting up the spindle motor, the rotation speed is controlled by PLL control using the speed control circuit 6, and when switching to phase control, the same voltage signal Vc as the voltage value supplied during steady rotation is used. [7] Since the rotation speed is controlled by PLL control using a phase control circuit], as shown in Fig. 3, the startup time for the spindle motor rotation speed is short, and There is little variation in the rotational speed during steady rotation, and furthermore, it is possible to smoothly transition from startup to steady rotation.

Although the above embodiment describes a spindle motor that rotationally drives a magnetic disk, it can be similarly applied to controlling the rotation speed of a motor that rotationally drives an optical disk or a compact disk, and the same effects as in the above embodiment can be achieved. .

[Effects of the Invention] As detailed above, according to the present invention, the start-up time for the spindle motor to reach steady rotation is reduced, and immediately after the spindle motor reaches steady rotation, fluctuations in the rotation speed are small and stable. Accordingly, it is possible to provide a rotation speed control device for a magnetic disk that can obtain a rotation speed that is as follows.

[Brief explanation of the drawing]

1 to 3 show an embodiment of the present invention, in which FIG. 1 is a block diagram showing a schematic configuration of a rotation speed control circuit, FIG. 2 is a timing chart for explaining the operation,
FIG. 3 is a diagram showing the rotation speed characteristics of a spindle motor, and FIGS. 4 to 9 show conventional rotation speed control circuits. FIG. 4 is a block diagram of a PLL circuit using phase control, and FIG. Figure 6 is a block diagram of a PLL circuit using speed control, Figure 6 is a block diagram of a PLL circuit using both phase control and speed control, Figure 7 is a diagram showing the rotation speed characteristics of a spindle motor in a PLL circuit using phase control, FIG. 8 is a diagram showing the rotation speed characteristics of a spindle motor in a PLL circuit using speed control, and FIG. 9 is a diagram showing the rotation speed characteristics of a spindle motor in a PLL circuit using both phase control and speed control. 1... Reference oscillator, 2a, 2b... N frequency dividing circuit, 3
...Rotation speed detector, 4...Phase control circuit (APC)
, 6... Speed control circuit (AFC), 10... Memory (storage means), 11... Switching circuit, 12... Shift circuit, 13... Control circuit (rotation speed control means), 14...
...D/A converter (rotation speed control means). Applicant's representative Patent attorney Takehiko Suzue

Claims (1)

[Claims] A rotation speed detector that detects the rotation speed of a spindle motor that rotates a magnetic disk, and a frequency difference signal between an output signal of the rotation speed detector and a first clock signal having a predetermined frequency. a speed control circuit; a phase control circuit that outputs a phase difference signal between the output signal of the rotation speed detector and a second clock signal of a predetermined frequency; storage means for storing a voltage signal; outputting the frequency difference signal while the frequency difference signal from the speed control circuit is less than the voltage signal stored in the storage means; Outputting the voltage signal when the signal becomes equal to the voltage signal stored in the storage means, and outputting the voltage signal when the phase difference signal from the phase control circuit becomes equal to the voltage signal stored in the storage means. a switching circuit that switches and outputs the phase difference signal, and a rotation speed control means that controls the rotation speed by supplying an output signal of the switching circuit to the spindle motor. Disc rotation speed control device.