JPH1065659A - Pll circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To enlarge a locking range, to prevent pseudo locking and to output digital data at an arbitrary transfer rate in a PLL(phased locked loop) circuit used in a digital signal recording/reproducing device or the like. SOLUTION: The PLL circuit basically comprises a first phase loop comprising PFD(phase frequency detector) 11, LPF 12, an error addition circuit 13, VCO(voltage control oscillator) 14 and a frequency divider 15 and a second phase loop comprising PFD 17, LPF 18, an error addition circuit 13, VCO 14 and a frequency divider 15. The oscillation frequency of VCVCO 14 is pulled into a system clock by the second phase loop. Thus, the generation of pseudo locking can be prevented even if the locking range of VCO 14 is taken to be wide, and the transfer rate of digital data can arbitrarily be changed in accordance with the switch of the system clock.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a PLL circuit for generating a clock synchronized with a digital modulation signal, and more particularly to a PLL for transferring digital data at an arbitrary transfer rate or transferring or recording / reproducing a digital signal for recording / reproducing. Circuit.

[0002]

2. Description of the Related Art Conventionally, as a device provided with a PLL circuit for generating a clock synchronized with a digital modulation signal, a digital signal transfer device or a recording / reproducing device for transferring or recording / reproducing digital data at an arbitrary transfer rate is known. is there. Among them, as a digital signal recording / reproducing device, there is a helical recording type digital data recorder using a rotating drum. And as this digital data recorder, ANSI (American National Stand
It is known that high-speed transmission rates and large-capacity data conforming to the ID-1 format of the Ards Institute are playing an active role in measurement fields such as science and national defense around the world.

In the ID-1 format, only the contents of recording data to be left on the magnetic tape and the footprint (for example, track length, track width, track angle, recording wavelength, etc.) of the magnetic tape are specified. That is,
Unlike a normal VTR, the frequency (transfer rate) and relative speed of recording data are not specified.

[0004] Therefore, data can be recorded on a tape conforming to the ID-1 format at any transfer rate, and conversely, any data transfer from the tape conforming to the ID-1 format can be performed. Data can be read at the rate.

A system utilizing the characteristics of the digital data recorder conforming to the ID-1 format will be described with reference to an example. A first example is a case where data having a high transfer rate generated in real time must be recorded, such as an artificial satellite system, a survey for industrial purposes, and data collection. After recording this data in real time,
When analyzing this data using a processor or an analyzer having a low processing speed, such as a computer, it is necessary to reproduce the data at the same transfer rate for these machines. It is used for data rate conversion in such a case.

[0006] The second example is astronomical observation and the like. When long-term observation data over a 24-hour period is recorded and analyzed, if this data is reproduced in real time, it is inefficient and difficult to work. No. Therefore, it is necessary to reproduce these data at a transfer rate higher than that at the time of recording in accordance with the processing speed of a computer or the like.

As described above, in the digital data recorder used in the measurement field, recording is performed in real time in accordance with the input transfer rate during recording, and at the transfer rate in accordance with the transfer rate of the processor during reproduction. It is desired to be reproduced. Due to such a requirement, a general digital data recorder can realize not only the highest transfer rate that can be realized by the machine but also any lower transfer rate.

However, in a helical recording digital data recorder, it is difficult to actually realize an arbitrary transfer rate. At present, an arbitrary transfer rate is realized by a digital data recorder using a ring memory.

FIG. 3 is a diagram showing a functional configuration of a conventional digital data recorder using a ring memory. Here, data exchange between the recorder main body 30 of the digital data recorder and the outside is performed via a ring buffer 32. First, recording data from the outside is stored in a memory buffer (MB) 32b inside the ring buffer 32, and when a certain amount of data is stored, it is written into the ring memory 32a. At the same time, the memory buffer (MB) 3
2c starts reading data from the ring memory 32a. When the memory buffer 32c reads data, the data in the ring memory 32a decreases, but when the memory buffer 32c reads a certain amount of data, it overflows and cannot be read, so the data in the ring memory 32a increases.

When the data amount of the ring memory 32a reaches the read point (RP) 32d, a recording command is issued to the recorder body 30 by a controller (not shown). In response to this recording command, the recorder body 30
The data is recorded on the tape 31a of the cassette 31 by rotating the drum 30a having the magnetic head.

Since the recording transfer rate of the recorder body 30 is faster than the transfer rate of data input from the outside, the data in the ring memory 32a eventually decreases. When the data amount of the ring memory 32a reaches the write point (WP) 32e, a stop command is issued to the recorder body 30 by a controller (not shown). As a result, the recorder main body 30 stops recording data on the tape 31a, and the data amount is reduced to the read point 32.
Wait for d to be reached. Then, when the data amount reaches the read point 32d again, data recording on the tape 31a is started.

When the data from the tape 31a is reproduced and transferred to the outside, the opposite operation is performed. As described above, the stop interval of the recorder main body 30 is controlled by the ring memory 32a such that the start and stop of the recorder main body 30 are repeated and the transfer rate of the recorder main body 30 matches the transfer rate of the input / output data. Apparently, the transfer speed of the digital data recorder can be arbitrarily selected.

In the system shown in FIG. 3, since the start and stop of the recorder body 30 which can obtain a certain transfer rate are used repeatedly, the recorder body 3 is used.
The technology of 0 can use the technology of a normal digital data recorder. However, this system has a problem that a large amount of memory is required. Further, the tape 31a is easily damaged by repeated start and stop. Further, since the drum 30a is rotating even at the time of stop, there is a problem that the magnetic head and the tape 31a keep contact with each other, and the life of the head in actual use time is shortened.

Therefore, there is a system which does not require a memory, does not damage the tape, and the life of the magnetic head is based on the actual use time. FIG. 4 is a diagram showing a functional configuration of a conventional digital data recorder which does not require a memory. In this system, the controller 42 sends a control command to the recorder main body 40 in accordance with the transfer rate of data input / output from the outside, and the rotation speed of the drum 40a and the cassette 4
The feed speed of one tape 41a is changed in a one-to-one relationship. Thus, the transfer rate of the digital data recorder can be arbitrarily selected.

However, in order to realize a digital data recorder as shown in FIG. 4, various techniques are required. For this reason, there is no digital data recorder currently used all over the world that can select an arbitrary transfer rate, and in fact, it is 1 / N of the highest transfer rate of the digital data recorder. The selection is discontinuous (step). For this 1 / N step selection, a PLL (Phase Locked Loop) circuit is used.

FIG. 5 is a block diagram showing a schematic configuration of a conventional PLL circuit for performing 1 / N step selection. This P
The LL circuit includes a normal PFD (Phase Frequency Detector) 51 and an LPF to cope with a plurality of transfer rates.
(Low Pass Filter) 52 and VCO (Voltage Controlle
In addition to the configuration with the d oscillator 53, a frequency divider 54 is provided after the output of the VCO 53.

The PFD 51 compares the phase of the reproduced digital signal from the tape with the phase of the reproduced clock of the frequency divider 54, and sends a voltage value corresponding to the phase error to the LPF 52. The LPF 52 integrates a voltage corresponding to the phase error and sends it to the VCO 53 as a control voltage.
The VCO 53 outputs a reproduced clock at an oscillation frequency according to the control voltage.

The frequency divider 54 operates according to a frequency division ratio of 1/1 to 1 / N (N is an integer) instructed by the frequency detector 55.
The reproduction clock from the CO 53 is divided and output. To the frequency detector 55, a system clock generated by an external reference signal or the like so as to be the same as the target frequency of the reproduction clock is input. The frequency detector 55 controls the frequency division ratio 1/1 to 1 / N of the frequency divider 54 based on the frequency ratio between the system clock and the reproduced digital signal.

The frequency division ratio may be controlled by a mode selection signal or the like from the system controller. The system controller outputs a mode selection signal based on a calculation or a manual command.

[0020]

However, in the PLL circuit shown in FIG. 5, the range in which the PLL circuit operates accurately (lock range) is 1/1 to the center oscillation frequency of the VCO 53.
1 / N ± 1 to 2%. The reason is that pseudo lock due to side buds of a digital reproduction signal modulated with random digital data becomes a problem.
This is because the range of the oscillation frequency of No. 3 or the lock range of the PLL circuit must be kept within a range where pseudo lock does not occur.

Here, the pseudo lock will be described. First, a digital reproduction signal has a plurality of spectra because it is modulated with digital data that changes at random. Originally, the PLL circuit is a circuit that extracts phase information of a predetermined spectrum from the plurality of spectra and generates a clock synchronized with the digital reproduction signal, but expands the oscillation frequency range of the VCO 53 or the lock range of the PLL circuit. Then, a lock synchronized with a spectrum other than the predetermined spectrum may be generated. This is called a pseudo lock.

As a means for preventing the pseudo lock, there is a method of increasing the frequency division ratio of the frequency divider 54 so that the number of steps is within a few% of a range in which the pseudo lock does not occur. The clock frequency must be several tens of times the required clock frequency, and it is difficult to realize a digital data recorder with a high transfer rate requiring a system clock close to 100 MHz.

The present invention has been made in view of such a point, and an object of the present invention is to provide a PLL circuit which does not cause a pseudo lock even if the range of the oscillation frequency of the VCO or the lock range of the PLL is expanded.

[0024]

According to the present invention, in order to solve the above-mentioned problems, a PLL (Phase Lo) for generating a clock from a digitally modulated signal modulated by a digital signal is provided.
In a cked Loop) circuit, a first phase comparator that compares the phase of the digital modulation signal with the oscillation clock of a VCO (Voltage Controlled Oscillator), and compares the phase of a continuous system clock with the oscillation clock of the VCO. A second phase comparator, an adder that adds the phase error of the first phase comparator and the phase error of the second phase comparator, and feeds back the added phase error to the VCO; PL characterized by having
An L circuit is provided.

In such a PLL circuit, the first phase comparator compares the phase of the digital modulation signal with the oscillation clock of the VCO, and the second phase comparator compares the continuous system clock and the oscillation clock of the VCO. And the phase is compared. Then, the adder adds the phase error of the first phase comparator and the phase error of the second phase comparator, and feeds back the added phase error to the VCO. As a result, VC near the frequency of the continuous system clock
The output frequency of O is pulled in, preventing false locking of the random digitally modulated signal.

[0026]

DESCRIPTION OF THE PREFERRED EMBODIMENTS One embodiment of the present invention will be described below with reference to the drawings. FIG. 2 is a block diagram showing a schematic configuration of a reproduction system of the digital data recorder of the present embodiment. The digital data recorded on the tape 1 is reproduced by a magnetic head (not shown) on the drum 2,
The signal is amplified by the preamplifier 3, waveform-equivalent by the equalizer 4, and sent to the PLL circuit 5 of this embodiment and the serial / parallel converter (S / P Conv) 6.

The PLL circuit 5 generates a reproduction clock following the jitter from the reproduction data including the jitter received in the recording and reproduction of the digital data recorder by a configuration described later, and converts the reproduction clock into a serial-parallel converter 6. A 9-8 demodulator (9/8 DEC) 7 and a memory 8 are sent.

The serial / parallel converter 6 converts the digital data from the equalizer 4 into serial / parallel at the timing of the clock supplied from the PLL circuit 5. The serial / parallel-converted digital data is demodulated by the 9-8 demodulator 7 and written into the memory 8. The digital data written in the memory 8 is read out with a stable system clock generated by the PLL circuit 9 based on the reference clock,
The error is corrected by a CC (Error Checking and Correcting) 10 and output.

FIG. 1 is a block diagram showing a schematic configuration of the PLL circuit 5 of the present embodiment. This PLL circuit basically consists of
PFD (Phase Frequency Detector) 11 and LPF (Low
Pass Filter) 12, error adding circuit 13, VCO
(Voltage Controlled Oscillator) 14 and frequency divider 15
And a PFD (PhaseFr
equency Detector) 17 and LPF (Low Pass Filter)
18, an error adding circuit 13, a VCO 14, and a second phase loop formed by the frequency divider 15.

The PFD 11 compares the phase of the reproduced digital signal from the tape with the phase of the reproduced clock of the frequency divider 15, and sends a voltage corresponding to the phase error to the LPF 12. The LPF 12 integrates a voltage corresponding to the phase error, and sends it to the error adding circuit 13. Where LPF
12, the cutoff frequency is set relatively high, so that the first phase loop has a high gain.

The error adding circuit 13 adds the phase error from the LPF 18 of the second phase loop to the phase error from the LPF 12, and uses this as a control voltage to obtain V
Send to CO14.

The VCO 14 outputs a reproduced clock at an oscillation frequency according to the control voltage. The frequency divider 15
The division ratio (1 / 1-1 / 1/1) commanded by the frequency detector 16
N), the reproduced clock from the VCO 14 is divided and output. A continuous system clock generated by an external reference signal or the like so as to have the same frequency as the target frequency of the reproduction clock is input to the frequency detector 16. The frequency detector 16 divides the frequency of the frequency divider 15 from 1/1 to 1 / N (N is an integer) based on a frequency ratio between the frequency of the system clock and a preset lock frequency of the VCO 14.
Control.

The frequency division ratio may be controlled by a mode selection signal or the like from the system controller. The system controller outputs a mode selection signal based on a calculation or a manual command.

On the other hand, the PFD 17, which is a component of the second phase loop, compares the phase of the continuous system clock with the phase of the reproduced clock, and sends a voltage value corresponding to the phase error to the LPF 18. The LPF 18 integrates a voltage corresponding to the phase error and sends the integrated voltage to the error adding circuit 13. Here, the cutoff frequency of the LPF 18 is set close to DC and has a low gain.
Is set to have a much slower response speed than the first phase loop.

In such a PLL circuit, first, in the first phase loop, the frequency divider 15 sets the oscillation frequency of the VCO 14 to any one of 1/1 to 1 / N so that the oscillation frequency becomes close to the system clock. The frequency is divided and output as a reproduction clock. This reproduced clock is also input to the PFD 11. The PFD 11 calculates a phase error between the input reproduced clock and the reproduced digital data. Thereafter, in the first phase loop, the above operation is repeated,
The reproduced clock approaches 1 / N in width to the fluctuation of the frequency and phase of the reproduced digital data due to tape expansion, vibration, servo jitter, and the like.

On the other hand, in the second phase loop, the phase error between the system clock and the reproduced clock is added to the error adding circuit 13. As a result, the oscillation frequency of the VCO 14 changes in a direction approaching the system clock.

As described above, in the present embodiment, the VCO 14 is controlled by the second phase loop in addition to the normal first phase loop.
Oscillating frequency is pulled close to the frequency of the system clock, so that even if the lock range of the VCO 14 is widened, it is possible to prevent the occurrence of pseudo-locking of random reproduced digital data. Thus, the transfer rate of digital data can be arbitrarily changed.

The lock range of the VCO 14 is set to ± 3d
If the frequency is set to B (decibel) or more, the phase can be locked at any frequency. The PL of the present embodiment
In order for the L circuit to work effectively, the relationship between the reproduced digital data and the system clock must be in an integer ratio relationship. However, since the tape reproduction is originally synchronized with the system clock, there is no actual problem.

[0039]

As described above, according to the present invention, the first phase comparator compares the phase of the digital modulation signal with the oscillation clock of the VCO, and the second phase comparator compares the phase of the oscillation clock of the VCO.
The phase of the continuous system clock is compared with the phase of the oscillation clock of the VCO, the phase error of the first phase comparator and the phase error of the second phase comparator are added, and the added phase error is sent to the VCO. Since feedback is used, V is set near the frequency of the continuous system clock.
The output frequency of the CO can be pulled in, the pseudo lock of the random digital modulation signal can be prevented, and the lock range can be extended.

The transfer rate can be arbitrarily changed according to the switching of the system clock.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a schematic configuration of a PLL circuit according to an embodiment.

FIG. 2 is a block diagram showing a schematic configuration of a digital data recorder playback system of the present embodiment.

FIG. 3 is a diagram showing a functional configuration of a conventional digital data recorder using a ring memory.

FIG. 4 is a diagram showing a functional configuration of a conventional digital data recorder which does not require a memory.

FIG. 5 is a block diagram illustrating a schematic configuration of a conventional PLL circuit that performs 1 / N step selection.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... Tape, 2 ... Drum, 5 ... PLL circuit, 11 ... PFD (Phase Frequency Detector), 1
2: LPF (Low Pass Filter), 13: Error adding circuit, 14: VCO (Voltage Controlled Osci)
llator), 15: frequency divider, 16: frequency detector, 17: PFD, 18: LPF.

 ────────────────────────────────────────────────── ─── Continued on the front page (72) Inventor Shuji Tsunashima 6-7-35 Kita Shinagawa, Shinagawa-ku, Tokyo Inside Sony Corporation

Claims (4)

[Claims] 1. A PLL (Phase Lo) for generating a clock from a digitally modulated signal modulated by a digital signal.
cked Loop) circuit, the digital modulation signal and VCO (Voltage Controlled)
Oscillator), a first phase comparator for comparing the phase with the oscillation clock of the VCO, a second phase comparator for comparing the phase of the continuous system clock with the phase of the oscillation clock of the VCO, and the first phase comparator. And an adder that adds the phase error of the second phase comparator and the phase error of the second phase comparator, and feeds back the added phase error to the VCO. 2. The first phase comparator is configured to compare the phase of an oscillation clock of the VCO divided by N (N is an integer) by a frequency divider with the digital modulation signal. 2. The PLL circuit according to claim 1, wherein the second phase comparator is configured to compare the phase of the oscillation clock divided by N with the system clock. 3. The PLL circuit according to claim 2, further comprising a frequency detector that counts a frequency of the system clock and switches a frequency division ratio of the frequency divider according to the count value. 4. The PL according to claim 2, wherein said frequency division ratio of said frequency divider is switched by a selection signal from a system controller.
L circuit.