JP2003281812A - Disk rotation control device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a disk rotation control device which can promptly make return to a predetermined rotational velocity range when rotation velocity deviates largely from a controllable predetermined rotational velocity range in the CLV (constant linear velocity) control of a disk based on a reproducing signal. <P>SOLUTION: The disk rotation control device includes a PLL circuit 53 generating a synchronized signal with the reproducing signal of the disk, and an underflow detector 76 and an overflow detector 80 which detect the level of the velocity error signal of a control system at the time that the constant linear velocity control of the disk is carried out on the basis of the synchronized signal. An acceleration signal which accelerates the disk is given in the case that the level is below the predetermined range. A decelerating signal which decelerates the disk is applied to a control system in the case of more than the range. <P>COPYRIGHT: (C)2004,JPO

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a disk rotation control device, and more particularly to a spindle motor drive control circuit for an optical disk or the like.

[0002]

2. Description of the Related Art A digital signal is a constant linear velocity method (CL
When tracking is performed by an optical pickup on a disc recorded in V), the disc is driven so that its rotation speed decreases as the optical pickup moves from the inner peripheral portion to the outer peripheral portion of the disc. The rotation speed is controlled by rotating the spindle motor so that the frequency of the synchronous clock (clock generated based on the reproduction signal in the phase-locked loop circuit) synchronized with the reproduction signal reproduced from the disk becomes a predetermined frequency. It is done so as to control the speed. Hereinafter, a DVD device will be described as an example.

First, FIG. 10 is a block diagram of a circuit for controlling a spindle motor in a DVD apparatus. In the figure, 1 is a disc, 2 is an optical pickup,
3 is a spindle motor, 4 is a drive amplifier for the spindle motor, 5 is an analog signal processing circuit for equalizing the reproduced signal, 6 is a circuit for digitally processing the reproduced signal, 7 is a PLL circuit, 8 is a frequency comparator, and 9 is a phase. Comparator, 10
Is a calculator, and 11 is a PWM signal generation circuit.

Next, the operation will be described. Disk 1
Is started by the amplifier 4 and the reproduction signal is read by the optical pickup 2, the analog signal processing circuit 5
Waveform equalization at. The data in the reproduced signal is processed by the digital signal processing circuit 6 and output. At this time, the sync signal recorded at a predetermined interval in the reproduction signal is also extracted. The PLL circuit 7 is composed of a phase locked loop circuit, and a channel clock (a data reading synchronous clock synchronized with the reproduction signal) is generated from the reproduction signal.

The channel clock is input to the next frequency comparator 8. On the other hand, in the DVD apparatus, the center frequency of the channel clock when the disc 1 is rotated at a constant linear velocity is 26.16 MHz, so that the clock of this frequency is also supplied as a reference clock to the frequency comparator 8 by the crystal oscillator or the like. The frequency comparator 8 compares the frequencies of the channel clock extracted from the PLL circuit 7 and the reference clock, and outputs the error component as a frequency error signal.

By the way, the phase comparator 9 is supplied with a reference clock of 26.16 MHz by a crystal oscillator or the like as in the case of the frequency comparator 8, and this is divided by the amount corresponding to the recording interval of the synchronizing signal. The cycle of the circulated clock is equal to the cycle of the synchronizing signal when the disk 1 is rotating at a constant linear velocity). Then, the frequency-divided clock and the clock generated from the synchronizing signal are compared in phase and output as a phase error signal.

Both the frequency error signal and the phase error signal are input to the computing unit 10, multiplied by a real number, gain adjusted, and then added and output. This calculator 10
The error signal output of is input to the PWM signal generation circuit 11,
PWM (Pulse Wide Modulation) conversion is applied to the amplifier 4. Spindle motor 3 to cancel the error signal PWM output by amplifier 4
Since the number of rotations is controlled, the disk 1 rotates at a constant linear velocity.

[0008]

DISCLOSURE OF THE INVENTION Problems to be Solved by the Invention
In the apparatus, the rotation control of the spindle motor 3 uses the CLV method with a constant linear velocity. However, unlike the CAV method in which the rotation speed is constant, the rotation speed of the disk 1 is greatly changed in a track jump other than the normal reproduction, for example, in the track jump from the inner circumference to the outer circumference or vice versa, and thus the linear velocity due to the inertia of the disk 1 or the like. It takes time to re-engage to a constant state and establish a signal-readable state. Therefore, if a signal is read by the CAV method to improve accessibility, this problem can be solved, but if a DVD signal recorded by the CLV method is read by the CAV method, the frequency of the reproduction signal increases toward the outer periphery, and the higher the speed, the higher the speed. Processing is required.

However, there is a limit to the access speed of the memory used for the storage circuit in the subsequent digital signal processing circuit 6 and the like, and the PLL circuit 7 also needs to have a wide band, and further, only low speed processing is performed in the inner circumference. Therefore, there is a limit to increase the rotation speed of the disc 1.

The present invention has been made in order to solve the above-mentioned problems, and the constant angle control is focused on improving the accessibility on the inner peripheral side of the disk, and the signal processing speed is restrained on the outer peripheral side. An object of the present invention is to obtain a disk rotation control device that switches the disk rotation control method to a constant linear velocity control that applies a load.

[0011]

DISCLOSURE OF THE INVENTION A disk rotation control device of the present invention uses a signal generating means for generating a signal synchronized with a reproduction signal of a disk, and the rotation of the disk by using the signal generated by the signal generating means. A constant linear velocity control, a detector for detecting whether or not the velocity error signal in the control means is below a predetermined value, and an acceleration for accelerating the disk when the velocity error signal is below a predetermined value. A signal is supplied to the control means, and an acceleration means for releasing the acceleration signal when the value is equal to or more than a predetermined value is provided.

Further, a signal generating means for generating a signal synchronized with the reproduction signal of the disc, a control means for controlling the rotation of the disc with a constant linear velocity using the signal generated by the signal generating means, and this control means. A detector for detecting whether or not the speed error signal at a predetermined value is greater than or equal to a predetermined value, and a deceleration signal for decelerating the disk when the speed error signal is at or above a predetermined value, and when the speed error signal is at or below a predetermined value. Is equipped with a deceleration means for releasing the deceleration signal.

Also, a signal generating means for generating a signal synchronized with the reproduction signal of the disk, a control means for controlling the rotation of the disk at a constant linear velocity using the signal generated by the signal generating means, and this control means. A first and second detector for detecting whether or not the speed error signal is less than a first predetermined value, and an acceleration signal for accelerating the disk to the control means when the speed error signal is less than a predetermined value. And an acceleration means and a deceleration means for giving a deceleration signal for decelerating the disk when it exceeds a predetermined value.

[0014]

In the disk rotation control device of the present invention, when the speed error signal is less than a predetermined value as a result of the detection by the detector, the acceleration means gives the control means an acceleration signal for accelerating the disk, When the speed error signal is equal to or higher than the predetermined value, the acceleration signal is released.

Further, as a result of the detection by the detector, when the speed error signal is equal to or more than the predetermined value, the deceleration means gives the control means a deceleration signal for decelerating the disk, and when the speed error signal is less than the predetermined value, the deceleration signal is given. Is released.

In addition, the result of the detection by the first detector,
When the speed error signal is less than or equal to a predetermined value, the acceleration means gives the control means an acceleration signal for accelerating the disk, and when the speed error signal is greater than or equal to the predetermined value, the acceleration signal is released, and the detection signal of the second detector is detected. As a result, when the speed error signal is equal to or greater than the predetermined value, the deceleration means gives the deceleration signal for decelerating the disk to the control means, and when the speed error signal is equal to or less than the predetermined value, the deceleration signal is canceled.

The present invention will be described below in detail with reference to the drawings showing the embodiments thereof. Embodiment 1. Figure 1
FIG. 1 is a block diagram showing an example of a disk rotation control device that is Embodiment 1 of the present invention. In the figure, 50 is a disk, 51 is an optical pickup, 52 is an analog signal processing circuit for equalizing a reproduction signal, 53 is a PLL circuit for generating a clock synchronized with reproduction data, and 54 is a digital signal processing circuit.

Further, 55 is a spindle motor, 56 is a pulse generator which outputs a plurality of pulses per one rotation of the spindle motor 55, 57 is a frequency comparator, 5
8 is a phase comparator, 59 is a frequency divider that divides the clock input by a crystal oscillator, etc., 60 is a calculator, 61 is a selector, 62 is a low-pass filter, 63 is a PWM signal generation circuit, and 64 is a spindle motor. It is an amplifier for driving.

Reference numeral 65 is a frequency comparator, 66 is a phase comparator, 67 is a frequency divider for dividing a clock input by a crystal oscillator or the like, 68 is a computing unit, and 69 is a predetermined input from an input terminal 72. It is a comparator that compares the value with the frequency measurement value output from the frequency comparator 65.

Next, the operation will be described. First, after initialization is performed, the disk 50 starts to rotate, and focus and track control in the optical pickup 51 is performed. Spindle control using the pulse generator 56 is as follows. Before starting, the frequency divider 59
When set to, the frequency division ratio M is, for example, the frequency f of a crystal oscillator or the like input to the frequency divider 59, the rotation speed n of the disk 50 at a predetermined speed, and the rotation speed per rotation of the disk 50 of the pulse generator. If the number of output pulses is k, it can be calculated by M = n / fk ........ (1).

Next, in the frequency comparator 57, the interval between the pulses input from the pulse generator 56 is measured using the crystal oscillator. If the disk 50 is rotating at a predetermined rotation speed, the frequency division ratio M and the frequency comparator 5
The frequency measurement values of 7 are equal, but if not, an error occurs. The frequency comparator 57 outputs an error value for the frequency division ratio M for each pulse. The phase comparator 58 compares the output signal of the frequency divider 59 with the output timing phase of the pulse output from the pulse generator. If the timing of the output pulse and the output signal of the frequency divider 59 are not in phase synchronization, the error is measured and output.

Next, both the frequency comparator 57 and the phase comparator 58 are input to the arithmetic unit 60, multiplied by a real number for gain adjustment, and then added. The output of the added error passes through the selector 61, is input to the PWM signal generation circuit 63, and is output after the error is PWM-modulated. This output is input to the low pass filter 62, and the high frequency component of the signal is removed. However, in FIG. 1, assuming that the low-pass filter 62 is an analog circuit, the PW
Although the signal is PWM-modulated by the M signal generation circuit 63 and then output, the low-pass filter 62 may be a digital filter. In this case, the PWM signal generation circuit 63 is not necessary (the operation of converting the error component into the time base fluctuation by the PWM modulation is performed by the digital filter).

Next, the output of the low pass filter 62 is input to the amplifier 64, and the spindle motor 55 is controlled so that the frequency and phase error components are canceled. The disk 50 is rotating at a predetermined number of revolutions in a state where there is no frequency and phase error, and the disk 50 is CAV (constant angular velocity) controlled by the above operation.

Next, when focus or track servo is applied and the reproduction signal can be read, the output signal of the optical pickup 51 is input to the analog signal processing circuit 52, where data equalization and binarization processing is performed, and the digital signal is digitally processed. After the synchronization signal is extracted by the signal processing circuit 54, signal processing such as error correction is performed. The equalized reproduction signal is input to the PLL circuit 53, and a clock phase-synchronized with the data is generated based on the synchronization signal. The phase-locked clock is input to the digital signal processing circuit 54 and used for reading data.

Next, the reproduced signal processed by the analog signal processing circuit 52 is input to the digital signal processing circuit 54. Next, a clock phase-locked with the reproduction signal is input from the PLL circuit 53 to the next frequency comparator 65 and is also used as a clock for extracting the reproduction data. On the other hand, the frequency divider 67 is supplied with a reference clock from a crystal oscillator or the like, divided into a predetermined frequency division ratio, and then supplied to the frequency comparator 65 as a reference clock, and the above-mentioned PL within one cycle of the reference clock is supplied.
The number of clocks of the input clock from the L circuit 53 is measured. This measured value is compared with a target value, that is, a measured value when the disk 50 is rotating at a constant linear velocity (a constant value if the linear velocity is constant), and the error is output as a frequency error signal.

Next, since the sync signal is recorded on the disk 50 at a constant interval of the reproduction signal, the digital signal processing circuit 54 divides the clock from the PLL circuit 53 to phase the sync signal. A synchronized synchronization clock (when the output clock of the PLL circuit 53 is in phase synchronization with the reproduction signal, that is, the synchronization signal) is output. This is also used in the digital signal processing circuit 54 as a reference signal for discriminating data. On the other hand, the frequency divider 67 divides the frequency of the clock output from the PLL circuit 53 by the amount corresponding to the frequency division ratio when the synchronous clock is generated, and outputs it as a phase error detection clock (frequency division). The frequency of the phase error detecting clock becomes equal to the frequency of the synchronous clock when the disk 50 rotates at a constant linear velocity). Then, the phase comparator 66 compares the output timing phases of the synchronous clock and the phase error detecting clock. If the phases are not synchronized, the error is measured and output as a phase error signal.

Both the frequency error signal and the phase error signal are input to the arithmetic unit 68, multiplied by a real number, gain adjusted, and then added and output. This calculator 68
Is output to the selector 61. Hereinafter, when the frequency and phase error output of the computing unit 68 is selected, this signal is input to the PWM signal generation circuit 63, and the disk 50 is subjected to CLV (constant linear velocity) control.

In the above operation, the disk 50 is CAV
If controlled, when the optical pickup 51 is moved from the inner circumference to the outer circumference or the opposite direction, it is not necessary to change the rotation speed of the disk 50, so that the PLL circuit 53 is also easily resynchronized after the movement and the accessibility is improved. . Therefore, on the inner peripheral side of the normal disk 50, the output of the arithmetic unit 60 is selected by the selector 61. However, on an optical disk such as a DVD or a CD recorded at a constant linear velocity, the frequency of the reproduction signal increases toward the outer circumference, and the frequency of the clock from the PLL circuit 53 also increases in synchronization with it.

Therefore, the measurement value measured by the frequency comparator 65 (which becomes larger toward the outer circumference during the CAV control).
And the predetermined value input from the input terminal 70 are compared by the comparator 69. Here, the predetermined value input from the input terminal 70 is, for example, the upper limit of the clock frequency at which the PLL circuit 53 can perform phase synchronization or the digital signal processing circuit 5
When operating at the upper limit of signal processing in 4,
The measured value is measured by the frequency comparator 65.

In the above, when the measured value measured by the frequency comparator 65 in the comparator 69 is equal to the predetermined value or the measured value measured by the frequency comparator 65 is larger, the selector 61 At, a signal for selecting the error amount of the arithmetic unit 68 is output, and the CLV control is performed. Therefore, since the increase of the reproduction signal frequency is stopped and controlled to a constant value due to the CLV control transition, the increase of the output clock of the PLL circuit 53 stops and the digital signal processing circuit 54 stops the increase of the signal processing speed. It takes.

In the above-described operation of the first embodiment, the comparator 69 controls the CAV on the inner peripheral side of the disk 50 with an emphasis on improving the accessibility, and on the outer peripheral side to suppress the increase in the signal processing speed. It is possible to perform appropriate disk control according to the playback position on the CLV control of.

The predetermined value input from the input terminal 70 is not limited to the limit value indicating the maximum processing speed, and CAV⇒CLV
Any value for migration is fine. As shown in FIG. 2, the limit value A
In case of point setting (solid line) and B point setting (dotted line),
CLV control on the outer circumference from each location, CAV on the inner circumference
Be in control. However, FIG. 2 shows the case where CAV control is performed at a processing speed of 1 × speed at the innermost circumference, and the maximum processing speed is n × speed.

Embodiment 2. 3 is a block diagram showing an example of a disk rotation control device according to a second embodiment of the present invention. In the figure, the same reference numerals as those in FIG. 1 indicate the same or corresponding portions, 71 is a comparator, 72 is an input terminal of a predetermined value, and 73 is a selector.

Next, the operation will be described. CLV when jumping the optical pickup 51 from the outer circumference to the inner circumference
If the control is continued, the rotation speed of the spindle motor 55 increases toward the inner circumference. Therefore, the pulse interval measurement value input from the pulse generator 56 (increased toward the inner circumference during CLV control) measured by the frequency comparator 57 and the predetermined value input from the input terminal 72 are compared. 7
Compared with 1. Here, the predetermined value is a value measured by the frequency comparator 57 when the spindle motor 55 rotates at a predetermined speed.

In the above, when the measured value measured by the frequency comparator 57 in the comparator 71 is equal to the predetermined value or the measured value measured by the frequency comparator 57 is larger, the selector 73 At, a signal for selecting the error amount of the computing unit 60 is output, and the CAV control is performed. Therefore, since the increase in the rotation speed of the spindle motor 55 is stopped and controlled to a constant value for the CAV control transition, excessive rotation in the inner circumference is prevented.

In the above operation in the second embodiment, the comparator 71 performs the fastest signal processing on the outer circumference by CLV, and the inner processing reduces the signal processing speed to CAV.
By shifting to the control, it is possible to suppress an increase in the rotation speed of the spindle motor 55 due to the CLV control in the inner circumference, and an increase in vibration and power consumption accompanying it.

The predetermined value input from the input terminal 72 is not limited to the limit value indicating the value when the spindle motor 55 rotates at the limit speed, but may be any value for shifting from CLV to CAV. In this case, shift to CAV control on the inner circumference,
The rotation speed of the spindle motor 55 is controlled to be constant. Figure 4
When the limit value C point is set (solid line) and the point D is set (dotted line), the outer circumference is CLV control and the inner circumference is CAV control. However, in FIG. 4, the CLV control is performed at m rpm at the outermost circumference, and the limit rotation speed is n rpm.

Embodiment 3. 5 is a block diagram showing an example of a disk rotation control device according to a third embodiment of the present invention. In the figure, the same reference numerals as those in FIGS. 1 and 3 indicate the same or corresponding portions, and 101 is a selector.

Next, the operation will be described. First, when the optical pickup 51 is jumped from the inner circumference to the outer circumference of the disk 50, the signal processing speed increases toward the outer circumference if the CAV control is continued. Therefore, the frequency comparator 65
The comparator 69 compares the measured value measured in (increases toward the outer periphery during CAV control) with a predetermined value input from the input terminal 70. Here, the predetermined value input from the input terminal 70 is, for example, a frequency comparator when operating at the upper limit of the clock frequency at which the PLL circuit 53 can perform phase synchronization or the upper limit of the signal processing at the digital signal processing circuit 54. The measured value is measured at 65.

In the above, if the measured value measured by the frequency comparator 65 in the comparator 69 is equal to the predetermined value or the measured value measured by the frequency comparator 65 is larger, the selector 101 At, a signal for selecting the error amount of the arithmetic unit 68 is output, and the CLV control is performed. Therefore, since the increase of the reproduction signal frequency is stopped and controlled to a constant value due to the CLV control transition, the PLL circuit 53
The output clock stops increasing and the digital signal processing circuit 54 stops increasing the signal processing speed.

Next, the optical pickup 51 is moved from the outer circumference to the inner circumference.
If the CLV control is continued when jumping, the rotation speed of the spindle motor 55 increases toward the inner circumference. Therefore, the pulse interval measurement value (CLV measured by the frequency comparator 57 and input from the pulse generator 56 is input.
During control, the value becomes larger toward the inner circumference) and the predetermined value input from the input terminal 72 is compared by the comparator 71. Here, the predetermined value is a value measured by the frequency comparator 57 when the spindle motor 55 rotates at a predetermined speed.

In the above, when the measured value measured by the frequency comparator 57 in the comparator 71 is the same as the predetermined value or the measured value measured by the frequency comparator 57 is larger, the selector 101 At, a signal for selecting the error amount of the computing unit 60 is output, and the CAV control is performed. Therefore, since the increase in the rotation speed of the spindle motor 55 is stopped and controlled to a constant value for the CAV control transition, excessive rotation in the inner circumference is prevented.

In the above operation, the comparator 69 reproduces the CAV control on the inner circumference side of the disk 50 with emphasis on improving the accessibility and the CLV control on the outer circumference side for stopping the increase in the signal processing speed. It is possible to apply appropriate disk control according to the position. Further, the comparator 71 performs the highest speed signal processing on the outer circumference by CLV, and the inner circumference reduces the signal processing speed to shift to the CAV control, whereby the rotation speed of the spindle motor 55 by performing the CLV control on the inner circumference. It is possible to suppress the increase in power consumption and the accompanying increase in vibration and power consumption.

The predetermined value input from the input terminal 70 is not limited to the limit value indicating the maximum processing speed, and CAV → CLV
The arbitrary value for the transition or the predetermined value input from the input terminal 72 is not limited to the limit value indicating the value when the spindle motor 55 rotates at the limit speed, but may be any value for the CLV⇒CAV transition. good. As described above, the CAV control is automatically switched to the inner circumference and the CLV control is automatically switched to the outer circumference.

Fourth Embodiment 6 is a block diagram showing an example of a disk rotation control device according to a fourth embodiment of the present invention. In the figure, the same reference numerals as those in FIG. 1 denote the same or corresponding portions, 74 is an input terminal for an acceleration signal, 75 is a control circuit, 76 is an underflow detector, 7
Reference numeral 7 is a selector, and 103 is an input terminal.

Next, the operation will be described. Input terminal 74
The acceleration (kick) signal of the disk 50 supplied from the above is input to the selector 77 and is also supplied to the control circuit 75. The control signal provided from the input terminal 103 is used for switching the selector 61, and the output of the arithmetic unit 60 or the arithmetic unit 68 is switched. On the other hand, in the underflow detector 76, the value of the error signal output from the calculator 60 or the calculator 68 of the selector 61 is compared with a predetermined value. Here, as a result of comparison, if the rotation speed of the disk 50 is extremely low and acceleration is required, an underflow signal is output to the control circuit 75. Further, as a result of comparison, if the rotation speed of the disk 50 approaches the rotation speed under the CAV control or CLV control, the output of the underflow signal is stopped.

In the control circuit 75, the underflow detector 7
While the underflow signal is being output from 6, the selector 77 outputs the selection signal in order to output the acceleration (kick) signal from the input terminal 74, and when the underflow signal is stopped, the output of the PWM signal generation circuit 63 is output. Output the signal to select. Therefore, while the underflow signal is being output, the disk 50 is in an accelerating state, and otherwise the disk 50 is controlled by the PWM signal.

When the predetermined value in the underflow detector 76 is an error signal value when the duty ratio of the PWM signal is 0% or 100%, for example, when the rotation of the disk 50 is too low and the PWM control cannot be performed. Since the underflow signal is output to the input terminal 74, the acceleration signal can be forcibly sent from the input terminal 74, and when the duty ratio of the PWM signal becomes 0 to 100% and the PWM control becomes possible, the acceleration signal is output. Will be released. However, the predetermined value is not limited to the error signal value,
It may be set so that the acceleration signal can be released when the disk 50 has reached a certain rotation or more.

Embodiment 5. 7 is a block diagram showing an example of a disk rotation control device according to a fifth embodiment of the present invention. In the figure, the same reference numerals as those in FIG. 6 indicate the same or corresponding portions, 78 is a deceleration signal input terminal, 79 is a control circuit, 80 is an overflow detector, and 8
1 is a selector.

Next, the operation will be described. Input terminal 78
The deceleration (brake) signal of the disk 50 supplied from the above is input to the selector 81 and is also given to the control circuit 79. The control signal provided from the input terminal 103 is used for switching the selector 61, and the output of the arithmetic unit 60 or the arithmetic unit 68 is switched. On the other hand, the overflow detector 80 compares the value of the error signal output from the calculator 60 or the calculator 68 of the selector 61 with a predetermined value. Here, as a result of comparison, if the rotational speed of the disk 50 is extremely high and deceleration is required, an overflow signal is output to the control circuit 79. Further, as a result of comparison, if the rotation speed of the disk 50 approaches the rotation speed when the CAV control or CLV control is performed, the output of the overflow signal is stopped.

In the control circuit 79, the overflow detector 8
While the overflow signal is output from 0, the selector 81 decelerates (brake) from the input terminal 78.
To output the signal, a selection signal is output, and when the overflow signal stops, a signal for selecting the output of the PWM signal generation circuit 63 is output. Therefore, while the overflow signal is being output, the disk 50 is in the deceleration state,
Otherwise, the disk 50 is controlled by the PWM signal.

When the predetermined value in the overflow detector 80 is an error signal value when the duty ratio of the PWM signal is 0% or 100%, for example, when the rotation of the disk 50 is too high and the PWM control cannot be performed. Since the overflow signal is output, the deceleration signal can be forcibly sent from the input terminal 78, and the deceleration signal is released when the PWM control becomes possible within the duty ratio of the PWM signal within 0 to 100%. You can do it. However, the predetermined value is not limited to the error signal value,
It may be set so that the deceleration signal can be released when the disk 50 becomes less than a certain rotation.

Sixth Embodiment 8 is a block diagram showing an example of a disk rotation control device according to a sixth embodiment of the present invention. In the figure, the same reference numerals as those in FIG. 7 indicate the same or corresponding portions, and 102 is a selector. First, the acceleration (kick) signal of the disk 50 supplied from the input terminal 74 is input to the selector 102 and is also supplied to the control circuit 75. The control signal supplied from the input terminal 103 is used for switching the selector 61, and the output of the arithmetic unit 60 or the arithmetic unit 68 is switched. On the other hand, in the underflow detector 76, the value of the error signal output from the calculator 60 or the calculator 68 of the selector 61 is compared with a predetermined value. Here, as a result of comparison, if the rotation speed of the disk 50 is extremely low and acceleration is required, an underflow signal is output to the control circuit 75. Further, as a result of comparison, if the rotation speed of the disk 50 approaches the rotation speed under the CAV control or CLV control, the output of the underflow signal is stopped.

In the control circuit 75, the underflow detector 7
While the underflow signal is being output from 6, the above acceleration (kick) is applied from the input terminal 74 in the selector 102.
In order to output the signal, a selection signal is output, and when the underflow signal stops, a signal for selecting the output of the PWM signal generation circuit 63 is output. Therefore, the disk 50 is in an accelerated state while the underflow signal is output.

Next, the deceleration (brake) signal of the disk 50 supplied from the input terminal 78 is input to the selector 102 and is also supplied to the control circuit 79. On the other hand, the overflow detector 80 compares the value of the error signal output from the calculator 60 or the calculator 68 of the selector 61 with a predetermined value. Here, the comparison result disk 50
When the number of revolutions is extremely high and deceleration is required, an overflow signal is output to the control circuit 79. Further, as a result of comparison, if the rotation speed of the disk 50 approaches the rotation speed when the CAV control or CLV control is performed, the output of the overflow signal is stopped.

In the control circuit 79, the overflow detector 8
While the overflow signal is being output from 0, the selector 102 outputs the selection signal in order to output the deceleration (brake) signal from the input terminal 78, and when the overflow signal is stopped, the output of the PWM signal generation circuit 63 is selected. Output a signal. Therefore, the disk 50 is in the decelerating state while the overflow signal is output. Therefore, when the underflow signal or the overflow signal is not output, the disk 50 is controlled by the PWM signal.

When the rotation of the disk 50 is other than a predetermined value, PWM
When control is impossible, an underflow signal or an overflow signal will be output, so an acceleration or deceleration signal can be forcibly sent, and the PWM signal dut
When the y ratio becomes 0 to 100% and the PWM control becomes possible, the acceleration or deceleration signal can be released. However, the predetermined value is not limited to the error signal value,
It may be set so that the acceleration or deceleration signal can be released when the disk 50 is out of a certain rotation.

Embodiment 7. FIG. 9 is a block diagram showing an example of a disk rotation control device according to a seventh embodiment of the present invention. In the figure, the same reference numerals as those in FIG. 1 respectively indicate the same or corresponding portions, 83 is a synchronization signal lock determination circuit, 84 is a frequency divider, 85 and 86 are counters, 87 is an input terminal of a sector cycle signal, and 88 is Input terminals for sector period signals, 89 and 90 for comparators, 91 for control circuits, 92 for selectors, 93 for reference signal input terminals, and 94 for hold signals.

Next, the operation will be described. The sync signal lock determination circuit 8 determines whether the sync signal input from the digital signal processing circuit 54 has a predetermined cycle (cycle determined by the recording format or the like) without erroneous detection or omission.
It is judged at 3. This operation of the synchronization signal lock determination circuit 83 can be used also for the lock determination of the synchronization clock of the PLL circuit 53, and also serves as a guide for whether or not the reproduction signal can be read correctly. Therefore, when the synchronization signal is missing for several cycles, the synchronization clock of the PLL circuit 53 is not synchronized with the reproduction signal, and the CLV control using this synchronization clock becomes inappropriate. In the worst case, if the synchronization clock is completely out of synchronization and is output as a fixed cycle clock, the frequency divider 6
An error signal for acceleration or deceleration is always output from the cycle difference from the clock 7 and the disk 50 malfunctions such as over-rotation, stop, or reverse rotation. Therefore, as a result of the determination by the synchronization signal lock determination circuit 83, when the synchronization signal is correctly input, the counters 85 and 86 are reset every synchronization signal cycle.

On the other hand, the frequency divider 84 divides the reference signal input from the input terminal 93 into a clock having a predetermined cycle (for example, the cycle of the synchronizing signal), and the counters 85 and 86.
Entered in. Here, since the counters 85 and 86 are reset every synchronization signal cycle when the synchronization signal is correctly input even if the clock is input, the counters 85 and 86 are reset immediately even after counting up. But,
When the sync signal is missing or erroneously detected, the reset signal is not output from the sync signal lock determination circuit 83, so the counters 85 and 86 are incremented until the sync signal is correctly input and reset. However, the counter 85 and the counter 86 are connected in cascade, and the counter 8
6 corresponds to the upper bits of the counter 85.

Next, a value a corresponding to a predetermined sector cycle of the reproduction signal is input from the input terminal 87. Since, for example, a DVDROM has one sector in 26 frames (synchronization signal cycle), this value is input as 26, and the comparator 89 counts. Compare with the value of 85. Further, a value b corresponding to a period corresponding to a period of several tens of sectors, for example, 20 sectors is input from the input terminal 88, and 20 is input to the comparator 90 for comparison.

In the control circuit 91, when the value of the counter 85 in the comparator 89 is smaller than a, that is, when the loss of the synchronizing signal is smaller than 1 sector (normal reproduction), the selector 92 outputs the output of the calculator 68 (CLV). Error signal) P
The value is output to the WM signal generation circuit 63 and the value of the counter 85 is a.
When it is larger (occurs when a track jump occurs, etc.), a hold signal is output to output the PWM signal generation circuit 6
Hold the output of 3. Therefore, the disk 50
Is in a hold state (a state in which the spindle motor 55 is not supplied with a control voltage and is rotating by inertia) without a CLV control when a synchronization signal larger than one sector is missing.
Until the synchronous clock of the circuit 53 becomes locked again,
It is possible to prevent malfunction of the disk 50, such as over-rotation, stop, or reverse rotation.

Next, if the hold state of the disk 50 continues forever, the rotation will stop, so in the control circuit 91, when the value of the counter 86 in the comparator 90 is larger than b, that is, the above-mentioned sync signal is lost. When there are several tens of sectors or more (the focus of the optical pickup or the track control may be lost), the selector 92
Outputs the output (CAV error signal) of the calculator 60 to the PWM signal generation circuit 63. Therefore, the disk 50 enters the CAV control state by the pulse generator 56 and continues to rotate.

In the above-mentioned operation, the CLV control is once performed in the hold state and then the CAV control is performed according to the missing state of the sync signal.
It is prevented that the rotation of the disk 50 is largely changed by the CAV control suddenly, and the PLL circuit 53 easily resynchronizes the clock because of the hold state. Therefore, in the above, a = 26 and b = 20, but not limited to these, a = the number of missing sync signals at the time of track jump, etc., a × b = focus of the optical pickup, or deviation of track control. In the case of, etc., the number of missing sync signals can be used as a guideline to input a, 88
It is possible to automatically switch the CLV control → the hold state → the CAV control simply by inputting the value of b to b.

[0065]

Since the present invention is constructed as described above, it has the following effects.

As a result of the detection by the detector, when the speed error signal is below a predetermined value, the acceleration means gives the control means an acceleration signal for accelerating the disk, and when the speed error signal is above the predetermined value, the acceleration signal is sent. Since it is canceled, the constant linear velocity control is possible by accelerating in a short time when the disc is started or when the track jump that requires the acceleration of the disc is performed. Since the acceleration signal is released, the disk access can be simplified and speeded up.

When the speed error signal is equal to or more than the predetermined value, the speed reducing signal is applied to the control means by the speed reducing means, and when the speed error signal is less than the predetermined value, the deceleration signal is released. When a track jump that requires deceleration of the disk is performed, deceleration is performed in a short time to enable constant linear velocity control, and the deceleration signal is automatically released when decelerating to the range where constant linear velocity control is possible. Can be simplified and speeded up.

Further, as a result of the detection by the first detector,
When the speed error signal is below a predetermined value, the acceleration means gives the control means an acceleration signal for accelerating the disk, and when the speed error signal is above a predetermined value, the acceleration signal is released, and the detection by the second detector is performed. As a result, when the speed error signal is greater than or equal to the predetermined value, the deceleration means gives the deceleration signal for decelerating the disk to the control means, and when the speed error signal is less than or equal to the predetermined value, the deceleration signal is released. When a normal track jump that requires disk acceleration or deceleration is performed, constant linear velocity control can be performed by accelerating and decelerating in a short time. Since the signal is released, the disadvantage of the constant linear velocity control disk, that is, the disk access delay, can be solved, the access operation can be simplified, and the deceleration means can be used. Thereby preventing excessive rotation of the click.

[Brief description of drawings]

FIG. 1 is a block diagram showing a disk rotation control device according to a first embodiment of the present invention.

FIG. 2 is an operation explanatory diagram of the disk rotation control device in the first embodiment.

FIG. 3 is a block diagram showing a disk rotation control device according to a second embodiment of the present invention.

FIG. 4 is an operation explanatory diagram of the disk rotation control device in the second embodiment.

FIG. 5 is a block diagram showing a disk rotation control device according to a third embodiment of the present invention.

FIG. 6 is a block diagram showing a disk rotation control device according to a fourth embodiment of the present invention.

FIG. 7 is a block diagram showing a disk rotation control device according to a fifth embodiment of the present invention.

FIG. 8 is a block diagram showing a disk rotation control device according to a sixth embodiment of the present invention.

FIG. 9 is a block diagram showing a disk rotation control device according to a seventh embodiment of the present invention.

FIG. 10 is a block diagram showing a disk rotation control device in a conventional example.

[Explanation of symbols]

51 optical pickup, 52 analog signal processing circuit,
53 PLL circuit, 54 digital signal processing circuit, 5
5 spindle motor, 56 pulse generator, 5
7 frequency comparator, 58 phase comparator, 59 frequency divider,
60 arithmetic unit, 61 selector, 62 low pass filter, 63 PWM signal generation circuit, 64 amplifier, 65 frequency comparator, 66 phase comparator, 67 frequency divider, 68
Arithmetic unit, 69 comparator, 70 input terminal, 71 comparator, 72 input terminal, 73 selector, 74 input terminal, 75 control circuit, 76 underflow detector, 7
7 selector, 78 input terminal, 79 control circuit, 80
Overflow detector, 81 selector, 83 synchronization signal lock determination circuit, 84 frequency divider, 85,86 counter, 87,88 comparator, 89,90 input terminal, 91
Control circuit, 92 selector, 93 input terminal, 101,
102 Selector.

   ─────────────────────────────────────────────────── ─── Continued front page    (72) Inventor Noboru Yashima             2-3 2-3 Marunouchi, Chiyoda-ku, Tokyo             Inside Ryo Electric Co., Ltd. (72) Inventor Yukari Hiratsuka             2-3 2-3 Marunouchi, Chiyoda-ku, Tokyo             Inside Ryo Electric Co., Ltd. (72) Inventor Naoki Kizu             2-3 2-3 Marunouchi, Chiyoda-ku, Tokyo             Inside Ryo Electric Co., Ltd. F term (reference) 5D109 KA04 KB05 KB25 KC03 KC07                       KD05 KD14 KD34

Claims (3)

[Claims] 1. A signal generating means for generating a signal synchronized with a reproduction signal of a disk, a control means for controlling a constant linear velocity of rotation of the disk using a signal generated by the signal generating means, and a controlling means. A detector for detecting whether or not the speed error signal is less than or equal to a predetermined value, and an acceleration signal for accelerating the disk when the speed error signal is less than or equal to a predetermined value, and when the speed error signal is greater than or equal to a predetermined value. Is a disk rotation control device having an acceleration means for canceling the acceleration signal. 2. A signal generation means for generating a signal synchronized with a reproduction signal of the disk, a control means for controlling the rotation of the disk at a constant linear velocity using the signal generated by the signal generation means, and this control means. A detector for detecting whether or not the speed error signal at a predetermined value is greater than or equal to a predetermined value, and a deceleration signal for decelerating the disk when the speed error signal is at or above a predetermined value, and when the speed error signal is at or below a predetermined value. Is a disk rotation control device having a deceleration means for releasing the deceleration signal. 3. A signal generating means for generating a signal synchronized with a reproduction signal of the disk, a control means for controlling a constant linear velocity of the rotation of the disk by using a signal generated by the signal generating means, and this control means. A first and second detector for detecting whether or not the speed error signal is less than a first predetermined value, and an acceleration signal for accelerating the disk to the control means when the speed error signal is less than a predetermined value. A disk rotation control device comprising acceleration means and deceleration means for giving a deceleration signal for decelerating the disk when a given value is exceeded.