KR100200733B1 - Device reducing locking access time of an wide capture pll circuit in reproducing device - Google Patents

Abstract

The present invention controls a V16M signal for controlling a phase locked loop circuit that generates a clock for quickly reading data recorded on a recording medium according to the speed of a spindle motor, A frequency divider for dividing an input RFCK frequency by 1 / N and outputting a reference frequency; A microcomputer for recognizing a jumping direction of the disc; At least one or more retarders for attenuating or increasing a frequency component output from the frequency divider according to a jumping direction of the recording medium recognized by the microcomputer; A first selector for selecting one of outputs of the delay units according to a jump direction of the recording disk recognized by the microcomputer; And a phase detector for detecting a phase difference between a frequency selected by the first selector and a frequency output from the frequency divider and outputting the detected phase difference to the low pass filter. As described above, according to the present invention, when the optical pickup jumps a track from the inner peripheral portion to the outer peripheral portion, the clock component of V16M generates a fast clock component, and when jumping a track from the outer peripheral portion to the inner peripheral portion, Component has the effect of reducing the locking access time of the wide-capture phase-locked loop circuit when the reproducing apparatus is operated in normal operation after the jump of the optical pickup by generating a slow clock component.

Description

A device for reducing the locking access time of a wide-capture phase-locked loop circuit of a playback apparatus

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an apparatus for reducing a locking access time of a wide-capture phase-locked loop circuit of a playback apparatus, and more particularly, to a system and method for reducing a clock for rapidly reading data recorded on a recording medium, To a device for reducing the locking access time of a wide-capture phase-locked loop circuit of a reproducing apparatus by controlling a V16M signal for controlling a generated phase-locked loop circuit.

In general, a playback apparatus using a disk as a recording medium such as a CD, a CD-ROM, or a DVD is regarded as an important performance for a time required for a normal operation state from an abnormal operation state, that is, an access time for locking .

FIG. 1 is a diagram for explaining a locking access time of a conventional wide-capture phase-locked loop circuit.

1, reference numeral 10 denotes an MDP signal generating unit for generating a signal MDP for controlling the spindle motor, 12 denotes a clock changing unit for changing the clock of V16M by the speed of the spindle motor Reference numeral 16 denotes a digital phase locked loop circuit for generating a clock for reading data recorded on the recording medium and reference numeral 14 denotes a clock generating section for generating a clock required by the digital phase locked loop circuit 16. The MDP signal generating unit 10 includes a 1/64 frequency divider 101 for inputting a quartz oscillation frequency X'TAL output from a crystal oscillator and dividing the frequency by 1/64, And a phase comparator 103 for comparing the phases output from the 1/64 frequency divider 101 and the 1/2 divider 102. The phase comparator 103 compares the frequency outputted from the 1/2 frequency divider 102 with the 1/2 frequency divider 102, The clock generator 12 receives a reference RF clock signal RFCK and a WFCK signal whose frequency component is varied by outputting a frame signal as the spindle motor rotates to generate a frequency error signal of two clocks RFCK and WFCK A linear velocity servo 121 for outputting a phase error signal and a digital filter 122 for outputting a normalized signal VPCO by receiving a frequency error and a phase error output from the linear velocity servo 121, A low pass filter 144 which receives only the low band signal by inputting the signal VPCO outputted from the digital filter 122 and a second voltage control unit 144 which is controlled by the output signal of the low pass filter 144, An oscillator 145 and a 1 / K frequency divider 125 for dividing the output signal of the first voltage controlled oscillator 145 into 1K. The signal outputted here is a V16M signal, which is a signal for generating a signal for reading data recorded on the recording medium in accordance with the speed of the spindle motor. The clock generating unit 14 includes a 1 / M frequency divider 141 for receiving the V16M signal output from the clock changing unit 12 and dividing the input signal into 1 / M, and an output signal of a predetermined frequency divider 146 A low pass filter 144 for passing only the low frequency components of the output signal of the phase comparator 143 and a first voltage controlled oscillator 144 controlled by the output signal of the low pass filter 144 And a 1 / K frequency divider 146 dividing the output signal of the first voltage-controlled oscillator 145 by 1K and outputting it to the phase comparator 143. In addition, the digital phase-locked loop circuit 16 generates a clock for reading data from the recording medium by the output signal of the clock generating unit 14. [

The operation of the thus constructed apparatus can generate the V16M signal because the linear velocity servo 121 and the digital filter 122 are operated because the RF signal is normally input. However, since the RF signal is not normally input when the optical pickup jumps the track, the locking access time of the wide-capture phase-locked loop circuit increases in the reproducing apparatus using the disk as the recording medium.

It is an object of the present invention to provide a wide capture phase locked loop (PLL) of a playback apparatus, in which a V16M signal approximates to an operating state of a system even when an optical pickup jumps a track, Thereby reducing the locking access time of the circuit.

1 is a view for explaining a locking access time of a conventional wide-capture phase-locked loop circuit.

2 is a block diagram of an apparatus for reducing the locking access time of a wide-capture phase-locked loop circuit according to the present invention.

3 is a timing chart according to the present invention.

In order to control the clock signal for normally reading the data recorded on the recording medium according to the rotation speed of the spindle motor in the reproducing apparatus using the disk as the recording medium according to the present invention for achieving the above object, A linear velocity servo for inputting a WFCK signal whose frequency component is variable according to a rotation speed and outputting a frequency error and a phase error of the RFCK and WFCK signals, and a linear velocity servo for distributing error components output from the linear velocity servo to obtain a normalized frequency VPCO A low-pass filter for generating a control voltage by passing a low-pass signal through a low-pass filter, a voltage-controlled oscillator controlled by an output of the low-pass filter, and a predetermined frequency divider for dividing an output of the voltage- The apparatus for generating the control signal V16M for changing the RFCK frequency divides the input RFCK frequency by 1 / N, A frequency divider for outputting a wave number; A microcomputer for recognizing a jumping direction of the disc; At least one or more retarders for attenuating or increasing a frequency component output from the frequency divider according to a jumping direction of the recording medium recognized by the microcomputer; A first selector for selecting one of outputs of the delay units according to a jump direction of the recording disk recognized by the microcomputer; And a phase detector for detecting a phase difference between a frequency selected by the first selector and a frequency output from the frequency divider and outputting the detected phase difference to the low pass filter.

A microcomputer for outputting a first activation signal when the optical pickup moves the track and outputting a second activation signal when the number of the moved tracks is equal to or greater than the reference track number; A second selector for selecting and outputting the output of the phase detector according to a first activation signal of the microcomputer; And a switching unit for transmitting the output of the second selection unit to control the low-pass filter according to a first activation signal of the microcomputer.

The delay unit may include a first delay unit for outputting a control signal for increasing the control voltage of the voltage controlled oscillator and decreasing the oscillation frequency when the optical pickup moves from the outer periphery to the inner periphery of the disk, And a second delay unit for outputting a control signal for decreasing the control voltage of the voltage control oscillator and increasing the oscillation frequency when the disk moves from the inner circumference to the outer circumference of the disk.

In the present invention, the switching unit inverts the first activation signal of the microcomputer and outputs the inverted first activation signal. An OR gate for receiving the output of the inverter and the second activation signal of the microcomputer as inputs and performing an OR operation; And a buffer unit for passing the output of the second selector only when the output signal of the gate is activated.

In the present invention, when the first activation signal of the microcomputer is not outputted, the voltage control oscillator is controlled by a signal when the track is not jumped.

Hereinafter, the present invention will be described in more detail with reference to the accompanying drawings.

FIG. 2 is a block diagram of an apparatus for reducing the locking access time of a wide-capture phase-locked loop circuit according to the present invention, which is an improvement of the clock changing unit shown in FIG.

2, reference numeral 200 denotes a first frequency divider for dividing the input RFCK frequency by 1 / N to output a reference frequency, reference numeral 210 denotes a direction in which a disc is jumped, A microcomputer 220 outputs a first activation signal when the track is moved and outputs a second activation signal when the number of moved tracks is equal to or greater than the reference track number. At least one or more delay units 230 for attenuating or increasing the frequency components output from the first frequency divider 200 and a delay unit 230 for delaying the frequency components output from the first frequency divider 200 according to the jump direction of the recording medium recognized by the microcomputer 210, And 240 designates a phase difference between the frequency selected by the first selector 230 and the frequency output from the first divider 200 and outputs it to the low pass filter 280) Reference numeral 250 denotes a reference RF clock (RFCK) signal, and a WFCK signal whose frequency component is varied according to the output of the frame signal while the spindle motor is rotating. The frequency of the two clocks RFCK and WFCK A linear velocity servo 250 for outputting an error signal and a phase error signal; 255, a frequency error and a phase error outputted from the linear velocity servo 250 are input to distribute error components to obtain a normalized signal VPCO; Reference numeral 260 denotes a second selector for selecting and outputting the output of the phase detector 240 according to the first activation signal of the microcomputer 210. Reference numeral 260 denotes a first selector of the first Pass filter 280 to control the output of the second selection unit 260 according to the activation signal and 270 denotes a switching unit that transmits the output of the second selection unit 260 260 is connected to the low-pass filter 2 Reference numeral 280 denotes a low-pass filter, reference numeral 290 denotes a voltage-controlled oscillator controlled by the output voltage of the low-pass filter 280, reference numeral 300 denotes a voltage-controlled oscillator 290 And a second frequency divider for dividing the output voltage of the second divider by a predetermined multiple.

The delay unit 220 includes a first delay unit 2201 for outputting a control signal for increasing the control voltage of the voltage controlled oscillator and decreasing the oscillation frequency when the optical pickup moves from the outer periphery to the inner periphery of the disk, And a second delay unit for outputting a control signal for increasing the oscillation frequency by lowering the control voltage of the voltage control oscillator when the optical pickup moves from the inner circumference to the outer circumference of the disk.

The switching unit 270 receives the outputs of the inverters 2701 and 2701 and the second activation signal of the microcomputer 210 for inverting and outputting the first activation signal of the microcomputer 210, And a buffer unit 2703 for passing the output of the second selector 260 only when the output signals of the O gate 2702 and the O gate 2702 are activated.

FIG. 3 is a timing diagram according to the present invention, in which (a) shows the frequency output from the first divider 200, (b) shows the frequency GEN2 output from the first delay 2201 , (C) shows the frequency GEN3 output from the second delay 2202, (d) shows the VPCO adjusted from the frequency GEN2 shown in (b), And the adjusted VPCO from the frequency (GEN3), respectively.

The operation of the present invention will now be described with reference to FIGS. 2 and 3. FIG.

Basically, the present invention extracts data stored in a recording medium on the assumption that a recording medium reproducing apparatus using a CD-ROM, a DVD, etc. is controlled by a linear velocity (CLV) method. Therefore, in order to normally extract data from the inner and outer circumferential portions of the disk, the rotational speed of the spindle motor is controlled at a high speed when data recorded in the inner circumference portion is read, and when the data recorded in the outer circumferential portion is read, You should control the speed slowly. To this end, the present invention intends to reduce the locking access time of the wide-capture phase-locked loop circuit by introducing the concept of controlling the V16M signal when the optical pickup jumps a track.

The RFCK input to the first divider 200 according to the present invention is a signal generated by a crystal oscillator and has a periodicity of one frame in the case of CD. The first divider 200 for inputting this signal inputs the RFCK signal and divides it by 1 / N to use it as a reference signal.

The signal output from the first divider 200 is input to the first delay unit 2201 and the second delay unit 2202 according to a control signal in accordance with the jump direction of the optical pickup recognized by the microcomputer 210 And outputs signals GEN2 and GEN3 for going up or down the oscillation frequency of the voltage controlled oscillator 290. [ That is, the first delay unit 2201 generates a signal GEN2 for advancing in the direction of decreasing the frequency of the voltage-controlled oscillator 290 while the optical pickup jumps from the outer periphery to the inner periphery, When the optical pickup jumps from the inner peripheral portion to the outer peripheral portion, the signal generator GEN2 generates a signal GEN3 for advancing in the direction to raise the oscillation frequency of the voltage controlled oscillator 290. [ In addition, the delay setting of the delay units 220 allows the microcomputer 21 to select according to the jumping direction of the optical pickup. Therefore, the high and low widths of the VPCO input to the low-pass filter 280 can be controlled and can be varied according to the state of the jump.

The first selector 230 selects one of the signals GEN2 and GEN3 output from the delay units 220 according to a control signal according to the jump direction of the optical pickup recognized by the microcomputer 210 . That is, when the optical pickup jumps from the outer peripheral portion to the inner peripheral portion, when the optical pickup jumps from the inner peripheral portion to the outer peripheral portion of the output signal of the first delay device 2201, the output signal of the second delay device 2202 is selected do

The phase detector 240 receives the output of the first divider 200 and the output of the first selector 230 (GEN2 or GEN3), detects the phase difference, and outputs the detected phase difference to the low-pass filter 280. [

However, when the optical pickup does not have a large number of tracks to jump, the actual V16M signal hardly changes. Therefore, if the number of tracks to jump is smaller than the reference number of tracks as a result of detecting the number of tracks to which the optical pickup moves in the microcomputer 210, it is regarded that there is no phase difference detected by the phase detector 240, And holds the value before the jump, that is, the value output from the digital filter 255, by setting the input error component to '0'. However, if the number of tracks to be jumped is larger than the reference number of tracks as a result of detecting the number of tracks to which the optical pickup moves, the microcomputer 210 outputs the phase difference output from the phase detector 240 to the low pass filter 280. Based on this error component, the voltage of the low pass filter 280 is controlled, and the thus controlled voltage controls the voltage controlled oscillator 290 to change the V16M signal.

As described above, according to the present invention, when the optical pickup jumps a track from the inner circumference to the outer circumference, a clock component of V16M generates a fast clock component. When the track jumps from the outer circumference to the inner circumference, The effect of reducing the locking access time of the wide-capture phase-locked loop circuit when the reproducing apparatus is operated in normal operation after the optical pickup jumps.

Claims (5)

In order to control the clock signal for normally reading the data recorded on the recording medium in accordance with the rotation speed of the spindle motor in the reproducing apparatus using the disk as the recording medium, a WFCK signal whose frequency component is varied in accordance with the RFCK signal and the rotation speed of the spindle motor And outputs a frequency error and a phase error of the RFCK and the WFCK signal; a low-pass filter which disperses error components output from the linear velocity servo and low-pass the normalized frequency (VPCO) A voltage controlled oscillator controlled by the output of the low pass filter, and a predetermined divider for dividing the output of the voltage controlled oscillator to generate a control signal V16M for changing the clock signal The apparatus comprising: A frequency divider for dividing the input RFCK frequency by 1 / N and outputting a reference frequency; A microcomputer for recognizing a jumping direction of the disc; At least one or more retarders for attenuating or increasing a frequency component output from the frequency divider according to a jumping direction of the recording medium recognized by the microcomputer; A first selector for selecting one of the outputs of the delay units in accordance with a jump direction of the recording disk recognized by the microcomputer, And a phase detector for detecting a phase difference between a frequency selected by the first selector and a frequency output from the frequency divider and outputting the detected phase difference to the low pass filter to reduce the locking access time of the wide capture phase locked loop circuit. The optical pickup of claim 1, further comprising: a microcomputer for outputting a first activation signal when the optical pickup moves the track, and outputting a second activation signal when the number of moved tracks is equal to or greater than a reference track number; A second selector for selecting and outputting the output of the phase detector according to a first activation signal of the microcomputer; Further comprising a switching unit for transmitting an output of the second selection unit to control the low pass filter according to a first activation signal of the microcomputer. The apparatus of claim 1, wherein the delay units include: a first delay unit for outputting a control signal for increasing the control voltage of the voltage control oscillator when the optical pickup is moved from the outer periphery to the inner periphery of the disk to reduce the oscillation frequency; And a second delay for outputting a control signal for increasing the oscillation frequency by lowering the control voltage of the voltage control oscillator when the optical pickup moves from the inner circumference to the outer circumference of the disk. Apparatus for reducing access time. 3. The microcomputer of claim 2, wherein the switching unit inverts the first activation signal of the microcomputer and outputs the inverted first activation signal; An OR gate for receiving the output of the inverter and the second activation signal of the microcomputer as inputs and performing an OR operation; And And a buffer unit for passing the output of the second selection unit only when the output signal of the gate is activated. 3. The method as claimed in claim 2, wherein when the first activation signal of the microcomputer is not outputted, the voltage control oscillator is controlled by a signal when the track is not jumped, and the locking access time of the wide capture phase- .