WO1996030942A1 - Components for housing an integrated circuit device - Google Patents

Components for housing an integrated circuit device Download PDF

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Publication number
WO1996030942A1
WO1996030942A1 PCT/US1996/003258 US9603258W WO9630942A1 WO 1996030942 A1 WO1996030942 A1 WO 1996030942A1 US 9603258 W US9603258 W US 9603258W WO 9630942 A1 WO9630942 A1 WO 9630942A1
Authority
WO
WIPO (PCT)
Prior art keywords
component
circuit traces
package
metallic substrate
integrated circuit
Prior art date
Application number
PCT/US1996/003258
Other languages
English (en)
French (fr)
Inventor
Paul R. Hoffman
Deepak Mahulikar
George A. Brathwaite
Dawit Solomon
Arvind Parthasarathi
Original Assignee
Olin Corporation
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Olin Corporation filed Critical Olin Corporation
Priority to JP8529426A priority Critical patent/JPH11503565A/ja
Priority to AU53604/96A priority patent/AU5360496A/en
Publication of WO1996030942A1 publication Critical patent/WO1996030942A1/en

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    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49827—Via connections through the substrates, e.g. pins going through the substrate, coaxial cables
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    • H01L23/053—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls the container being a hollow construction and having an insulating or insulated base as a mounting for the semiconductor body
    • H01L23/057—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls the container being a hollow construction and having an insulating or insulated base as a mounting for the semiconductor body the leads being parallel to the base
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    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1515—Shape
    • H01L2924/15153—Shape the die mounting substrate comprising a recess for hosting the device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/15165—Monolayer substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1517—Multilayer substrate
    • H01L2924/15172—Fan-out arrangement of the internal vias
    • H01L2924/15173—Fan-out arrangement of the internal vias in a single layer of the multilayer substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15312—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a pin array, e.g. PGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1532—Connection portion the connection portion being formed on the die mounting surface of the substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/161—Cap
    • H01L2924/1615—Shape
    • H01L2924/16152—Cap comprising a cavity for hosting the device, e.g. U-shaped cap
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/161—Cap
    • H01L2924/1615—Shape
    • H01L2924/16195—Flat cap [not enclosing an internal cavity]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/161—Cap
    • H01L2924/163—Connection portion, e.g. seal
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/30107—Inductance

Definitions

  • Microelectronic devices are typically manufactured from a semiconductor material such as silicon, germanium or gallium/arsenide.
  • the semiconductor material is fashioned into a die, a generally rectangular structure having circuitry formed on one surface. Along the periphery of that electrically active surface are input/output pads to facilitate electrical interconnection to external circuitry.
  • the sealing glass 98 bonds to a peripheral surface 100 of the cover component 96 and to the mid-portion 84 of the first plurality of conductive circuit traces 26, as well as to the dielectric layer 94, if present or else to the substrate 92 if the substrate 92 is non- conductive.
PCT/US1996/003258 1995-03-29 1996-03-11 Components for housing an integrated circuit device WO1996030942A1 (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP8529426A JPH11503565A (ja) 1995-03-29 1996-03-11 集積回路装置を収容するための部品
AU53604/96A AU5360496A (en) 1995-03-29 1996-03-11 Components for housing an integrated circuit device

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US41314995A 1995-03-29 1995-03-29
US08/413,149 1995-03-29

Publications (1)

Publication Number Publication Date
WO1996030942A1 true WO1996030942A1 (en) 1996-10-03

Family

ID=23636049

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US1996/003258 WO1996030942A1 (en) 1995-03-29 1996-03-11 Components for housing an integrated circuit device

Country Status (4)

Country Link
JP (1) JPH11503565A (ja)
AU (1) AU5360496A (ja)
TW (1) TW309654B (ja)
WO (1) WO1996030942A1 (ja)

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6946728B2 (en) 2004-02-19 2005-09-20 Hewlett-Packard Development Company, L.P. System and methods for hermetic sealing of post media-filled MEMS package
EP1630864A3 (en) * 2004-08-23 2008-02-13 Tecnisco Ltd. Substrate with many via contact means disposed therein
CN104952741A (zh) * 2014-03-27 2015-09-30 英特尔公司 柔性基板上的电气电路
WO2016061306A1 (en) * 2014-10-17 2016-04-21 Rsm Electron Power, Inc. Low cost high strength surface mount package
CN111295748A (zh) * 2017-10-05 2020-06-16 德州仪器公司 半导体装置中的引线框

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2005002335A (ja) * 2003-05-21 2005-01-06 Japan Gore Tex Inc 接着フィルムおよびこれを使った半導体装置
US7886437B2 (en) * 2007-05-25 2011-02-15 Electro Scientific Industries, Inc. Process for forming an isolated electrically conductive contact through a metal package
JP2010245337A (ja) * 2009-04-07 2010-10-28 Elpida Memory Inc 半導体装置及びその製造方法
KR101381438B1 (ko) * 2010-04-30 2014-04-04 유보틱 인텔릭츄얼 프라퍼티 컴퍼니 리미티드 인쇄회로기판에 전기적으로 결합되도록 구성된 에어 캐비티 패키지 및 상기 에어 캐비티 패키지의 제공 방법
JP5987222B2 (ja) * 2011-09-30 2016-09-07 住友電工デバイス・イノベーション株式会社 半導体装置

Citations (9)

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Publication number Priority date Publication date Assignee Title
JPS60136348A (ja) * 1983-12-26 1985-07-19 Hitachi Ltd 半導体装置
US4806503A (en) * 1985-10-25 1989-02-21 Sharp Kabushiki Kaisha Method for the replacement of semiconductor devices
US4888449A (en) * 1988-01-04 1989-12-19 Olin Corporation Semiconductor package
US4897508A (en) * 1988-02-10 1990-01-30 Olin Corporation Metal electronic package
JPH0260149A (ja) * 1988-08-26 1990-02-28 Matsushita Electric Works Ltd 半導体パッケージ
US4939316A (en) * 1988-10-05 1990-07-03 Olin Corporation Aluminum alloy semiconductor packages
US4968552A (en) * 1989-10-13 1990-11-06 International Business Machines Corp. Versatile reactive ion etch barriers from polyamic acid salts
JPH04216655A (ja) * 1990-12-18 1992-08-06 Nec Kyushu Ltd 半導体装置
US5352926A (en) * 1993-01-04 1994-10-04 Motorola, Inc. Flip chip package and method of making

Patent Citations (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60136348A (ja) * 1983-12-26 1985-07-19 Hitachi Ltd 半導体装置
US4806503A (en) * 1985-10-25 1989-02-21 Sharp Kabushiki Kaisha Method for the replacement of semiconductor devices
US4888449A (en) * 1988-01-04 1989-12-19 Olin Corporation Semiconductor package
US4897508A (en) * 1988-02-10 1990-01-30 Olin Corporation Metal electronic package
JPH0260149A (ja) * 1988-08-26 1990-02-28 Matsushita Electric Works Ltd 半導体パッケージ
US4939316A (en) * 1988-10-05 1990-07-03 Olin Corporation Aluminum alloy semiconductor packages
US4968552A (en) * 1989-10-13 1990-11-06 International Business Machines Corp. Versatile reactive ion etch barriers from polyamic acid salts
JPH04216655A (ja) * 1990-12-18 1992-08-06 Nec Kyushu Ltd 半導体装置
US5352926A (en) * 1993-01-04 1994-10-04 Motorola, Inc. Flip chip package and method of making

Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6946728B2 (en) 2004-02-19 2005-09-20 Hewlett-Packard Development Company, L.P. System and methods for hermetic sealing of post media-filled MEMS package
US7534662B2 (en) 2004-02-19 2009-05-19 Hewlett-Packard Development Company, L.P. Methods for hermetic sealing of post media-filled MEMS package
EP1630864A3 (en) * 2004-08-23 2008-02-13 Tecnisco Ltd. Substrate with many via contact means disposed therein
CN104952741A (zh) * 2014-03-27 2015-09-30 英特尔公司 柔性基板上的电气电路
US9930793B2 (en) 2014-03-27 2018-03-27 Intel Corporation Electric circuit on flexible substrate
WO2016061306A1 (en) * 2014-10-17 2016-04-21 Rsm Electron Power, Inc. Low cost high strength surface mount package
US9392713B2 (en) 2014-10-17 2016-07-12 Rsm Electron Power, Inc. Low cost high strength surface mount package
CN111295748A (zh) * 2017-10-05 2020-06-16 德州仪器公司 半导体装置中的引线框

Also Published As

Publication number Publication date
AU5360496A (en) 1996-10-16
TW309654B (ja) 1997-07-01
JPH11503565A (ja) 1999-03-26

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