AU5360496A - Components for housing an integrated circuit device - Google Patents

Components for housing an integrated circuit device

Info

Publication number
AU5360496A
AU5360496A AU53604/96A AU5360496A AU5360496A AU 5360496 A AU5360496 A AU 5360496A AU 53604/96 A AU53604/96 A AU 53604/96A AU 5360496 A AU5360496 A AU 5360496A AU 5360496 A AU5360496 A AU 5360496A
Authority
AU
Australia
Prior art keywords
housing
components
integrated circuit
circuit device
integrated
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
Application number
AU53604/96A
Other languages
English (en)
Inventor
George A. Brathwaite
Paul R. Hoffman
Deepak Mahulikar
Arvind Parthasarathi
Dawit Solomon
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Olin Corp
Original Assignee
Olin Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Olin Corp filed Critical Olin Corp
Publication of AU5360496A publication Critical patent/AU5360496A/en
Abandoned legal-status Critical Current

Links

Classifications

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    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49827—Via connections through the substrates, e.g. pins going through the substrate, coaxial cables
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    • H01L23/04—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls
    • H01L23/053—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls the container being a hollow construction and having an insulating or insulated base as a mounting for the semiconductor body
    • H01L23/057—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls the container being a hollow construction and having an insulating or insulated base as a mounting for the semiconductor body the leads being parallel to the base
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    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1515—Shape
    • H01L2924/15153—Shape the die mounting substrate comprising a recess for hosting the device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/15165—Monolayer substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1517—Multilayer substrate
    • H01L2924/15172—Fan-out arrangement of the internal vias
    • H01L2924/15173—Fan-out arrangement of the internal vias in a single layer of the multilayer substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15312—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a pin array, e.g. PGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1532—Connection portion the connection portion being formed on the die mounting surface of the substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/161—Cap
    • H01L2924/1615—Shape
    • H01L2924/16152—Cap comprising a cavity for hosting the device, e.g. U-shaped cap
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/161—Cap
    • H01L2924/1615—Shape
    • H01L2924/16195—Flat cap [not enclosing an internal cavity]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/161—Cap
    • H01L2924/163—Connection portion, e.g. seal
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/30107—Inductance

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Chemical & Material Sciences (AREA)
  • Materials Engineering (AREA)
  • Dispersion Chemistry (AREA)
  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
AU53604/96A 1995-03-29 1996-03-11 Components for housing an integrated circuit device Abandoned AU5360496A (en)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US41314995A 1995-03-29 1995-03-29
US413149 1995-03-29
PCT/US1996/003258 WO1996030942A1 (en) 1995-03-29 1996-03-11 Components for housing an integrated circuit device

Publications (1)

Publication Number Publication Date
AU5360496A true AU5360496A (en) 1996-10-16

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Application Number Title Priority Date Filing Date
AU53604/96A Abandoned AU5360496A (en) 1995-03-29 1996-03-11 Components for housing an integrated circuit device

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Country Link
JP (1) JPH11503565A (ja)
AU (1) AU5360496A (ja)
TW (1) TW309654B (ja)
WO (1) WO1996030942A1 (ja)

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2005002335A (ja) * 2003-05-21 2005-01-06 Japan Gore Tex Inc 接着フィルムおよびこれを使った半導体装置
US6946728B2 (en) 2004-02-19 2005-09-20 Hewlett-Packard Development Company, L.P. System and methods for hermetic sealing of post media-filled MEMS package
JP4387269B2 (ja) * 2004-08-23 2009-12-16 株式会社テクニスコ ビアが形成されたガラス基板及びビアの形成方法
US7886437B2 (en) * 2007-05-25 2011-02-15 Electro Scientific Industries, Inc. Process for forming an isolated electrically conductive contact through a metal package
JP2010245337A (ja) * 2009-04-07 2010-10-28 Elpida Memory Inc 半導体装置及びその製造方法
CN103097282B (zh) * 2010-04-30 2016-01-13 优博创新科技产权有限公司 被配置成用于电气连接到印刷电路板上的气腔封装体以及其提供方法
JP5987222B2 (ja) * 2011-09-30 2016-09-07 住友電工デバイス・イノベーション株式会社 半導体装置
US9930793B2 (en) 2014-03-27 2018-03-27 Intel Corporation Electric circuit on flexible substrate
US9392713B2 (en) * 2014-10-17 2016-07-12 Rsm Electron Power, Inc. Low cost high strength surface mount package
US11444048B2 (en) * 2017-10-05 2022-09-13 Texas Instruments Incorporated Shaped interconnect bumps in semiconductor devices

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60136348A (ja) * 1983-12-26 1985-07-19 Hitachi Ltd 半導体装置
JPS6298737A (ja) * 1985-10-25 1987-05-08 Sharp Corp 半導体装置の交換方法
US4888449A (en) * 1988-01-04 1989-12-19 Olin Corporation Semiconductor package
US4897508A (en) * 1988-02-10 1990-01-30 Olin Corporation Metal electronic package
JPH0260149A (ja) * 1988-08-26 1990-02-28 Matsushita Electric Works Ltd 半導体パッケージ
US4939316A (en) * 1988-10-05 1990-07-03 Olin Corporation Aluminum alloy semiconductor packages
US4968552A (en) * 1989-10-13 1990-11-06 International Business Machines Corp. Versatile reactive ion etch barriers from polyamic acid salts
JPH04216655A (ja) * 1990-12-18 1992-08-06 Nec Kyushu Ltd 半導体装置
US5352926A (en) * 1993-01-04 1994-10-04 Motorola, Inc. Flip chip package and method of making

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Publication number Publication date
JPH11503565A (ja) 1999-03-26
WO1996030942A1 (en) 1996-10-03
TW309654B (ja) 1997-07-01

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