WO1996029794A1 - Circuit numerique d'egalisation de phases avec dispositif de retard et voies de transmission identiques - Google Patents

Circuit numerique d'egalisation de phases avec dispositif de retard et voies de transmission identiques Download PDF

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Publication number
WO1996029794A1
WO1996029794A1 PCT/DE1996/000378 DE9600378W WO9629794A1 WO 1996029794 A1 WO1996029794 A1 WO 1996029794A1 DE 9600378 W DE9600378 W DE 9600378W WO 9629794 A1 WO9629794 A1 WO 9629794A1
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WIPO (PCT)
Prior art keywords
circuit arrangement
data signal
delay
signal
clock signal
Prior art date
Application number
PCT/DE1996/000378
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German (de)
English (en)
Inventor
Roland BRÜCKNER
Robert Stemplinger
Original Assignee
Siemens Aktiengesellschaft
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Siemens Aktiengesellschaft filed Critical Siemens Aktiengesellschaft
Publication of WO1996029794A1 publication Critical patent/WO1996029794A1/fr

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Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/02—Speed or phase control by the received code signals, the signals containing no special synchronisation information
    • H04L7/033—Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/02—Speed or phase control by the received code signals, the signals containing no special synchronisation information
    • H04L7/033—Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop
    • H04L7/0337—Selecting between two or more discretely delayed clocks or selecting between two or more discretely delayed received code signals
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/0008—Synchronisation information channels, e.g. clock distribution lines

Definitions

  • Digital runtime controller with delay device and the same transmission channels.
  • sampling of the data signal with the clock signal on which the data signal is based is necessary.
  • a transmission of the data signal and the associated clock signal on separate lines is known as synchronous transmission.
  • a respective bit of the data signal is emitted, for example, with the negative flank of the clock signal and clocked in the receiver with the opposite flank of the clock signal as when transmitting, in other words here with the positive flank of the clock signal, and is thus taken over.
  • phase fluctuations of the data signal and the clock signal (jitter) caused by electromagnetic influences on the lines as well as pulse-pause distortions of the clock signal and further runtime differences between clock signal line and data signal line become apparent. noticeable, with which a secure transfer of the data signal in
  • Receiver is no longer guaranteed.
  • the limit for the safe operation of a purely synchronous transmission with regard to frequency and phase position is given when the signal transit time exceeds a few bit durations of the data signal. This can be remedied by a phase matching circuit arranged on the receiver side.
  • the subject matter of the application relates to a circuit arrangement for regulating a phase deviation between a data signal and a clock signal in the
  • the data signal can be delayed in a delay device, which can be set with regard to the delay duration of a signal passing through it
  • An evaluation device for detecting the directional phase deviation between the data signal emitted by the delay device and the clock signal is provided -
  • This type of circuit arrangement known from DE 3441501 AI is suitable for use in transmission line receivers.
  • the clock signal, according to which the data signal is transmitted is not transmitted on a transmission path parallel to the transmission path of the data signal.
  • indications of a transmission of the clock signal, according to which the data signal is transmitted, on a transmission path parallel to the transmission path of the data signal are not apparent from the cited literature reference.
  • the clock signal with the corresponding clock frequency required in this circuit arrangement for the supply on the input side is therefore given by a locally generated clock signal or by a clock signal distributed via a clock distribution system.
  • the known circuit arrangement must therefore be able to compensate for at least one bit duration of the data signal, which is not only a correspondingly high expenditure on circuitry, for example for the length of the circuit Delay device and the associated area requirement, during production, but also an associated increased power loss during operation. These two types of effort are all the more noticeable when a plurality of these circuit arrangements are implemented in an integrated circuit.
  • the object of the application is based on the problem of further developing the circuit arrangement torn at the beginning in such a way that the disadvantages mentioned are avoided.
  • the problem is solved in the circuit arrangement outlined at the outset in that the data signal and the clock signal, according to which the data signal is transmitted, are transmitted to the circuit arrangement on separate transmission paths which carry electrical signals and which are identical to one another and which are guided in close spatial proximity are fed.
  • the subject of the registration therefore entails a secure takeover of even highly jittered data signals with little effort in the circuitry to be provided and the power loss to be introduced.
  • the phase position between the data signal and the clock signal can be detected in the evaluation device by multiple clocking within a transmission period of one bit of the data signal, a corresponding phase position being given when the clocking with each other bring the same result.
  • this measure ensures that the center between the external clockings is at least offset inwards by at least the distance between the center and an external clocking from the boundary of the eye opening and is thus available for the actual clocking of the data signal stands.
  • the circuit arrangement has a one-part device which only changes the delay period of the delay line if the evaluation device has detected a shift in the phase position going in the same direction for several bits of the data signal.
  • the circuit arrangement is formed exclusively with gates that implement logic functions. This measure means that the circuit arrangement can be easily implemented in an integrated circuit, non-integrable components which have to be arranged outside the integrated circuit and which require additional connections of the integrated circuit to be avoided.
  • the circuit arrangement is implemented in an integrated circuit which combines two technologies with different upper cut-off frequencies.
  • circuit parts such as the setting device, which are operated with a considerably lower upper data rate than that operated by the technology with the higher upper data rate, can be implemented in a technology which is compared to the technology with the higher upper data ⁇ rate has a significantly reduced power loss.
  • the evaluation device can be switched off again and again for predetermined periods of time.
  • This measure which is based on the knowledge that changes in the phase difference between the data signal and the clock signal take place in relatively long periods of time, brings about a saving in the power loss for the time of switching off, which is necessary for the operation of the evaluation device implemented in the technology with the high power loss is required.
  • the viewing arrangement has a plurality of delay devices, each of which is supplied with a data signal transmitted in accordance with the clock signal.
  • a line carrying the associated clock signal is common to several lines each carrying a data signal, as a result of which the proportionate effort per data line for the clock signal line is reduced.
  • the circuit arrangement has an evaluation device which is common to a plurality of delay devices and which can be cyclically switched over to the individual delay devices. This measure, which is based on the knowledge that changes in the phase difference between the data signal and the clock signal take place over relatively long periods of time, results in a proportionate division of the structural and operational expenditure for the evaluation device implemented in technology with the high power loss with yourself.
  • the circuit arrangement has a delay device which, instead of the evaluation device and the input device, can be adjusted in terms of its delay duration by a control signal supplied from outside.
  • this measure enables the eye opening and thus the transmission reserve to be determined, the eye opening being determined by the most widely spaced evaluation results for which the evaluation device has a matching phase position has determined between the data signal and the clock signal.
  • FIG. 1 shows a basic illustration of a circuit arrangement realizing the subject of the application.
  • a data signal with a data rate of 800 Mbit / s in the exemplary embodiment and the associated clock signal are transmitted as in the case of synchronous transmission.
  • a phase detector checks the phase position of the data signal with respect to the associated clock signal and controls an adjustable delay chain in the data input until delay differences in the clock and data path are balanced.
  • a typical application of the subject matter of the present application is in a subrack of a switching device in the connection of two to one another. different modules of annexed switching matrix modules via the backplane of the subrack.
  • the functional blocks of the digital runtime compensation are shown in FIG.
  • a delay device VZE formed with a runtime chain LZK, a selection multiplexer MUX, a switchover synchronization USYN, an evaluation device DET (for: detector), level converter CMOS-ECL conv or ECL-CMOS Conv and one implements an adjusting device realizing control part ST.
  • the runtime chain is formed with a plurality of runtime elements and the selection multiplexer MUX, also referred to as a changeover switch, which switches between the differently delayed data signals.
  • the length of the runtime chain is 2 ⁇ equal to eight runtime links and the runtime of a buffer is nominally 125 ps (spread ⁇ 20%).
  • the control range of the running label is thus ⁇ 440 ps and even assuming the most unfavorable conditions (worst case), it is less than half a bit duration equal to 625 ps, but nevertheless ⁇ 370 ps. If the mode setting mode is omitted, the runtime chain can be shorter and thus power loss can be saved or the resolution can be improved (the minimum inverter runtime is approximately 70 ps).
  • the circuit part of the clock input TE, to which the associated clock signal CLIN is supplied on the input side, provides the necessary, differently delayed clocks clO, cll,... Cl3 via drivers.
  • the essentially undelayed clock clO is fed to the output COU of the circuit arrangement and, after the phase compensation of the data signal, the associated clock signal.
  • Further function blocks relate to the rule file generation and the encoders and decoders used for evaluation and permanent setting.
  • To identify the phase position of the output signal emitted by the delay device it is clocked in the evaluation device at three points in time offset by the time period t 1 and the respective state of this output signal is adopted in three flip-flops FFa, FFb and FFc.
  • the results are in the open eye of the eye diagram of the data signal when the clockings produce the same results.
  • the output signal emitted by the flip-flop FFb is present as the data signal which is in phase relationship with the clock signal at the output COU at the output DOU of the circuit arrangement.
  • the two output signals UP and DN of the evaluation device are set as follows, correct detection taking place:
  • bit slip As can be seen in FIG. 2, as long as there is no skipping of a bit, which is referred to in specialist circles as bit slip, the probability of a single correct signal (p1) depending on the jitter probability function and the transit time t 1 is clear higher than for a single erroneous signal (p2). If several data changes are recorded in each case, the probability that only the erroneous signal occurs repeatedly is very low.
  • the three detections flip-flops (FFa, FFb, FFc) are reset at the start of a measuring cycle.
  • injuries are registered and saved as shown above.
  • the following conditions can occur at the end of this registration phase: At this point, reference is made to Table 1.
  • a skipping of a bit which is referred to in specialist circles as a bit slip, occurs when a stable control state occurs in which the input data signal is shifted by one or more bits with respect to the clock signal.
  • a bit slip can certainly be avoided if the sum of the maximum setting range of the runtime chain ( ⁇ value) and the greatest possible runtime difference between the clock and data at the input does not exceed half a bit duration, in the exemplary embodiment 625 ps (case a). If there is little overlap, if the sum of the control range and delay offset is smaller than the sum of half the bit duration and total jitter (case b), a bit slip can occur, but is not stable. With a very large control range and delay offset (sum> 1 bit duration, case c)), a stable bit-slip state must always be expected.
  • tget Setup time .Abtakt FFs of the synchronous input or the DLA t Hold : Hold time Abakt FFs of the synchronous input or the
  • DLAs tpp pulse pause distortion of the clock signal t Skew : delay time between clock and data t ⁇ : delay between two clock times in the DLA t ⁇ ,: delay time of a delay element in the
  • the required eye opening of the digital transit time compensation is given by the fact that the three samples lie in the open window, or two samples and a transit time tL (adjustment of the transit time chain on the basis of the different sampling result of the third FF), so that the A correct mean oscillate between two neighboring states
  • REPLACEMENT LEAF palpation enables.
  • the required eye opening indicated in the above illustration is obtained by plotting the data edges with respect to the positive clock edge (eg on the storage oscilloscope).
  • the hatched area denotes the maximum permissible jitter of the data signal compared to the clock signal.
  • the required eye opening is determined in addition to the setup and hold time of the flip-flop clock, the delay in time between the clock signal and the data signal and the pulse-pause distortion of the clock.
  • the required eye opening is independent of the runtime offset between the clock signal and the data signal within the setting range. Using the digital transit time compensation therefore brings a gain in transfer reserve compared to a purely synchronous transfer if the transit time difference and the influence by pulse-pause distortion of the clock signal are greater than the transit time difference t ⁇ two sampling times of the DLA.
  • phase control detects an edge change in the data signal and selects the clock edge shifted by T / 2 for clocking the data signal.
  • ERS ⁇ ⁇ ZBLATT serve (x) is therefore significantly smaller. Averaging over many detected data edges ensures a clock edge in the middle of the bit. If only individual data edges are used for phase detection, ie no integration of the control signal is carried out, only half the jitter compared to an analog control circuit, which is known to carry out an integration of the control signal, can be permitted. An integration of the phase control signal is achieved by evaluating several data changes in each case. Averaging of the jitter can be achieved by recording several data changes during the digital runtime compensation, since the runtime chain is only adjusted if an eye that is open towards a new setting is also present.
  • the jitter of the clock signal is correlated with the jitter of the data signal by carrying the associated clock signal with the data signal. Due to the fact that the synchronous clock signal is carried along, the least amount of circuitry and the least power loss is to be expected in the digital runtime compensation compared to other digital phase-locked loops with the same resolution (high data rate), because due to the fixed relationship between the clock signal and the data signal, there is only a limited bit duration Part of the bit duration that must be compensated.
  • the digital transit time compensation which forms a digital control loop, can only be implemented with circuit parts that implement logic functions and can therefore be easily implemented in an integrated circuit.
  • the circuit arrangement can be implemented in 0.6 ⁇ m BiCMOS (Bipolar Complementary Metal Oxide Semiconductor) technology, which the
  • ECL emitter Coupled Logic
  • CMOS Complementary Metal Oxide Semiconductor
  • REPLACEMENT LEAF agile Information relating to the remaining transmission reserve can be obtained by implementing a second operating mode through the digital transit time compensation.
  • the runtime chain is set via a control signal supplied, for example, by a computer interface.
  • the eye opening in the receiver can be determined indirectly within the control range.
  • a buffer on the integrated circuit in a ring oscillator which is constructed identically to the runtime link in the running chain represents a possibility for determining the buffer runtime, so that the absolute size of the eye opening can be determined.
  • the external adjustment possibility offers a detection possibility and thus a test possibility of the even with a very small eye opening and at the same time delay
  • control signal is obtained by triple clocking the data and comparing the results. Different results are recognized (EXOR) and stored in two flip-flops FFd, FFe with synchronous set and asynchronous reset input.
  • the runtime difference of the clock cycles t-R is 150 ps (nom.) Larger than the buffer runtime tL of the runtime chain, but as small as possible in view of the required eye opening.
  • the control part having the adjustment device is designed to reduce the power loss in CMOS circuit technology.
  • CMOS circuit technology For level transitions from CMOS technology 5 ECL / CMOS and 2 CMOS / ECL converters per data input are arranged for ECL technology.
  • the function of the one-part device includes the evaluation of the UP and DN signals from the evaluation device, also known as a detector part, and the resetting (re) of its flip-flops FFd, FFe, the setting and storage of the runtime chain in a counter (3-bit UP / DOWN Counter), the generation of the changeover signal for the changeover switch MUX, and the generation of the clocks of the sequence control by dividing the input clock CLP.
  • the switchover between setting and control mode (mode switchover) and the memory for mode bit and setting (3 bit) are also implemented.
  • the counter status of the runtime chain is available at the OC outputs for further processing.
  • the registration phase of the phase detection is characterized by the boundary conditions integrating and settling behavior. Based on the application with ATM cells, the registration phase was set to approx. 500 bits (length of a cell), which means that bit changes occur reliably due to the header.
  • the digital runtime compensation can also be used for long identical sequences.
  • the control cycle (output frequency) is reduced to 50 kHz for evaluation with a universal computing machine, e.g. to enable a personal computer (PC).
  • the operating mode can be selected separately via the smod input and the desired setting of the runtime chain can be made.
  • Each input has a 4-bit memory that can be written to via a simple computer interface (4-bit data, 4-bit select sin and the write signal wr), one bit for the operating mode and three bits for the setting.
  • the data input is selected using chip select signals by a laus5 or laus2 decoder (not shown in more detail).
  • the state of the delay device can in each case be
  • REPLACEMENT LEAF t input can be tapped at the test outputs of the digital transit time compensation.
  • the selection is made by means of the chip select signals by a 5zul or 2zul bait (not shown in more detail).
  • the module reset res or the reset for the digital runtime compensation is active, all control functions are reset.
  • the state of all runtime chains is the middle position.
  • the reset is set asynchronously and withdrawn synchronously with the 100 MHz CMOS clock.
  • the design of the interfaces allows a bit rate of up to approx. 1.5 GBit / s (worst case).
  • a saving in power loss can be achieved by switching off the unnecessary ECL circuit parts and level converters if the control system is not constantly switched on. This is possible because runtime differences are caused by geometry, material or temperature and therefore have a rather large time constant.
  • a plurality of data inputs, to each of which data signals with mutually different data content can be fed, can be fed together with the clock signal associated with these data signals to an input port of the circuit arrangement.

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  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)

Abstract

Cette invention concerne un circuit de correction d'un déphasage entre un signal de données à haut débit binaire, sévèrement affecté de gigues, et le signal d'horloge associé. Le signal d'horloge qui gère l'émission du signal de données, et le signal de données sont introduits dans le circuit par des voies de transmission distinctes mais placées à proximité immédiate l'une de l'autre. Le circuit est constitué d'un dispositif de retard pour lequel une capacité de retard inférieure à la durée d'un bit du signal de données est suffisante. Ce circuit étant conçu exclusivement avec des composants de fonctions logiques et pouvant, par conséquent être introduit facilement dans un circuit intégré, il ne requiert qu'une technologie de circuit peu sophistiquée et se caractérise par de très faibles pertes d'énergies.
PCT/DE1996/000378 1995-03-23 1996-03-04 Circuit numerique d'egalisation de phases avec dispositif de retard et voies de transmission identiques WO1996029794A1 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
DE19510549.4 1995-03-23
DE19510549 1995-03-23

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Publication Number Publication Date
WO1996029794A1 true WO1996029794A1 (fr) 1996-09-26

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Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3735056A (en) * 1971-03-03 1973-05-22 Kabel Metallwerke Ghh System for transmitting digital signals
DE3441501A1 (de) * 1984-11-14 1986-05-15 Standard Elektrik Lorenz Ag, 7000 Stuttgart Schaltungsanordnung zum regenerieren und synchronisieren eines digitalen signals
EP0418641A2 (fr) * 1989-09-19 1991-03-27 Siemens Aktiengesellschaft Dispositif de synchronisation pour un signal numérique

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3735056A (en) * 1971-03-03 1973-05-22 Kabel Metallwerke Ghh System for transmitting digital signals
DE3441501A1 (de) * 1984-11-14 1986-05-15 Standard Elektrik Lorenz Ag, 7000 Stuttgart Schaltungsanordnung zum regenerieren und synchronisieren eines digitalen signals
EP0418641A2 (fr) * 1989-09-19 1991-03-27 Siemens Aktiengesellschaft Dispositif de synchronisation pour un signal numérique

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