Classifications

• • B—PERFORMING OPERATIONS; TRANSPORTING
  • B24—GRINDING; POLISHING
  • B24B—MACHINES, DEVICES, OR PROCESSES FOR GRINDING OR POLISHING; DRESSING OR CONDITIONING OF ABRADING SURFACES; FEEDING OF GRINDING, POLISHING, OR LAPPING AGENTS
  • B24B37/00—Lapping machines or devices; Accessories
  • B24B37/04—Lapping machines or devices; Accessories designed for working plane surfaces
  • B24B37/042—Lapping machines or devices; Accessories designed for working plane surfaces operating processes therefor
• • B—PERFORMING OPERATIONS; TRANSPORTING
  • B24—GRINDING; POLISHING
  • B24B—MACHINES, DEVICES, OR PROCESSES FOR GRINDING OR POLISHING; DRESSING OR CONDITIONING OF ABRADING SURFACES; FEEDING OF GRINDING, POLISHING, OR LAPPING AGENTS
  • B24B37/00—Lapping machines or devices; Accessories
  • B24B37/04—Lapping machines or devices; Accessories designed for working plane surfaces
• • B—PERFORMING OPERATIONS; TRANSPORTING
  • B24—GRINDING; POLISHING
  • B24B—MACHINES, DEVICES, OR PROCESSES FOR GRINDING OR POLISHING; DRESSING OR CONDITIONING OF ABRADING SURFACES; FEEDING OF GRINDING, POLISHING, OR LAPPING AGENTS
  • B24B37/00—Lapping machines or devices; Accessories
  • B24B37/04—Lapping machines or devices; Accessories designed for working plane surfaces
  • B24B37/07—Lapping machines or devices; Accessories designed for working plane surfaces characterised by the movement of the work or lapping tool
  • B24B37/10—Lapping machines or devices; Accessories designed for working plane surfaces characterised by the movement of the work or lapping tool for single side lapping
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
  • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
  • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
  • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
  • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
  • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
  • H01L21/304—Mechanical treatment, e.g. grinding, polishing, cutting

Definitions

• the present invention relates a chemical- mechanical polishing method to effect a high removal rate of material and uniform planarization of a surface on a wafer during the manufacture of a semiconductor device.
• the invention has particularly application in rapidly planarizing thin films of dielectric material.
• Semiconductor integrated circuits are manufactured by forming an array of separate dies on a common semiconductor wafer. During processing, the wafer is treated to form specified regions of insulating, conductive and semiconductor type materials.
• a wiring pattern comprising a dense array of conductive lines is formed by depositing a metal layer and etching to form a conductive pattern. A dielectric is then applied to the wiring pattern and planarization is effected as by chemical-mechanical polishing.
• Chemical-mechanical polishing is a conventional technique employed to planarize a patterned insulating layer or a patterned metallic layer.
• a pattern 110 is formed on layer 120 of, for example, an insulating material, a conductive material such as a metal, or a semiconductor substrate having an interwiring spacing 130 and trench 140.
• the object is to completely fill the interwiring spacing 130 and trench 140 with a subsequently deposited material 100 as, for example, an insulating material if pattern 110 is a conductive pattern.
• CMP chemical- mechanical planarization or polishing
• wafers to be polished are mounted on polishing blocks which are placed on the CMP machine.
• a polishing pad is adapted to engage the wafers carried by the polishing blocks.
• a cleaning agent is dripped onto the pad continuously during the polishing operation while pressure is applied to the wafer.
• a typical CMP apparatus 300 is shown in Fig. 3 and comprises a rotatable polishing platen 302, polishing pad 304 mounted on platen 302, which are driven by microprocessor control motor (not shown) to spin at about 25 to about 50 RPM.
• Wafer 306 is mounted on the bottom of a rotatable polishing head 308 so that a major surface of wafer 306 to be polished is positionable to contact the underlying polish pad 304.
• Wafer 306 and polishing head 308 are attached to a vertical spindle 310 which is rotatably mounted in a lateral robotic arm 312 which rotates the polishing head 308 at about 15 to about 30 RPM in the same direction as platen 302 and radially positions the polishing head.
• Robotic arm 312 also vertically positions polishing head 308 to bring wafer 306 into contact with polishing head 304 and maintain an appropriate polishing contact pressure.
• a tube 314 opposite polishing head 308 above polishing pad 304 dispenses and evenly saturates the pad with an appropriate cleaning agent 316, typically a slurry.
• An object of the present invention is a CMP method for uniformly planarizing a surface on a wafer at a high removal rate of material.
• a method of manufacturing a semiconductor device wherein a surface of a wafer is planarized comprising chemical- mechanical polishing the surface to effect planarization while applying a first pressure to the wafer and intermittently reducing the first pressure to a second pressure a plurality of times during chemical-mechanical processing.
• Another aspect of the invention is an improvement in a conventional method of chemical-mechanical polishing a surface of a wafer to effect planarization during manufacturing of a semiconductor device, wherein the wafer is placed on a polishing pad, a cleaning agent applied to the polishing pad, pressure applied to the wafer, the improved comprising intermittently reducing the pressure during chemical- mechanical polishing a plurality of times.
• Figure 1 illustrate a layer of material deposited on a patterned material.
• Figure 2 illustrates the planarized deposited layer of Figure 1.
• Figure 3 schematically illustrates a typical chemical-mechanical polishing machine.
• the present invention addresses the limitations of conventional CMP technology in achieving uniformly planarized surfaces of materials, particularly dielectric materials, at high removal rates.
• the inability of conventional CMP technology to achieve high polishing rates constitutes a serious economic impediment.
• Time consuming CMP decreases production throughput, consumes man hours and exhausts large amounts of cleaning agent and other consumable materials.
• the lack of a uniformly planarized surface adversely affects the reliability of the resulting semiconductor device, particularly in devices comprising multi-level vias wherein the upper vias would be overetched to insure complete etching at the lower levels.
• the present invention addresses and solves such limitations of conventional CMP technology, i.e., methodology and apparatus, by selecting an appropriate initial pressure applied to wafer undergoing CMP and intermittently reducing the initial pressure to a second pressure a plurality of times during the course of CMP processing. I discovered that during the course of CMP processing, the surface to be polished in contact with the polishing pad becomes depleted in cleaning agent, which adversely affects the polishing rate and uniformity of the CMP operation, since incomplete polishing occurs in depleted areas, as toward the center of the wafer.
• the initial pressure applied to the wafer undergoing CMP is intermittently reduced creating a pulsing pressure, thereby enabling the cleaning agent, which is normally continuously applied to the polishing pad, to continuously reach all portions of the surface of the wafer undergoing polishing throughout the entire CMP operation.
• the periodic reduction of pressure applied to the wafer during CMP processing eliminates the negative impact of starvation areas, i.e., areas which do not have a sufficient amount of cleaning agent.
• the present invention can be practiced employing otherwise conventional CMP technology, i.e., techniques and apparatus.
• CMP apparatus disclosed in the previously mentioned Gill , Jr. or Walsh patents can be employed in the practice of the present invention.
• a commercially available CMP apparatus which can be employed in the present invention is Model 372 Polish and manufactured by Westex Systems, Inc., of Phoenix, Arizona or Strasbaug, San Luis Opisbo, California Model 6DFSP form.
• the polishing pad employed in the claimed invention can be any of those which are conventionally employed in CMP, such as those comprising a cellular polyurethane pad, preferably about 50 mills thick.
• the cleaning agent employed in the claimed invention can be any of those conventionally employed in CMP processing.
• a slurry most preferably a slurry comprising potassium hydroxide and particulate silica, is employed.
• the improved CMP technique of the present invention can be employed to planarize various types of surfaces on a wafer, including conductive and insulating materials, such as oxides, tetraethyl orthosilicate, also referred to as tetraethoxysilane (TEOS) , nitrides, polysilicon, single crystalline silicon, amorphous silicon, and mixtures thereof.
• conductive and insulating materials such as oxides, tetraethyl orthosilicate, also referred to as tetraethoxysilane (TEOS) , nitrides, polysilicon, single crystalline silicon, amorphous silicon, and mixtures thereof.
• a dielectric layer such as TEOS
• the substrate of the wafer containing the conductive or non-conductive material is generally a semiconductor material, such as silicon.
• the first pressure is intermittently reduced to the second pressure during the course of CMP.
• the frequency of reducing the initial pressure depends upon each particular CMP operation, e.g., the particular CMP apparatus, speed of polishing, materials undergoing planarization and cleaning agent.
• the first pressure is reduced to the second pressure about every 1 to 15 seconds, preferably about every 1 to 10 seconds, most preferably about every 1 to 5 seconds.
• the first pressure is intermittently reduced to the second pressure about every 1 to 3 seconds.
• the speed and uniformity of planarization effected by conventional CMP technology is greatly improved by virtue intermittently reducing the pressure applied to the wafer undergoing planarization from an optimum initial pressure, preferably to about 0 psi.
• the inventive pulse CMP technique is applicable to a wide variety of situations which require planarization during the course of manufacturing a semiconductor device.

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• 1995
  • 1995-02-06 US US08/383,737 patent/US5486265A/en not_active Expired - Lifetime
• 1996
  • 1996-01-11 DE DE69607940T patent/DE69607940T2/de not_active Expired - Lifetime
  • 1996-01-11 JP JP8524253A patent/JPH10513121A/ja active Pending
  • 1996-01-11 KR KR1019970704799A patent/KR100399877B1/ko not_active IP Right Cessation
  • 1996-01-11 EP EP96902098A patent/EP0808230B1/de not_active Expired - Lifetime
  • 1996-01-11 WO PCT/US1996/000151 patent/WO1996024466A1/en active IP Right Grant

Patent Citations (7)

Non-Patent Citations (1)

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