WO1996024136A1 - Memoire a semi-conducteurs - Google Patents

Memoire a semi-conducteurs Download PDF

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Publication number
WO1996024136A1
WO1996024136A1 PCT/JP1995/001899 JP9501899W WO9624136A1 WO 1996024136 A1 WO1996024136 A1 WO 1996024136A1 JP 9501899 W JP9501899 W JP 9501899W WO 9624136 A1 WO9624136 A1 WO 9624136A1
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WO
WIPO (PCT)
Prior art keywords
transfer
memory
signal
circuit
semiconductor memory
Prior art date
Application number
PCT/JP1995/001899
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English (en)
Japanese (ja)
Inventor
Tomoyuki Shibata
Kanji Oishi
Original Assignee
Hitachi, Ltd.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi, Ltd. filed Critical Hitachi, Ltd.
Publication of WO1996024136A1 publication Critical patent/WO1996024136A1/fr

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Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1075—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers for multiport memories each having random access ports and serial ports, e.g. video RAM

Definitions

  • the present invention relates to a semiconductor memory device, and more particularly to a technique effective when used for an image memory having a random access port and a serial access port.
  • a dual-port memory for raster image processing and a serial input function is also available for dual 56K image processing.
  • Nikkei McGraw-Hill, March 19, 1996 Nikkei Electronics, page 24 It is known from page 264.
  • Japanese Patent Application No. 1-658843 proposes a two-port memory in which one serial input / output register is provided in common for a plurality of memory arrays or memory mats. Disclosure of the invention
  • the two-port memory disclosed in Japanese Patent Application No. Hei 11-65843 is intended to simplify the circuit by using the serial access section SAM commonly for a plurality of memory arrays.
  • SAM serial access section
  • transfer control becomes complicated, and current consumption increases due to the operation of multiple sense amplifiers.
  • the signal lines for serial transfer are arranged so as to overlap with the data lines of the memory array so that the degree of integration is not reduced.
  • the number of masks required for manufacturing a semiconductor memory device increases, and the manufacturing process becomes complicated. Above all, such a complicated process inevitably leads to an increase in the rate of occurrence of defects, so that the mass production, which is a characteristic of semiconductor integrated circuit devices, cannot be utilized in conjunction with the addition of the above manufacturing process. Increases product costs.
  • a memory circuit for serial input / output which is commonly used is provided for a plurality of memory arrays including a plurality of memory cells arranged in a matrix and a sense amplifier for amplifying the minute signal.
  • the signal amplified by the amplifier is divided into a plurality of blocks, and the signals are transferred in time series to the corresponding memory bits of the storage circuit as a signal amplitude sufficiently reduced with respect to the power supply voltage, and simultaneously with the transfer operation. Synchronize the stored information transferred to the memory circuit in parallel with the clock signal to start the serial output operation, split the data into multiple blocks, and perform time-series signal transfer and signal transfer with small amplitude.
  • FIG. 1 is a block diagram showing one embodiment of a semiconductor memory device according to the present invention.
  • FIG. 2 is a schematic layout diagram for explaining an embodiment of the relationship between the memory array of FIG. 1 and the SAM section
  • FIG. 3 is a schematic layout diagram of the memory array of FIG.
  • FIG. 4 is a circuit diagram of each KB for explaining one embodiment of the relationship with the SAM unit.
  • FIG. 4 shows another embodiment of the relationship between the memory array of FIG. 2 and the SAM unit.
  • 5 is a timing chart for explaining an example of the serial output operation of the circuit of the embodiment shown in FIG. 3, and
  • FIG. 7 is a layout diagram of each 1 KB for explaining another embodiment of the relationship between the memory array and the SAM unit.
  • FIG. 1 is a block diagram showing one embodiment of a semiconductor memory device according to the present invention.
  • FIG. 2 is a schematic layout diagram for explaining an embodiment of the relationship between the memory array of FIG. 1 and the SAM section
  • FIG. 3 is a schematic layout diagram of the
  • FIG. 7 is a cross-sectional view of an element structure for explaining a semiconductor memory device S according to the present invention.
  • FIG. 8 is a schematic circuit diagram for explaining another embodiment of the relationship between the memory array and the SAM section in FIG. 2 described above.
  • FIG. 9 is a schematic circuit diagram for explaining still another embodiment of the relationship between the memory array and the SAM section in FIG. 2 described above.
  • FIG. FIG. 2 is a functional block diagram showing an embodiment in which the semiconductor memory device thus applied is applied to a computer system. BEST MODE FOR CARRYING OUT THE INVENTION
  • FIG. 1 is a block diagram of an embodiment of the semiconductor memory device according to the present invention.
  • the semiconductor memory device of this embodiment is directed to an image memory having a random input / output port and a serial input / output port.
  • Each circuit block shown in the figure is formed on one semiconductor substrate such as single crystal silicon by a known semiconductor integrated circuit manufacturing technique.
  • the X addressless buffer is an X (row) address signal input from address pins A0 to A9 in synchronization with the row address strobe signal ZRAS. And supplies the internal address signal to the X decoder.
  • the X decoder decodes it and selects one word line.
  • the X-decoder also includes a read driver for driving a read line having a large load capacity by connecting a large number of memory cells at a high speed.
  • the Y address buffer fetches a Y (column) address signal input from the address terminals A0 to A9 in synchronization with the column address strobe signal ZCAS and converts the internal address signal to the random Y decoder and serial address counter. Supply in the evening.
  • the random Y decoder decodes the address signal to form a bit di selection signal.
  • the serial address counter takes it as an initial value in the serial access mode.
  • a dynamic memory cell composed of a memory for address selection and a capacity for information storage is arranged in a matrix at an intersection of a read line and a bit Di (or a data line or a digit line).
  • the bit line is not particularly limited, but is a folded bit line system in which a pair of complementary bit lines are arranged so as to extend in parallel to the sense amplifier SA.
  • the bit lines are arranged so as to extend in the lateral direction of the memory array, and the code lines are arranged so as to extend in the longitudinal direction of the memory array.
  • This memory array is composed of a plurality (N) of memory mats or memory arrays.
  • the sense amplifier and I ZO BUS are provided corresponding to the bit lines of the memory array.
  • the sense amplifier amplifies a minute signal level difference read to the complementary bit line, and amplifies the potential of the complementary bit line to a high level and a low level corresponding to the power supply voltage and the circuit ground potential.
  • the read signal is amplified and the information storage capacitor constituting the memory cell is recovered by the read operation based on the lost information charge. Can be made.
  • the input / output line (IZO BUS) includes a column switch MOSFET connecting the bit line to the IZO BUS.
  • the selection signal generated by the Y decoder is supplied to the gate of the column switch M ⁇ SFET.
  • the IZO BUS is connected to an input terminal of an output buffer constituting a random boat.
  • the 4-bit random data is transmitted from the random boat terminals RI 00 to RI 03 through the output buffer. Is output.
  • the write data of the random input is transmitted to the IZO BUS through the input buffer.
  • the data is transmitted to the complementary bit line through the selected column switch, and the word line is written to the selected memory cell.
  • the storage circuit (SAM register) is essentially composed of a static RAM, and the transfer is performed to reduce the number of signal lines BUS used for data transfer from the memory array.
  • the gate divides the information of bit No. in the memory array and transfers it in a time-sharing manner. In other words, the remaining information is transmitted in a time-division manner through the signal line BUS, while the data of a plurality of bits which are firstly transferred in parallel are serially output.
  • the SAMY decoder decodes the serial output Y address signal formed by the serial address counter and supplies it to the gate of the selection switch MOSFET for selecting the storage information stored in the SAM register.
  • a selection signal is formed, read out to the serial input / output line SAM I / OB US, and output from the output terminals SIO0 to SI03 through the main amplifier SMA and the output buffer 0B.
  • the data input serially through the input buffer IB is transferred to the serial input / output line SAM It takes in the SAM register via I ZOBUS and transfers it to the memory array side in a time division manner via the transfer gate to perform the write operation.
  • the timing generation circuit receives signals ZRAS, CAS, DTZOE, / WE, DSF, SC and ZSE supplied from the outside, and generates various control signals and timing signals necessary for the operation of the internal circuit.
  • / RAS, / CAS, / WE, etc. the slash (/) attached is a signal that sets the mouth level to the active level.
  • a horizontal di is added above the character. It corresponds to being.
  • ZR AS and ZC AS are address strobe signals that take in the address signals as described above.
  • ZWE is a write enable signal. When it is set to high level during random access, read operation is performed, and when it is low level, write operation is performed.
  • DTZOE has two meanings: parallel transfer timing control, which sets the operation timing of the transfer gate according to the operation mode, and output enable control. However, since the parallel transfer of the transfer gate is performed a plurality of times in a time-sharing manner, the timing signal DTZOE controls the transfer start timing, and the subsequent transfer operation is not particularly limited. It is performed several times in synchronization with the transfer signal formed by the SAM decoder using the serial clock SC.
  • SC is a serial clock, and the serial address counter counts this and generates a serial address signal. That is, data is output from the serial output terminals SIO0 to SI03 in synchronization with the serial clock SC.
  • ZSE is a silylar enable signal. When this signal is turned to a high level, each circuit for serial output operation is activated, and the serial data output is performed as described above.
  • the serial clock SC in addition to such serial input / output, also connects the memory array with the SAM register. It is also used as a timing signal for performing a partial parallel transfer in.
  • the refresh counter starts operation by bringing ZCAS high when ZRAS is high, counts using the change in ZRAS as a clock, and generates an X-system address signal suitable for the refresh operation. .
  • the refresh address signal is supplied to the X decoder through the X address buffer, and the read and amplification of the memory cell is performed by the read line selection operation and the amplification operation of the sense amplifier, and is rewritten to the original memory cell. Is performed.
  • FIG. 2 shows layout diagrams for explaining an embodiment of the relationship between the memory array and the SAM unit.
  • the memory array is not particularly limited, but is composed of four memory mats MAT0 to MAT3.
  • Each of the memory mats MAT0 to MAT3 is of a so-called shared sense system. That is, memory arrays ARY-R and ARY-L are provided on the left and right of the sense amplifier SA, and the complementary bit lines of one of the memory arrays ARY-R or ARY-L on which the selected word line is provided are connected. Connected to sense amplifier SA.
  • a transfer gate circuit TG and a corresponding transfer bus BUS are provided adjacent to the sense amplifier SA.
  • the transfer bus BUS is arranged inside the transfer gate circuit TG so as to run in parallel with the extension direction of the guide line.
  • the transfer bus BUS of the memory mat MAT 3 located farthest from the common SAM register (SAMREG) of the VIAT 3 is the same as the memory mat MAT 0 with the common SAM register. ⁇ Arranged to run parallel to the MAT 3 array direction, in other words, the bit line extension direction. It is also connected appropriately to the internal bus of the transfer gate circuit TG of Matsuto MAT0 to MAT2.
  • 1,024 memory cells are connected to one word line of the memory array. If the storage information of the memory cells connected to one memory cell line in the memory array is transferred to the SAM register at one time as in the related art, 1,024 pairs of transfer buses are required. Therefore, in this embodiment, the SAM register is divided into eight to reduce the number of transfer buses BUS. In other words, it is divided into eight, as in # 0 to # 7, and one block has a storage capacity of 128 bits. By such eight divisions, the number of wires of the transfer bus BUS can be reduced to 128 pairs.
  • the SAM decoder 1 forms a parallel transfer signal of block-divided data between the memory array and the RAM register. In other words, for the selected memory mat, parallel transfer is performed at the SAM register via the transfer bus BUS in 128 times in 128 bits.
  • the SAM decoder 2 decodes the address signal formed by the serial address counter and forms a selection signal for selecting the stored information stored in the RAM register.
  • the upper three bits of the address signal of 10 bits formed by the serial address counter are used.
  • the signal is supplied to the SAM decoder 1, and 128-bit storage information including the storage information of the block corresponding to the storage information to be output first is transferred from the memory array to the SAIV [register]. Then, while the serial output of a maximum of 128 bits is being performed, the storage information of the remaining seven blocks forms an address stepping signal with the above 3-bit address as an initial value.
  • the SAM decoder 1 decodes the data and transfers it sequentially.
  • the sense amplifier SA of the selected one memory mat is reset, and the random access to the memory mat is permitted.
  • the other memory mats that do not perform the serial output can be accessed at any time in parallel with the serial output operation as long as the address input operation does not conflict.
  • the write signal fetched into the SAM register serially is divided into eight times via the transfer bus BUS, and the data for the 1-line is written. it can.
  • one transfer operation transfers only 1-8 storage information as described above.
  • FIG. 3 is a schematic circuit diagram for explaining one embodiment of the relationship between the memory array and the SAM unit.
  • the transmission signal in order to perform the above-described partial barrel transfer at a low power consumption and at a high speed, is not a full amplitude like a power supply voltage and a ground potential of a circuit as in the related art. Although not particularly limited, it should be performed with a small amplitude based on the midpoint voltage.
  • a pair of complementary signals of a high level such as the power supply E formed by the sense amplifier (SENSE AMP) and a low level such as the ground potential of the circuit is transferred to the transfer bus BUS via the switch MOSFET constituting the transfer gate circuit TG.
  • the transfer bus BUS is composed of a pair of signal lines. And is precharged by a precharge circuit. In other words, the MOSFET is short-circuited by the switch controlled by the precharge signal TPC, and at the same time, the midpoint voltage HVC is applied and half-blended in the same manner as the complementary bit line in the memory array.
  • the SAM register to which a signal is transmitted via the transfer bus BUS is illustratively shown as one circuit, and is composed of N-channel type M 0 SF ETQ1, Q2 and P-channel type MOSFETs Q3 and Q4, respectively.
  • the input and output of the pair of CM 0 S inverter circuits are cross-connected to form a latch configuration.
  • a switch MOSFET Q5 is provided at the common source of the N-channel MOSFETs Q1 and Q2, and when the MOSFET Q5 is turned on, the operation of the latch circuit is enabled.
  • a signal from the transfer bus BUS is transmitted to such a latch circuit via a MOSFET that is switch-controlled by a transfer signal TGL1 on the receiving side.
  • the potential of the input node similarly half-blended by the precharge circuit TG PC via the half-precharged transfer bus BUS corresponds to the high level of one of the potentials corresponding to the output of the sense amplifier.
  • the switch MOS FET is turned off by the transfer signal SL1 or TGL1 and the transfer operation is performed.
  • the transfer bus BUS is precharged by the precharge signal TPC.
  • the latch circuit sets the signal STG1 to a high level in response to the capture of the signal, turns on the MOSFET Q5, and amplifies and retains the captured signal.
  • the output of the other sense amplifier on the memory array side is synchronized with the transfer signal SL2.
  • the signal is transmitted to the bus BUS, and synchronously transmitted to the other latch circuits of the SAM register via the switch MOS FET which is turned on by the transfer signal TGL 2 or the like on the receiving side and transmitted in the same manner as described above. Amplification and retention are performed. By repeating such an operation eight times in the above-described embodiment, the transfer of the stored information corresponding to one card is completed.
  • the signal held in the latch circuit is read out to the SAM IZO through a switch MOSFET controlled by the serial selection signal SAMYS, and is activated by the serial enable signal SE. Output through SAM MAIN AMP).
  • the P-channel type MOSFET provided in SAM10 is a VCC precharge MOSFET for SAM IZO.
  • the memory array unit is symmetrically arranged around the SAM unit as described later.
  • a transfer bus BUS connected via a MOSFET that is switch-controlled by the signal TGR1 is provided corresponding to the other memory array unit (not shown). In the configuration as shown in the embodiment of FIG. 2, there is no such signal TGR1 and the corresponding switch MOSFET and transfer bus.
  • FIG. 4 is a schematic circuit diagram for explaining another embodiment of the relationship between the memory array and the SAM unit. This embodiment corresponds to the case where memory access is performed in 4-bit units as described above. Since 1 data consists of 4 bits, the minimum unit of transfer data must be performed 4 bits at a time, and correspondingly, the transfer bus BUS is also composed of 4 pairs, and the register of the SAM section has the minimum of 4 bits. You will receive it as a unit.
  • the transfer signals SL 1 and TG 1 cause one unit of data in the RAM
  • the data is transferred to the unit circuit REG 1 of the SAM register, and then another unit of data in the RAM section is transferred to the unit circuit REG 2 of the SAM register by the transfer signals SL 2 and TG 2 using the same transfer bus BUS. It is made to be.
  • the SAM register is divided into eight as described above, the same operation as described above is repeated eight times using the same transfer bus BUS.
  • the number of transfers (for example, 8) and the number of registers (8 sets) are not limited to being the same, and the number of registers can be smaller than the number of transfers. In this case, if the transfer to the register and the data output from the register are processed in parallel, the number of registers can be reduced.
  • FIG. 5 is a timing chart for explaining an example of the serial output operation of the embodiment circuit of FIG.
  • the shared selection signal SHL is selected and the corresponding memory cell ARY-L is selected, the small signal according to the storage information of the selected memory cell appears on the complementary bit line BLL.
  • the sense amplifier When the sense amplifier starts the amplifying operation, it amplifies the minute signal of the complementary bit Di BLL to form a high level such as a power supply voltage and a ground potential of the circuit and an open level. This is received by the memory cell as it is, so that the storage charge which has been lost by the read operation and is restored to the original state.
  • the transfer signals TGL and SL corresponding to the divided block of the SAM register corresponding to the Y address to be output first are formed, and the corresponding signal appears on the transfer bus BUS.
  • the SAM register when the signal required to capture the input is reached, the above-mentioned transfer signal TGL and SL are reset, and the precharge signal of the transfer bus BUS etc. A TPC is formed, and the transfer bus BUS is half-charged.
  • the SAM register amplifies the captured input signal and holds the data. Then, the serial selection signal SAMYS is generated in synchronization with the serial clock, and the held signal of the SAM register held by the transferred stored information is sequentially passed through the serial input / output line SAM I 0. Is output.
  • the memory array side resets the word line WLL / shade select signal SHL when the write operation to the memory cell is completed, and accordingly, the bit line BLL is also reset. Half recharged. However, the sense amplifier maintains the operating state until the data transfer for one word line is completed, and functions as a storage circuit.
  • FIG. 6 is a 1 KB layout diagram for explaining another embodiment of the relationship between the memory array and the SAM unit.
  • the memory mat in order to shorten the substantial length of the transfer noise between the memory array and the SAM unit, the memory mat is divided into two around the SAM unit and arranged symmetrically. That is, the memory mats MAT0 and MAT1 are arranged on the lower side (left side), and the memory mats MAT2 and MAT3 are arranged on the upper side (right side).
  • the signal dit lengths of the memory mats MAT1 and MAT3 located farthest from the SAM section are equal to those of the memory mat MAT located farthest in the embodiment of FIG. It can be shortened to about half the length compared to 3. As a result, the data transfer speed can be increased.
  • the current required to form the same signal level is halved, in addition to the above-mentioned improvement in signal transfer speed due to the reduction in load capacity. Because it can be destroyed, low power consumption can also be realized.
  • FIG. 7 is a sectional view of an element structure for explaining a semiconductor memory device according to the present invention.
  • the element structure of the array part and the peripheral part in the above-mentioned dynamic RAM is exemplarily shown as a representative.
  • the storage capacitor of the memory cell uses the second polysilicon layer SG as a storage node and is connected to one of the source and drain of the address selection MOSFET.
  • the second polysilicon layer has a fin structure, and is constituted by a thin electrode made of a third polysilicon layer TG via a thin gate insulating film.
  • the gate of the address selection MOSFET is composed of the first polysilicon layer FG.
  • the other source and drain of the address selection MOSFET are FG, SG and TG
  • the metal wiring layer MH such as aluminum for the first employment, is connected through the intermediary of the metal.
  • the l3 ⁇ 4S layer Ml constitutes a bit line (or data line or digit line).
  • Two N-channel type MOSFETs are formed in the periphery.
  • the first layer Ml is connected to the source and drain of the MOSFET by a contact LCNT. Alternatively, it is connected to the first-layer polysilicon FG by a contact FCNT.
  • the first wiring layer Ml and the second wiring layer M2 are connected via the first through hole TH1, and the second wiring layer M2 and the third wiring layer M3 are connected. Is connected via the second through hole TH2.
  • the first wiring layer Ml as a dummy through the first through hole TH1 is used as described above.
  • the first layer wiring ⁇ Ml and the contact LCNT are connected to the first layer polysilicon FG as a gate electrode.
  • the third wiring layer M3 for supplying an input signal is connected to the second wiring layer M2 via the second through hole TH2.
  • the first wiring layer Ml is connected to the second wiring layer M2 as a dummy through the first through hole TH1
  • the wiring is guided to the third wiring layer M3 via the second through hole TH2 with the wiring layer M2 interposed.
  • the transfer bus BUS When a memory circuit is formed using three layers of metal wirings M 1, ⁇ 2, and 1 ⁇ 3 such as aluminum, the transfer bus BUS also has three wiring layers M 1 to M 3. By using a multilayer structure, a substantial wiring area can be reduced. For example, in the case of a 128-bit transfer bus BUS as described above, the bus Can be configured by width.
  • the above polysilicon layer may also be used for the transfer bus BUS.
  • the first and second layers or the second and third layers are arranged in parallel in a polysilicon layer whose resistance per unit area is relatively higher than that of the aluminum layer. To reduce the resistance value.
  • the above-mentioned 128-bit signal can be realized with a bus width of 32 bits.
  • the circuit can be simplified by using the SAM section in common for multiple memory mats or memory arrays. Become.
  • the transfer bus in a laminated structure with the multi-layer wiring required for the memory circuit, the increase in the occupied area can be substantially prevented from becoming a problem.
  • FIG. 8 is a schematic circuit diagram for explaining another embodiment of the relationship between the memory array and the SAM unit.
  • the small-amplitude high-speed transfer bus is constituted by one signal line.
  • the latch circuit including the MOSFETs Q1 to Q4 amplifies and holds the transferred small-amplitude signal using the half precharge voltage HVC as a reference voltage.
  • FIG. 9 is a schematic circuit diagram for explaining still another embodiment of the relationship between the memory array and the SAM section.
  • the small-amplitude high-speed transfer bus is constituted by one signal line. As a result, the number of transfer signal lines can be reduced to half as described above.
  • FIG. 10 is a functional block diagram of an embodiment in which a semiconductor memory device (image memory VRAM) to which the present invention is applied is applied to a computer system.
  • a semiconductor memory device image memory VRAM
  • Bus and central processing unit SCPU peripheral device control unit
  • DRAM dynamic memory
  • SRAM static memory
  • backup parity and its control unit program
  • This computer system is composed of a ROM (read 'only' memory) in which is stored and a display system.
  • the peripheral device control unit is connected to an external storage device, a keyboard KB, and the like.
  • the display system is constituted by a VRAM or the like using a semiconductor memory device having a RAM section and a SAM section as in the above-described embodiment, and is connected to a display as an output device for writing. Display billion information.
  • a power supply for supplying power to the internal circuit of the computer system is provided.
  • the central processing unit CPU controls the operation timing of each memory by forming a signal for controlling each memory.
  • a memory circuit for serial input / output which is commonly used is provided for a plurality of memory arrays including a plurality of memory cells arranged in a matrix and a sense amplifier for amplifying a small signal thereof, and The amplified signal is divided into a plurality of blocks and transferred in a time series to the corresponding storage bits of the storage circuit as a signal amplitude sufficiently reduced with respect to the power supply voltage.
  • the serial output operation is started by synchronizing the transferred stored information with the clock signal.
  • time-sequential signal transmission and its signal transmission are performed with a small amplitude by dividing into a plurality of blocks, thereby reducing wiring.
  • the number makes it possible to perform substantially parallel transfer, and it is also possible to display windows across multiple memory arrays by using such partial transfer operations, and to use a common serial I / O storage circuit.
  • the simplification of the circuit is also used.
  • the transfer signal transferred by the transfer circuit for example, the output signal of the sense amplifier is transmitted to a transfer node charged to about 1/2 of the power supply voltage, and the transfer signal is operated by a timing signal.
  • the CMOS latch circuit which constitutes the storage circuit, is input to the input by the above timing signal, with a simple circuit that stops the output when the input is input to the controlled CM0S latch circuit.
  • the transfer node between the storage circuit and the memory array can be shortened, thereby increasing the speed and reducing the power consumption. Electricity can be achieved.
  • the transfer bus By arranging the transfer bus in a laminated structure using the multilayer wiring forming the memory array section, the area occupied by the transfer bus can be significantly reduced.
  • the above-described semiconductor memory device can adopt various embodiments.
  • the configuration of the memory array or the memory mat can employ various embodiments such as a configuration in which a sense amplifier is directly connected to each bit line of the memory array, in addition to the above-described shared sense amplifier.
  • the precharge level of the small-amplitude high-speed transfer bus is not limited to the midpoint voltage H VC, but may be a ground potential or a power supply voltage V CC.
  • the configuration of the SAM section is for serial output using a shift register.
  • various embodiments in which the serial selection signal SAMYS is formed by a shift register or a pointer can be adopted.
  • the serial input function may be omitted.
  • the semiconductor memory device can be widely used for a two-port memory including a RAM section and a SAM section, such as an image memory in a microcomputer system.

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Abstract

Cette invention concerne une mémoire à semi-conducteurs qui comprend, d'une part, plusieurs réseaux de mémoires contenant chacun plusieurs cellules mémoires disposées en forme de matrice ainsi que des amplificateurs de détection pour amplifier les signaux faibles, et, d'autre part, un circuit de mémoire commun pour les entrées et les sorties en série. Les signaux amplifiés par les amplificateurs de détection, et qui ont une amplitude bien inférieure à celle de la tension d'alimentation, sont transmis en blocs selon un système de partage de temps vers les bits correspondants du circuit de mémoire susmentionné. Dans un même temps, les signaux transmis à ce circuit de mémoire sont sortis en série et en synchronisation avec les signaux d'horloge. Cette transmission de faibles signaux en blocs et par partage de temps permet d'obtenir sensiblement les mêmes résultats qu'avec une transmission en parallèle, même si l'on utilise moins de lignes de signaux. En faisant appel à des opérations de transmission de ce type, il est désormais possible d'obtenir un affichage en fenêtre tout en disposant de plusieurs réseaux de mémoire. En outre, il est possible de simplifier un circuit en utilisant en commun le circuit de mémoire pour les entrées et les sorties en série.
PCT/JP1995/001899 1995-01-30 1995-09-21 Memoire a semi-conducteurs WO1996024136A1 (fr)

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JP3178895 1995-01-30
JP7/31788 1995-01-30

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JPS62231495A (ja) * 1986-03-31 1987-10-12 Toshiba Corp 半導体記憶装置
JPS62271291A (ja) * 1986-05-20 1987-11-25 Ascii Corp メモリ装置
JPS6410495A (en) * 1987-07-01 1989-01-13 Matsushita Electric Ind Co Ltd Readout circuit for dynamic ram
JPH03234055A (ja) * 1990-02-09 1991-10-18 Hitachi Ltd 半導体集積回路装置

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JPS62192086A (ja) * 1986-02-18 1987-08-22 Matsushita Electronics Corp 半導体記憶装置
JPS62224065A (ja) * 1986-03-26 1987-10-02 Hitachi Ltd 半導体集積回路装置及びその製造方法
JPS62231495A (ja) * 1986-03-31 1987-10-12 Toshiba Corp 半導体記憶装置
JPS62271291A (ja) * 1986-05-20 1987-11-25 Ascii Corp メモリ装置
JPS6410495A (en) * 1987-07-01 1989-01-13 Matsushita Electric Ind Co Ltd Readout circuit for dynamic ram
JPH03234055A (ja) * 1990-02-09 1991-10-18 Hitachi Ltd 半導体集積回路装置

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