Classifications

• • G—PHYSICS
  • G06—COMPUTING; CALCULATING OR COUNTING
  • G06F—ELECTRIC DIGITAL DATA PROCESSING
  • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
  • G06F13/38—Information transfer, e.g. on bus
  • G06F13/40—Bus structure
  • G06F13/4063—Device-to-bus coupling
  • G06F13/409—Mechanical coupling
• • H—ELECTRICITY
  • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
  • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
  • H05K7/00—Constructional details common to different types of electric apparatus
  • H05K7/14—Mounting supporting structure in casing or on frame or rack
  • H05K7/1438—Back panels or connecting means therefor; Terminals; Coding means to avoid wrong insertion
  • H05K7/1439—Back panel mother boards
  • H05K7/1442—Back panel mother boards with a radial structure

Definitions

• the invention is a method including a structure, and further structures for connecting electrical elements, for shortening the physical and electrical dis ⁇ tances between adjacent electronic elements which process electrical signals having very fast transition times, includ ⁇ ing sub-nanosecond transition times.
• the structure of the pre ⁇ sent invention significantly reduces unwanted reflections of said signal on the balance of said lines at said common point.
• a connector structure and a novel arrangement of a multiplicity of said connector structures, for shortening the physical and electri ⁇ cal distances between adjacent printed circuit (hereinafter "PC") boards mounting integrated circuit (hereinafter “IC”) chips. Further, it includes a connector for connecting flex ⁇ ible ribbon connector cables between such boards, and for a novel arrangement of a multiplicity of connectors to increase processing rates for said sub-nanosecond electrical signals.
• PC printed circuit
• IC integrated circuit
• processing rate (the inverse of time to add, subtract, multiply, divide, etc., two numbers) is of great importance.
• Processing rate is inversely proportional to transition time, i.e., the time it takes an electronic ele ⁇ ment to switch between "ON" and "OFF".
• transition time i.e., the time it takes an electronic ele ⁇ ment to switch between "ON” and "OFF".
• transition times have decreased to sub-nanosecond figures, with a resul- tant potential increase in processing rates, the speed with which electronic signals propagate along conductors is fixed by the velocity of light.
• physical distances separating circuit elements become increasingly significant, with respect to time, for a signal to go from one point to another in a circuit. Reducing this distance by one-half can, in certain circumstances, actually have the effect of nearly doubling system processing rate.
• processing rates of advanced electronic sys ⁇ tems can be limited by sheer physical separation, such as the distances between:
• FIGS. 2 and 10 discloses a 'star' or 'asterisk' connection which is superficially similar to that of the present invention.
• the leads in Coe are self- supporting, relatively massive structures with necessarily large associated stray reactive values, causing unavoidable degradation of electrical signals sent along them, whereas the present invention allows order-of-magnitude reductions of size and of associated reactive values, thus increasing the processing rate of the basic device.
• Coe '872 also may be relevant to the radial arrangement of PC boards, below.
• Takashima patents (5,060,111; 5,091,822; 5,210,060, and 5,301,089) all disclose a radial connection system which superfically resembles the soldered or welded connection configuration of the present invention.
• the present invention permits substantially an order of reduc ⁇ tion in lead dimension over Takashima, allows access to the common bus in the middle of the structure, and permits a substantial reduction in complexity.
• Takashima 5,301,089 discloses a radial connection system which is a PC configuration, incorporating a radial bus assembly containing a cross-bar switch for distributing sig ⁇ nals to the various PC boards.
• the cross-bar switch of this reference cannot be considered to be analogous to the asterisk connection of the present invention. (Takashima '089 may also be relevant to the PC board arrangement, below.)
• Heuer 2,971,179 discloses a female connector for re ⁇ ceiving PC boards or flexible flat cables. The structure of the present invention is distinguishable.
• Jerominek 3,737,833 discloses a female connector for use with flexible flat cables.
• the structure of the present invention is distinguishable.
• Roberts et al 4,740,867 discloses a female connector for connecting a flexible flat ribbon cable to a PC board.
• the present invention is distinguishable.
• Weidler 4,995,814 discloses a female interconnector for connecting two blade-shaped members such as PC boards, flat cables, or a combination thereof, to each other.
• the structure of the present invention is distinguishable.
• Dambach et al 5,194,010, FIG. 3 discloses a female connector for interconnecting flat cables, boards, etc.
• the structure of the present invention is distinguishable.
• (Dam ⁇ bach et al '010 may "e relevance to interconnecting flat cables, below. )
• Frankeny et al 5,205,740 discloses an interconnector for connecting flat ribbon cables together. It has na rele ⁇ vance to the present invention.
• Matschke et al 5,276,817 discloses an interconnector for connecting PC boards and flat cables together.
• FIG. 2 thereof is the only portion of this disclosure having even a superficial relevance to the present invention, and is distinguishable.
• Carter 3,660,728 discloses a conductor interconnec ⁇ tion system for flat cables. It has only a superficial rele ⁇ vance to the present invention and is distinguishable.
• Weidler 4,995,814 discloses an interconnector for two blade-shaped circuit members such as boards, flat cables, or a combination thereof, and is distinguishable from the pre ⁇ sent invention. (This may have relevance to female connectors, above. )
• Dambach et al 5,194,010, FIG. 3 discloses a connec ⁇ tor for interconnecting flat cables, boards, etc., together. Dambach et al is distinguishable from the present invention. (This may also have relevance to female connectors, above.)
• Sobhani 5,213,511 has only a superficial relevance to the present invention, and is distinguishable therefrom.
• Coe 4,679,872 discloses an arrangement of PC boards around a radial bus assembly.
• One of the specific purposes of Coe is to reduce the stray capacitances and inductances of high speed circuitry by reducing the length of interconnecting leads (Col. 1, Ins 41-58; col. 7, Ins. 6-15).
• the present invention is distinguishable.
• Takashima 5,301,089 discloses an arrangement of PC boards around a radial bus assembly which contains a cross-bar switch distributing signals to the various PC boards.
• a cross ⁇ bar switch is not an equivalent of the structure of the pre ⁇ sent invention.
• the present invention includes a structure for ob ⁇ taining reduced reflections at a common point from any of a multiplicity of signal lines having similar characteristic im ⁇ pedances connected to the common point.
• electrical sig ⁇ nals including signals having transition times of substanti- ally less than one nanosecond, are introduced from one of the signal lines into the balance of the lines, reflections at the common point from discontinuities of any kind in any of the lines are greatly reduced, and do not significantly affect the original signal.
• the multiplicity of lines radiates sym ⁇ metrically from the common point in a planar, or asterisk, fashion, although they could also radiate in a dandelion fashion.
• the asterisk arrangement When the asterisk arrangement is used, it is poss ⁇ ible to connect the line from the signal source to the common point orthogonally to the plane, which insures that the stray reactances from the balance of the lines are equally distributed.
• This feature alone of the present invention makes possible a performance improvement of up to twenty-fold in processing rates, by reducing the signal path length from PC board to PC board, by equalizing the path lengths, by allowing access to the common bus at other points of a PC board than the input, by minimizing the loading effects of intervening circuitry connected to the signal paths, and by substantially reducing structural complexity.
• the female connector for receiving a thin flat connector such as the edge of a PC board or the end of a flat flexible ribbon cable.
• the female connector is comprised of two halves which are mirror images of each other. Each half includes a body of two parallel longitudinal members each having a foot end and a head end. Each foot end has a toe portion which extends out ⁇ wardly from the longitudinal body, and the toe portions of the two halves are abutted to one another to form the connector.
• the head ends are fabricated into a head member which extends transversely to the head ends of the longitudinal members and to the toe, and the foot ends are fabricated into a foot mem ⁇ ber which also extends transversely thereto and to the toe, and parallel to the head member.
• the head member has canti- levered therefrom a resilient arced member which extends to- ward the foot member substantially parallel to the longitudi ⁇ nal body, with the arced member having a convex surface and a concave surface, and an electrical conductor connected to the convex surface as hereinafter described.
• the convex surfaces of the arced members face and curve toward one another so that a PC board or a flat flexible ribbon cable end inserted there ⁇ between will force the cantilevered members apart, stressing them and thereby gripping the flat connector between them.
• the facing surfaces of the resilient arced members may have bonded thereto metallic facings which form the electrical terminals which conductively mate with electrical surfaces on the PC boards and the like. The toe portions act as a stop member to the inserted PC board.
• a multi-conductor connector which will receive a PC board or a multi-conductor flat flexible cable or the like, is formed when the head and foot members are extended transverse ⁇ ly with a multiplicity of longitudinal members fabricated therebetween, and cantilevered members extending between each pair of longitudinal members.
• a third feature of the present invention is a struc ⁇ ture for distributing short rise-time electrical signals, in ⁇ cluding those having transition times of substantially less than one nanoscond.
• the structure includes a multiplicity of flat flexible circuit cables having a multiplicity of extended metallic conductors on at least two surfaces. The surfaces are separated from one another by insulation.
• Each of the cables has thereon a multiplicity of electrically conducting extended conductors or traces, one or more of whi ⁇ end in electrical connectors, which serve to connect the traces to sources of electrical energy, to other electrical elements, as well as to sources of electrical signals having rapid transition times, including sub-nanosecond transition times.
• Each of the exten ⁇ ded traces includes one or more connection points intermedi- ate to the ends thereof, one or more of which have apertures extending between said surfaces of the cables. At least one of the apertures has electrical conductors extending through the cable and conductively connecting to one or more connection points on the other surface of the cable, or to adjacent c _es.
• present invention i.- a novel way of arranging PC boards so as to obtain minimum separation - i.e., maximum packing - and more efficient cool ⁇ ing, and also a novel way of connecting them together so as to obtain maximum processing rates of overall operation. It accomplishes this with minimum deterioration, including 'stretching', of the electrical signals, caused by the loading effects of attaching additional circuits to the signal lines between them.
• FIG. l discloses a typical existing method of the prior art for arranging a multiplicity of PC boards.
• FIG. 2A discloses a 'star' or 'asterisk' structure, the primary structure of the present invention.
• FIG. 2B discloses an alternate, 'dandelion', struc ⁇ ture of the present invention.
• FIGS. 3A-C disclose the structure of the female con ⁇ nector feature of the present invention: - FIG. 3A discloses the structure of one-half of the female connector of the present invention, the other half being a mirror image thereof;
• FIGS. 3B1-3B3 disclose the structure and operation of the female connector of the present invention: - FIG. 3BI discloses one half of the female connector;
• FIG. 3BII discloses the mirror image of 3BI
• FIG. 3BIII discloses both halves of the female connector assembled, with a flat connector inserted therein;
• FIG. 3C discloses the structure of the female connector when attaching a finger of a flat flexible ribbon cable thereto.
• FIGS. 4A-D disclose the structure of a multiplicity (FIGS. 4A-D descriptions, continued):
• FIG. 4A discloses an exploded view of the structure when 5 attaching a multiplicity of fingers of a flat flexible ribbon cable to a multi-conductor female connector;
• FIG. 4B discloses an exploded view of a pair of connector blocks for clamping together a multiplicity of ribbon cables, each connecting a pair of multi-conductor female
• FIG. 4C discloses how a multiplicity of multi-conductor female connectors, as disclosed in FIG. 4A, are clamped together as disclosed in FIG. 4B;
• FIG. 4D discloses how edge-terminaled PC boards are 15 inserted in the assembly of FIG. 4C.
• FIGS. 5A and 5B disclose the structure of a multi ⁇ plicity of multi-conductor female connectors which are ar ⁇ ranged in a circular or cylindrical arrangement , with INPUT/ OUTPUT connectors connected thereto: 20 - FIG. 5A discloses the structure of a multiplicity of flexible ribbon cables having multi-conductor female connectors on the ends thereof which are clamped to ⁇ gether and interconnected with a pair of INPUT/OUTPUT connectors; and 25 - FIG. 5B discloses the structure of an assembled INPUT/ OUTPUT structure, including a multiplicity of multiple- conductor female connectors, each having a PC board (FIG. 5B description, continued):
• FIG. 6 discloses an assemblage of PC boards, inser ⁇ ted into an assembled INPUT/OUTPUT structure as disclosed 5 in FIG. 5B.
• FIG. l is an illustration of a typical prior art structure for arranging and connecting a multiplicity of PC
• a master board, or 'motherboard' contains circuitry which controls the interaction between, and operation of, the separate dependent boards, which are called 'daughterboards' (for obvious reasons) .
• the daughterboards interface with the motherboard through two rows of multi-conductor sockets shown
• the wiring interconnecting the various sockets - and the motherboard control circuitry - will be printed on one or more surfaces (sometimes internal) of the motherboard.
• 'Rise-time' and 'fall-time' are the times required for a electrical signal to switch between minimum and maximum voltage levels, and vice versa. Propagation delay time each way thus becomes about 2.2.nsec, or 4.4 nsec overall, result ⁇ ing in a theoretical maximum processing rate of 227 MHZ (megahertz, or millions of cycles per second), even with an impossible allowance of zero time fo: -ocess-delay times at the receiving ends of the signal pati
• the present invention makes possible a performance improvement of up to twenty-fold in processing rates, by re- ducing signal path lengths from PC board to PC board and by equalizing them, and by minimizing the loading effects of in ⁇ tervening circuitry connected to the signal paths, and by re ⁇ ducing structural complexity.
• a novel method has been discovered for making electrical connections in high processing-rate electrical cir ⁇ cuits. This is useful when it is required to connect a num ⁇ ber of parallel lines having similar values of controlled impedance, so that any one of these lines may be used as the signal input - the 'SEND' line - feeding the remainder of the lines - the 'RECEIVE' lines.
• This new method of connection gives little or no practical distortion of the electrical sig ⁇ nal at the receiving end of the lines, and actually gives bet ⁇ ter results as the number of receiving signal paths increases (which is the reverse effect of existing methods of connection of the motherboard/daughterboard arrangements illustrated in FIG. 1).
• the basic invention is disclosed in FIG. 2, and is a structural method of making electrical connections for use in electrical circuits, especially high-speed digital circuits for processing electrical signals having very short transition times, i.e., less than one nanosecond.
• the structure works with slower signals, but is especially effective with very high-speed signals.
• present invention 10 is a structure for connecting at a common point 12 a multiplicity N of signal lines 14A . . . 14N, each having similar charac ⁇ teristic impedances. This ⁇ ucture will greatly reduce, at common point 12, reflections-, from terminating impedances 16A . . . 16N at far ends 18A . . . 18N of lines 14A . . . 14N, when a current signal of magnitude A having very short tran ⁇ sition times is introduced from one of said lines 14A into the balance, 14B . . . 14N, of said lines. Because present invention 10 is comprised of a mul ⁇ tiplicity N of lines 14A . . .
• the signal current provided by any one >f lines 14a . . . 14n will divide equally among all lines. Any mismatch of impedances which any one of the signals encounters as it propagates down the lines will cause a reflection to travel back to common point 12.
• the signal causing the reflection is only 1/Nth as large as the initial signal, and because impedance-matching terminations are pro ⁇ vided at the end of each line 14a . . . 14n, the reflection which will be seen at common point 12 will be small and, in a digital circuit, will not be sufficient to cause any signifi ⁇ cant distortior aereof.
• connection 10 is with lines 14A . . . 4N arranged symmetrically in a nominally planar fashion about common point 12 in a 'star' or 'asterisk' pattern.
• One of the lines 14A can be used as input in that ar ⁇ rangement, or it could enter axially at common point 12, or ⁇ thogonally to the plane of lines 14B . . . 14N, which would insure uniform stray capacitive and inductive reactances for each of the lines 14B . . . 14N and, additionally, would be delayed only by half-network propogation delay-time.
• the structure can be obtained by any of several fab ⁇ rication techniques. These can range from a simple soldered or welded connection of a multiplicity N of central coaxial con ⁇ ductors 20A . . . 2ON arranged symmetrically about common point 12, to a machined fixture with coaxial connectors incor ⁇ porating the basic structure therein, and even including a star or asterisk structure fabricated by integrated circuit technology on an IC microchip. Upon reflection, it will be realized by those skilled in the art that signal lead-lengths can be obtained which are extremely short, and that process ⁇ ing rates can be achieved that are as great as twenty times those presently available.
• such an arrangement of a multiplicity of signal lines could accomodate as many conductors as can physically be connected at one point, and might be called a 'dandelion' structure because of the internal structure.
• the structure would be adaptable to fiber optic technology.
• FIGS. 3A-D disclose another feature of the present invention, female electrical connector 30, for receiving thin flat connector 32, which can be the edge of a PC board or the end of a flat flexible ribbon cable.
• Female connector 30 is comprised of two halves 34a and 34b, which are mirror images of each other. Each half includes a body of two parallel lon ⁇ gitudinal members 36a and 36b, each having head end 38a and foot end 38b. Longitudinal members 36a and 36b have thereon toe portions 40a and 40b, respectively, extending outwardly from foot end 38b. Toe portions 40a and 40b are fixedly abut ⁇ ted to one another to form the complete connector, as dis ⁇ closed in FIG. 3BIII.
• Longitudinal members 36a and 36b have fabricated to head ends 38a, head member 42 which extends transversely thereto, and foot ends 38b of members 36a and 36b have fabricated to foot ends 38b, foot member 44 which also extends transversely to members 36a and 36b and to toes 40a and 40b, both respectively. Head member 42 and foot member 44 are substantially parallel.
• Head member 42 has cantilevered therefrom resilient arced member 46 which extends toward foot member 44 substanti ⁇ ally parallel to longitudinal members 36a and 36b.
• Arced mem- ber 46 has thereon convex surface 48 and concave surface 50.
• An electrical conductor is affixed to convex surface 48 as hereinafter described.
• Female connector 30 is formed of longitudinal mem ⁇ bers 36a and 36b, head member 42 and foot member 44, and arced member 46a cantilevered from head member 42, and a mirror image thereof, as disclosed in FIG. 3BIII.
• each half could be fabricated as a unitary body of a tough resili ⁇ ent plastic material such as RYTON or XYDAR plastics.
• convex surfaces 48a and 48b of the arced members face and extend to ⁇ ward one another, as disclosed in FIG.
• Facing surfaces 48a and 48b of resilient arced mem ⁇ bers 46a and 46b, respectively, will have bonded or otherwise affixed thereto metallic facings which form the electrical terminals which conductively mate with electrical surfaces on thin flat connector 32 and the like.
• Toe portions 40a and 40b act as a stop member to inserted connector 32.
• a multi-conductor connector which will receive a PC board or a multi-conductor flat flexible cable or the like, is formed when head member 42 and foot member 44 are extended transv jly with a multiplicity of longitudinal members 36a and 36b fabricated therebetween.
• Cantilevered members 46a and 46b will be located between each pair of longitudinal members 36a and 36b.
• FIGS. 3BI, 3BII, 3BIII, and 3C disclose how ribbon cable 'fingers' 52a and 52b are bonded to convex surfaces 48a and 48b of cantilever members 46a and 46b, all respectively. Bonding can be done by any method well-known in the art, such as with an epoxy ce- nt, which will give a permanent bond which will withstar.- repeated insertions and withdrawals.
• Contact with electrical conductors on other ribbon cables or PC boards is made through connector 56, by means to be described in connection with FIGS. 4A-D, hereinafter.
• ac * ve conductor 58 is connected to terminal 52a by jumper 60, which may con- tain signal processing electronics.
• Conductor 58 is balanced on the opposite surface of cable 54 by ground plane conductors 60a and 60b, in accordance with the teaching of of U.S. Patent 4,680,557, issued July 24, 1987 to the applicant herein.
• FIGS. 4A-4D disclose a structure made possible by the multi-conductor female connector descri b ed hereinbefore in connection with FIGS. 3A-3C.
• FIG. 4A discloses multi-conductor connector 56, at ⁇ tached to prior-art microstrip cable 62, with signal conduc ⁇ tors 58a . . . 58f balanced by active power and/or grou .d conductors 60a . . . 60f.
• FIG. 4B discloses an exploded view of a multiplicity of multi-conductor connectors 56a . . . 56n, disclosing the structure of a multi-connector terminal for interconnecting a muliplicity of PC boards.
• Each multi-conductor connector 56a . . . 56n is connected to another of said connectors by flat flexible ribbon cables 64a . . . 64n, which can be cable 54 of FIG. 3C, or any other existing cable, e.g., prior-art micro- strip cable 62 of FIG. 4A, other flat flexible ribbon cable presently known in the art or which may be developed in the future, or any combination thereof.
• Insulating separators 74a . . . 74n provide electrical separation between cables 64a . . . 64n, which are pressed together by pressure-blocks 68 and 70, and clamped together by appropriate means.
• FIG. 4C discloses the assembled structure shown in exploded form in FIG. 4B. Pressure blocks 68 and 70 press cables 64a . . . 64n tightly together, and multi-conductor female connectors 56a . . . 56n fan out radially into a cylin ⁇ drical form, as shown, ready to receive PC boards.
• FIG. 4D discloses PC boards 32a . . . 32n, inserted into connectors 56a . . . 56n, with PC board 32n+l ready to be inserted into connector 56n+l.
• FIG. 5A discloses, in exploded view, another embodi ⁇ ment of FIG. 4D, wherein pressure-blocks 68 and 70, and con- nector block 72 therein, are replaced by INPUT/OUTPUT (I/O) connector 78 and POWER connector 80.
• I/O INPUT/OUTPUT
• Conductive pins 82a . . . 82n of I/O connector 78, and pins 84a . . . 84n of POWER con ⁇ nector 80 perform the same functions as electrically conduct ⁇ ing pins 76a . . . 76n of connector block 72.
• FIG. 5B discloses the assembled structure of FIG.
• FIG. 6 discloses an assembled multi-board system constructed according to the teachings of the present inven- tion.
• POWER connector 80 is located at the base, and I/O con ⁇ nector 78 is located at the upper end.
• PC boards 32a . . . 32n are inserted into multi-conductor female connectors 56a . . . 56n.
• Multiple star or asterisk connectors 10 are connected at many points internally from the top to the bottom of the structure.
• Appropriate cooling functions are located in the top 82, and shaped shields direct the flow of air around the temperature-sensitive components on PC boards 32a . . . 32n, to keep the internal temperature within safe, proper operating limits.
• External shields 84 which can be transparent or opaque, protect the internal components.

Landscapes

• Engineering & Computer Science (AREA)
• General Engineering & Computer Science (AREA)
• Theoretical Computer Science (AREA)
• Microelectronics & Electronic Packaging (AREA)
• Computer Hardware Design (AREA)
• Physics & Mathematics (AREA)
• General Physics & Mathematics (AREA)
• Coupling Device And Connection With Printed Circuit (AREA)
• Electronic Switches (AREA)

Priority Applications (15)

Applications Claiming Priority (2)

Publications (1)

Family

ID=25664640

Family Applications (1)

Country Status (13)

Cited By (1)

Families Citing this family (2)

Citations (3)

Family Cites Families (5)

• 1994
  • 1994-09-20 CZ CZ961801A patent/CZ180196A3/cs unknown
  • 1994-09-20 AU AU34644/95A patent/AU3464495A/en not_active Abandoned
  • 1994-09-20 JP JP8510833A patent/JPH09510044A/ja active Pending
  • 1994-09-20 BR BR9408102A patent/BR9408102A/pt not_active IP Right Cessation
  • 1994-09-20 WO PCT/US1994/010593 patent/WO1996009750A1/en not_active Application Discontinuation
  • 1994-09-20 SK SK816-96A patent/SK81696A3/sk unknown
  • 1994-09-20 EP EP94929254A patent/EP0734643A4/de not_active Ceased
• 1995
  • 1995-08-29 ZA ZA957230A patent/ZA957230B/xx unknown
  • 1995-09-01 IL IL11514095A patent/IL115140A/xx not_active IP Right Cessation
  • 1995-09-18 HR HRPTC/US94/10593A patent/HRP950481A2/hr not_active Application Discontinuation
  • 1995-09-19 TR TR95/01141A patent/TR199501141A2/xx unknown
• 1996
  • 1996-05-15 NO NO962013A patent/NO962013L/no not_active Application Discontinuation
  • 1996-05-17 FI FI962098A patent/FI962098A/fi unknown

Patent Citations (3)

Non-Patent Citations (1)

Also Published As

Similar Documents

Legal Events