AU1636999A - Data processing device - Google Patents

Description

S F Ref: 342977D1

AUSTRALIA

PATENTS ACT 1990 COMPLETE SPECIFCATOi FOR A STANDARD PATENT

ORIGINAL

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r i Name and Address of Applicant: Actual Inventor(s): Address for Service: Invention Title: Peter M. Compton 14481 S.W. Arabian Drive Beaverton Oregon 97005 UNITED STATES OF AMERICA Peter M. Compton Spruson Ferguson, Patent Attorneys Level 33 St Martins Tower, 31 Market Street Sydney, New South Wales, 2000, Australia Data Processing Device .4 I

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The following statement Is a full description of this invention, including the best method of performing it known to me/us:i4 DATA PROCESSING DEVICE In general, the invention is a method including a structure, and further structures for connecting electrical elements, for shortening the physical and electrical distances between adjacent electronic elements which process electrical signals having very fast transition times, including sub-nanosecond transition times.

In particular, when a multiplicity of signal lines having similar characteristic impedances are connected at a common point and a signal having said fast transition times is introduced on one of said lines, the structure of the pre- 'sent invention significantly reduces unwanted reflections of said signal on the balance of said lines at said common point. Also included in the present invention is a connector structure, and a novel arrangement of a multiplicity of said i connector structures, for shortening the physical and electri- S cal distances between adjacent printed circuit (hereinafter boards mounting integrated circuit (hereinafter "IC") chips. Further, it includes a connector for connecting flex- A ible. ribbon connector cables between such boards, and for a S' novl- arrangement of a multiplicity of connectors to increase processing rates for said sub-nanosecond electrical signals.

BACKGROUND OF THEPRESENT INVENTION In modern electronic systems such as computers and other data handling devices, processing rate (the inverse of time to add, subtract, multiply, divide, etc., two numbers) is -1of great importance. Processing rate is inversely proportional to transition time, the time it takes an electronic element to switch between "ON" and "OFF". Even though transition times have decreased to sub-nanosecond figures, with a resultant potential increase in processing rates, the speed with which electronic signals propagate along conductors is fixed by the velocity of light. Thus, physical distances separating circuit elements become increasingly significant, with respect to time, for a signal to go from one'point to another in a circuit. Reducing this distance by one-half can, in certain circumstances, actually have the effect of nearly doubling system processing rate.

Thus, processing rates of advanced electronic systems can be limited by sheer physical separation, such as the 15 distances between: 1. distinct passive and active circuit elements, e.g.

Scapacitors, inductors, resistors, semiconductors, etc.; 2. separated functional groups of circuit elements on PC boards; and 3. separated distinct PC boards.

The first of these distances has been reduced by reducing the physical sizes and power requirements of individual S circuit elements, and by crowding thousands of such-elements of microscopic dimensions on a single IC chip. This solution has become so well known in the art that examples need pot be provided.

The second of these distances has been reduced by Smounting many IC chips on a single PC board, so arranged that Sthe physical separation between related chips is as small as 2 i i possible, thus achieving the maximum possible processing rate 7r minimum possible processing time for that association of chips. Again, most modern electronic equipment incorporates this structure, has become well-known in the art, and need not be illustrated here.

Reducing the third of these distances is contral to the novelty of the present invention.

Existing solutions to this third problem reduce processing time by packing separated PC boards as tightly togc.her as possible, and typically use sophisticated cooling arrangements to compensate for the heat-buildup caused by the closer physical relationships of the heat-generating elements themselves. Typical of these existing solutions are the fol- S lowing references, all of which are U.S. patents and all of 15 which fall under onr; or more of the following structures: 1. 'star' or 'asterisk' connection; 2. female connector structures; 3. interconnecting of flat cables; and 4. radial arrangement of PC boards.

1. REFERENCES TO 'ASTERISK' CONNECTION STRUCTURE: SCoe 4,679,872, FIGS. 2 and 10 discloses a 'star' or 'asterisk' connection which is superficially similar to that of the present invention. However, the leads in coe are selfsupporting, relatively nassive structures with necessarily la:-ge associated stray reactive values, causing unavoidable degradation of electrical signals sent along them, wher3as the present invention allows order-of-magnitude reductions of size and of associated reactive values, thus increasing the 3 R- ""lll ~Ld~a~IC~Cqa processing rate of the basic device. (Coe '872 also may be relevant to the radial arrangement of PC boards, below.) The four Takashina patents (5,060,111; 5,091,822; 5,210,060, and 5,301,089) all disclose a radial connection system which superfically resembles the soldered or welded connection configuration of the present invention. However, the present invention permits substantially an order of reduction in lead dimension over Takashima, allows access to the common bus in the middle of the structure, and permits a substantial reduction in complexity.

Takashima 5,301,089 discloses a radial connection system which is a PC configuration, incorporating a radial bus assembly containing a cross-bar switch for distributing signals to the various PC boards. The cross-bar switch of this S 15 reference cannot be considered to be analogous to the asterisk Sconnection of the present invention. (Takashima '089 may also j be relevant to the PC board arrangement, below.) iJ 2. REFERENCES TO FEMALE CONNECTORS:

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ii 20 Heuer 2,971,179 discloses a female connector for receiving PC boards or flexible flat cables. The structure of "the present invention is distinguishable.

Jerominek 3,737,833 discloses a female connector for use with flexible flat cables. The structure of the present invention is distinguishable.

Roberts et al 4,740,867 discloses a female connector for connecting a flexible flat ribbon cable to a PC board. The present invention is distinguishable.

Weidler 4,995,814 discloses a female interconnector for -4connecting two blade-shaped members such as PC boards, flat 4cables, or a combination thereof, to each other. The structure of the present invention is distinguishable. (Weidler '514 may also have relevance to interconnecting flat cables, below.) Dambach et al 5,194,010, FIG. 3, discloses a female connector for interconnecting flat cables, boards, etc. The structure of the present invention is distinguishable. (Dambach et al '010 may have relevance to interconnecting flat cables, below.) Fran]keny et al 5,205,740 discloses an interconnector for connecting flat ribbon cables together. It has nQ relevance to the present invention.

Matschke et al 5,276,817 discloses an interconnector for connecting PC boards and flat cables together. F'IG. 2 thereof is the only portion of this disclosure having even a j ~iisuperficial relevance to the present invention, and is EFEREVCES 1- INTERCONNZCTION OF ELAT Carter 3,660,728 discloses a conductor interconnection system for flat cables. It has only a superficial rele- *vance to the present invention and is distinguishable.

S Weidler 4,995',814 discloses an interconnector for 7 two blade-shaped circuit members such as boards, flat cables, or a comibination thereof, and is distinguishable from the prosent invention. (This may have relevance to female connectors, above.) DM2bach et al 5,194,010, FIG. 3, discloses a connector for interconnecting flat cables, boards, etc., together.

Dambaruh ot al -is distinguishable from. the present invention.

(This may also have relevance to female connectors, above.) Sobhanj 5,213,511 has only a superficial relevance to the present invention, and is distinguishable therefrom.

4. REFERENCES TO ARRANGEMENT OF: PC BOARDS;: Coe 4,679,872 discloses an arrangement of PC boards around a radial bus assembly. one of the specific purposes of Coa is to reduce the stray capacitances and inductances of high speed circuitry by reducing the length of interconnecting leads (Col. 1, ins 41-58; col. 7, ins. 6-15). However, the present invention is distinguishable.

Takashina 5,301,089 discloses an arrangement of PC boards around a radial bus assembly which contains a cross-bar 15 switch distributing signals to the various PC boards. A crossbar switch is not an equivalent of the structure of the presr;.t invention.

BRIEF DErSCEIPTION OF THE PBESENT INVENTION: 20 The present invention includes a structure for obtaining reduced reflections at a common point from any of a *multiplicity of signal lines having similar characteristic impedances connected to the common point. When electrical sigflals,. including signals-having tr"ansition times of substantially less than one nanosecond, are introduced fromn One of the signal lines into the balance of the lines, reflections at the commuon point from discontinuities of any kind in any of the lines are greatly reduced, and do not significantly affect the original aignal. For example, when a multiplicity N of -6signal lines are connected at a common point and radiate symmetrically from it, and one of the lines is connected to a source of electrical signals of magnitude A amperes feeding N-i of the lines, reflections at the common point froin any of the N-lnewilhv a magnitude not exceeding J N-1 Preferably, the multiplicity of lines radiates symnictrically from the common point in a planar, or asterisk, fashion, although they could also radiate in a dandelion fashion.

When the asterisk arrangement is used, it is possible to connect the line from the signal source to the commion point orthogonally to the plane, which Insures that the stray I *.:.reactances from the balance of the lines are cq-ually .1:15 distribufted.

This feature alone of the present invention makes possible a performance improvement of up to twenty-fold in processing rates, by reducing the signal path length from PC board to PC board, by equalizing the path lengths, by allowing zu access to the common bus at other points of a PC board than the input, by minimizing the loading effects of intervening circuitry connected to the signal paths, and by substantially reducing structural complexity.

Another feature of the present invention is a female electrical connector for receiving a thin flat connector such as the edge of a PC board or the end of a flat flexible ribbon ctfible. The female connector is comprised of two halves which are mirror image& of each other. Each half includes a body of two parallel longitudinal members each having a foot and and -7a head end. Each foot end has a toe portion which extends outwardly from the longitudinal body, and the toe portions of the two halves are abutted to one another to form the connector.

The head ends are fabricated into a head member which extends transversely to the head ends of the longitudinal members and to the toe, and the foot ends are fabricated into a foot member which also extends transversely thereto and to the toe, and parallel to the head member. The head member has cantilevered therefrom a resilient arced member which extends toward the foot member substantially parallel to the longitudinal body, with the arced member having a convex surface and a concave surface, and an electrical conductor connected to the convex surface as hereinafter described. With the toe portions of the two halves abutted to one another, the convex surfaces 15 of the arced members face and curve toward one another so that a PC board or a flat flexible ribbon cable end inserted therebetween will force the cantilevered members apart, stressing them and thereby gripping the flat connector between them. The facing surfaces of the resilient arced members may have bonded 20 thereto metallic facings which form the electrical terminals which conductively mate with electrical surfaces on the PC boards and the like. The toe portions act as a stop member to the inserted PC board.

A multi-conductor connector, which will receive a PC board or a multi-conductor flat flexible cable or the like, is formed when the head and foot members are extended transversely with a multiplicity of longitudinal members fabricated therebetween, and cantilevered members extending between each pair of longitudinal members.

a A third feature of the present invention is a structure for distributing short rise-time electrical signals, including those having transition times of substantially less than one nanoscond. The structure includes a multiplicity of flat flexible circuit cables having a multiplicity of extended metallic conductors on at least two surfaces. The surfaces are separated from one another by insulation. Each of the cables has thereon a multiplicity of electrically conducting extended conductors or traces, one or more of which end in electrical connectors, which serve to connect the traces to sources of electrical energy, to other electrical elements, as well as to sources of electrical signals having rapid transition times, including sub-nanosecond transition times. Each of the extended traces includes one or more connection points internediate to the ends thereof, one or more of which have apertures extending between said surfaces of the cables. At least one of .the apertures has electrical conductors extending through the cable and conductively connecting to one or more connection points on the other surface of the cable, or to adjacent cables. The multiplicity of cables are held fixed in relationship to each other by clamp blocks, which have affixed thereto one or more connecting electrodes which extend through the apertures, and which provide electrical connection between two or more of the connection-points on two or more of the cables.

Yet another feature of the present invention is a novel way of arranging PC boards so as to obtain minimum separation maximum packing and more efficient cooling, and also a novel way of connecting them together so as to obtain maximum processing rates of overall operation. It -9- 10 accomplishes this with minimum deterioration, including 'stretching', of the electrical signals, caused by the loading effects of attaching additional circuits to the signal lines between them.

BRIEF DESCRIPTION OF THE DRAWINGS: s Fig. 1 discloses a typical existing method of the prior art for arranging a multiplicity of PC boards; Fig. 2A discloses a 'star' or 'asterisk' structure, the primary structure of an embodiment of the present invention; Fig. 2B discloses an alternate, 'dandelion', structure of an embodiment of the present invention; Figs. 3A-C disclose the structure of the female connector feature of an embodiment of the present invention: Fig. 3A discloses the structure of one-half of the female connector, the other half being a mirror image thereof; 1s -Figs. 3BI-3BIII disclose the structure and operation of the female connector: Fig. 3BI discloses one half of the female connector; SFig 3BII discloses the mirror image of 3BI: Fig. 3BIII discloses both halves of the female connector assembled, with a flat connector inserted therein; and 20 Fig. 3C discloses the structure of the female connector when attaching a finger of a flat flexible ribbon cable thereto.

Figs. 4A-D disclose the structure of a multiplicity 4 (FIGS. 4A-D descriptions, continued)z Ji 0 it

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I: of multiple female connectors for receiving a multiplicity of PC boards, connected according to the teachings of the p :eserit -FIG. 4A discloses an exploded view of the structure when attaching a multiplicity of fingers of a flat flexible ribbon cable to a multi-conductor female connector; -FIG. 4B discloses an exploded view of a pair of connector block~s for clamping together a multiplicity of ribbon cables, each connecting a pair of multi-conductor female connectors according to FIG. 4A; FIG. 4C discloses how a multiplicity of multi-conductor female connectors, as disclosed in FIG. 4A, are clamped together as disclosed in FIG. 4B; FIG. 4D discloses hiow edge-terminaled PC boards are- 15 inserted in the assembly of FIG. 4C.

FIGS. 5A and 5B disclose the structure of a multiplicity of multi-conductor female connectors which are arranged in a circular or cylindrical arrangement with INPUT/ OUTPUT connectors connected thereto: 20 FIG. 5A discloses the structure of a multiplicity of flexible ribbon cables having multi-conductor female connectors on the ends thereof which are clamped together and interconne cted with a pair of INPUT/OUTPUT connectors; and -FIG. 5B discloses the structure of an assembled INPUT/ ouTPUT structure, including a multiplicity of multipleconductor female connectors, each having a PC board iii (FIG. 5B descriptiion, continued): inserted therein, and clamped together with a pair of INPUT/OUTPUT connectors.

FIG. 6 discloseg art assemblage of PC boards, inser- -led into an assembled INPUT/OUTPUT structure as disclosed in PIC. SB.

DMTALED EXPLANATION or THE PR SENT INVE~NTION., FIG. I is an illustration of a typical prior art structure for arranging and connecting a multiplicity of PC .10 boards. A master board, or 'motherboard', contains circuitry .~..which controls the interaction between, and operation of, the separate dependent boards, which are called 'daughterboards' (for obvious reasons). The daughterboards interface with the motherboard through two rows of multi-conductor sockets shown thereon, one row of which may be used for signal input, and the other of which may be used for signal output from the dagtrors The wiring interconnecting the various sockets -and the motherboard control circuitry will be printed on one or more surfaces (sometimes internal) of the motherboard.

*20 It can be seen from FIG. I that some signals may have to go from the output elements of the nearest daughterboard to the input elements of the farthest thereof. The physical separation of these elements on this structure can be nearly 8 ins. (20 cm), with perhaps another 0.6 ins. (1.5 cm) at each end of each signal line to connect through the connectors and onto the PC boards, giving a Worst-case signal path length of 9.0 ins. (23 cm)g. In a 'typical system, however, a -12signal must be sent, received and proczessed at a distant circuit, returned, reacquired and reprocessed at the originating end, so that the initiating circuit will 'k~now' if further processing of a signal in a particular operating mode is required, or whether it can go on to succeeding mod.Aa.

signals in existing electronic systems, with PC boards of glass-epoxy constructS-on having a dielectric constant of 5.0, travel at rates s:lightly less than half the zedof light about 5.3 ins. (13.5 cm) per LUne-billionth of ecEEond Eo:nnecon: nEi -Esi:th:U:Zui:7 rsul t ina this case, 12 of them) connected between the source and destination of the signal, burden or 'load' it, causing its transition times (risetixne and failtine) to 'stretch' This adds perhaps another 0.5 nsec delay at the end of the signal line each way, as the receiving circuitr-. aits for the signal to switch to the 'ON, state from the 'OF~F' state, or vice versa.

'Rise-time' and 'fall-time' are the times rerquired fra electrical signal to sw.itch between minimum and maximum voltage levels, and vice versa. Propagation delay timle each way thus becomes about 2.2.nsec, or 4.4 nsec overall, resultin a theoretical maximum processing rate of 227 mHZ (megahertz, or millions of-cycles per second), even with an inpossible allowance of zero tine for process-delay tim~es at the receiving ends of the signal path.

The distance between PC boards, 'then, is seen to impse evee sste prcesin-rata limitations, especially since existing, commercially available, semiconductor devices -13- -14are available which -operate at much greater processing rates than these.

The present invention makes possible a performance improvement of up to twenty-fold in processing rates, by reducing signal path lengths from PC board to PC board and by equalizing them, and by minimizing the loading effects of intervening circuitry connected to the signal paths, and by reducing structural complexity.

A novel method has been discovered for making electrical connections in high processing-rate electrical circuits. This is useful when it is required to connect a number of parallel lines having similar values of controlled impedance, so that any one of these lines may be used as the signal input the 'SEND' line feeding the remainder of the lines the 'RECEIVE' lines. This new method of connection gives little or no practical distortion of the electrical signal at the receiving end of the lines, and actually ogives better results as the number of receiving signal paths increases (which is the reverse effect of existing methods of connection of the motherboard/daughterboard t. arrangements illustrated in Fig. 1).

15 The basic invention is disclosed in Figs. 2A and 2B, and is a structural method of making electrical connections for use in electrical circuits, especially high-speed digital circuits for processing electrical signals having very short transition times, less than one nanosecond. The structure works with slower signals, but is especially effective with very high-speed signals.

20 It is well known among those skilled in the art that, as transition times decrease of signals processed by electronic circuits, distortion of those signals increases, from a variety of sources, impedance mismatches and improper terminations, etc. Present invention 10 alleviates that problem in certain situations.

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As disclosed in Fig. 2A, present invention 10 is a structure for connecting at a common point 12 a multiplicity N of signal lines 14a 14n, each having similar characteristic impedances. This structure will greatly reduce, at common point 12, reflections from terminating impedances 16a 16n at far ends 18a 18n of lines s 14a .14n, when a current signal of magnitude A having very short transition times is introduced from one of said lines 14a into the balance, 14b 14n, of said lines.

Because present invention 10 is comprised of a multiplicity N of lines 14a 14n having similar characteristic impedances, the signal current provided by any one of lines 14a 14n will divide equally among all lines. Any mismatch of 10 impedances which any one of the signals encounters as it propagates down the lines will cause a reflection to travel back to common point 12. However, because the signal causing the reflection is only 1/Nth as large as the initial signal, and because impedance-matching terminations are provided at the end of each line 14a 14n, the reflection which will be seen at common point 12 will be small and, in a digital circuit, S* is v 15 will not be sufficient to cause any significant distortion thereof.

The preferred structure of connection 10 is with lines 14a 14n arranged symmetrically in a nominally planar fashion about common point 12 in a 'star' or 'asterisk' pattern. One of the lines 14a can be used as input in that arrangement, or it S could enter axially at common point 12, orthogonally to the plane of lines 14b 14n, which would insure uniform stray capacitive ard inductive reactances for each of the Slines 14b 14n and, additionally, would be delayed only by half-network propagation delay-time.

-16- Constructed as disclosed in Fig. 2A and described herein, it has been found that feeding a fast transition electrical signal into a multiplicity N of controlled impedance lines 14b 14n connected in parallel at common point 12 and arranged symmetrically in planar fashion thereabout, from "SEND" line 14a of similar impedance, will yield relatively undistorted signals on each of said signal lines 14b 14n. Depending on the amount of reflected energy tolerable by SEND line 14a, this planar connection arrangement may work satisfactorily for as few as four lines. Improved performance, minimal energy reflected back to common point 12 and source line 14a, is gained as more parallel signal-receiving paths are added, limited only by the driving energy limits of source S, or by the space limitations required by the connection itself.

S: The structure can be obtained by any of several fabrication techniques. These can range from a simple soldered or welded connection of a multiplicity N of central coaxial conductors 20a 20n arranged symmetrically about common point 12, to a machined fixture with coaxial connectors incorporating the basic structure therein, and even including a star or asterisk structure fabricated by integrated circuit technology on an IC microchip. Upon reflection, it will be realized by those skilled in the art that signal lead-lengths can be obtained which are extremely short, and that processing rates can be achieved that are as great as twenty times those presently available.

20 In an alternate three dimensional form 22, as disclosed symbolically in Fig. 2B, such an arrangement bf a multiplicity of signal lines could accommodate as many conductors as can physically be connected at one point 12, and might be called a 'dandelion' structure because of the internal structure. Sockets 24a, 24b, 24c 24n, represent points for a multiplicity of signal lines, or conductors 20a 20n. Said connection points are electrically connected at common point 12, by symbolic electrical member 26x to be inserted into cavity 28.

17- With appropriate changes in fabrication techniques, the structure would be adaptable to fiber optic technology.

Figs. 3A-C disclose another feature of the present invention, female electrical connector 30, for receiving thin flat connector 32, which can be the edge of a PC board or the end of a flat flexible ribbon cable. Female connector 30 is comprised of two halves 34a and 34b, which are mirror images of each other. Each half includes a body of two parallel longitudinal members 36a and 36b, each having head end 38a and foot end 38b. Longitudinal members 36a and 36b have thereon toe portions 40a and respectively, extending outwardly from foot end 38b. Toe portions 40a and 40b are o fixedly abutted to one another to form the complete connector, as disclosed in Fig.

3BIII. Longitudinal members 36a and 36b have fabricated to head ends 38a, head member 42 which extends transversely thereto, and foot ends 38b of members 36a and 36b have fabricated thereto, foot member 44 which also extends transversely to members 36a and 36b and to toes 40a and 40b, both respectively. Head member 42 and foot member 44 are substantially parallel.

Head member 42 has cantilevered therefrom resilient arced members 46a, 46b and 46c which extends toward foot member 44 substantially parallel to longitudinal members 36a and 36b. Arced members 46a, 46b and 46c (both not shown) have thereon convex surfaces 48a, 48b and 48c and concave surfaces 50a, 50b and 50c (both 20 not shown). Electrical conductors are affixed to convex surfaces 48a, 48b and 48c as hereinafter described..

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18- Female connector 30 is formed of longitudinal members 36a and 36b, head member 42 and foot member 44, and arced member 46a cantilevered from head member 42, and a mirror image thereof, as disclosed in Fig. 3BIII. Preferably, each half could be fabricated as a unitary body of a tough resilient plastic material such as s RYTON or XYDAR plastics. When toe portions 40a and 40b are fixedly abutted to each other, convex surfaces 48a and 48b of the arced members face and extend toward one another, as disclosed in Fig. 3BIII, so that a thin connector 32, such as a PC board or a flat flexible ribbon cable and, inserted between them, will force cantilevered members 46a and 46b ap: -t tressing them so that they fixedly grip flat connector 32 to therebetween.

Facing surfacp, 48a and 48b of resilient arced members 46a and 46b, respectively, wili have bonded or otherwise affixed thereto metallic facings which form the electrical terminals which conductively mate with electrical surfaces on thin flat connector 32 and the like. Toe portions 40a and 40b act as a stop member to inserted 15 connector 32.

S: A multi-conductor connector, which will receive a PC board or a multi-conductor flat flexible cable or the like, is formed when head member 42 and foot member 44 are extended

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transversely with i.L multiplicity of longitudinal members 36a and 36b fabricated therebetween. Canitilevered members 46a and 46b will be located between each pair of longitudinal members 36a and 36b.

I, 5 FIGS. 3B1, 3BII, 3B111, and 3C disclose how ribbon cable 'fingers' 52a and 52b are bonded to convex surfaces 4a and 48b Of' cantilever members 46a and 46b, all respectively.

Bonding can be done by any method well-known in the art, such as with an epoxy cement, which will give a permanent bond which will withstand repeated insertions and withdrawals.

I. cantilevered members 46a and 46b, with ribbon cable fingers 52a and 52b bonded on convex surface 48a and 48b, respectively, form an electrical contact between ribbon cable 54 at terminal 52a and thin member 32. Contact with electrical conductors on other ribbon cables or PC boards is made through connector 56, by means to be described in connection with FIGS. 4A-D, hereinafter.

it will -be seen from FIG. that active conductor 58 is connected to terminal 5za by jumper 60, which may con- 20 tain signal processing electronics. conductor 58 is balanced on the opposite surface of cable 54 by ground plane conductors T 60a and 60b, in accordance with the teaching of of U.S. Patent 4,B80,557, issued July 24, 1987 to the applicant herein.

FIGS. 4A-4D disclose a structure made possible by the multi-conductor female connector described hereinbefore in connection with FIGS. 3A-3C.

FIG. 4A discloses multi-conductor connector 56, attached to prior-art microstrip cable 62, with signal conductors 5Ba 58f balanced by active power and/or ground -19conductors 60a Fig. 4B discloses an exploded view of a multiplicity of multi-conductor connectors 56a 56n, disclosing the structure of a multi-connector terminal for interconnecting a multiplicity of PC boards. Each multi-conductor connector 56a 56n is connected to another of said connectors by flat flexible ribbon cables 64a 64n, which can be cable 54 of Fig. 3C, or any other existing cable, e.g., prior-art micro-strip cable 62 of Fig. 4A, other flat flexible ribbon cable presently known in the art or which may be developed in the future, or any combination thereof.

Insulating separators 74a 74n provide electrical separation between cables 64a 64n, which are pressed together by pressure-blocks 68 and 70, and clamped together by appropriate means. Each of said cables 64a 64n, said insulating separators 74a 74n, and pressure block 70 are perforated by a multiplicity of holes 66a 66n, which are penetrated by a multiplicity of electrically conducting pins 76a 76n, mounted on connector block 72. Pins 76a 76n electrically 15 interconnect with conductors on the opposite faces of said cables 64a 64n, and with selected conductors on other cables, according to the vo'tage and electrical signal requirements of a particular system. Connector-block 72 may be made interchangeable.

14AD -21- Fig. 4C discloses the assembled structure shown in exploded form in Fig. 4B.

Pressure blocks 68 and 70 press cables 64a .64n tightly together, and multiconductor female connectors 56a 56n fan out radially into a cylindrical form, as shown, ready to receive PC boards.

Fig. 4D discloses PC boards 32a .32n, inserted into connectors 56a 56n, with PC board 32n+ 1 ready to be inserted into connector 56n+ Fig. 5A discloses, in exploded view, another embodiment of Fig. 4D, wherein pressure-blocks 68 and 70, and connector block 72 therein, are replaced by INPUT/OUTPUT connector 78 and POWER connector 80. Conductive pins 82a 82n of I/O connector 78, and pins 84a 84n, of POWER connector perform the same functions as electrically conducting pins 76a 76n of connector :block 72.

Fig. 5B discloses the assembled structure of Fig. 5A, with terminal edg"s of PC ******boards 32a 32n inserted into multi-conductor female connectors 56a 56n.

boards 32a 32n inserted into multi-conductor female connectors 56a 56n.

e e e 22- Fig. 6 discloses an assembled multi-board system constructed according to the teachings of the present invention. POWER connector 80 is located at the base, and 1/O connector 78 is located at the upper end. PC boards 32a 32n are inserted into multi-conductor female connectors 56a 56n. Multiple star or asterisk connectors S 10 are connected at many points internally from the top to the bottom of the structure.

Appropriate cooling functions are located in the top 82, and shaped shields direct the flow of air around the temperature-sensitive components on PC oards 32a 32n, to keep the internal temperature within safe, proper operating limits. External shields 86, which can be transparent or opaque, protect the internal components.

to The terms and expressions which have been employed in the foregoing specification are used therein as terms of description and not of limitation, and there is no intention, in the use of such terms and expressions, of excluding equivalents of the features shown and described, or portions thereof, it being recognized that the scope of "the invention is defined and limited only by the claims which follow: ,9

Claims (1)

1. 23- The claims defining the invention are as follows: 1. A structure for obtaining reduced reflections at a common point from any of a multiplicity of signal lines having similar characteristic impedances connected to said common point, when an electrical signal, including a signal having transition times of substantially less than one nanosecond, is introduced from one of said lines into the balance of said lines, said structure comprising: a. a multiplicity N of signal lines connected at a common point and radiating therefrom: b. one of said lines: 10 1. bein connected to a source of electrical signals having a magnitude of A amperes: 2. feeding N-l of said lines. 2. A structure for connecting together at a common point a multiplicity of signal 15 lines of similar characteristic impedance, for reducing reflections at said common point from any of said signal lines when an electrical signal from one of said lines is introduced into the balance of said lines, said structure comprising: a. a multiplicity N of signal lines connected at a common point and radiating S: "therefrom: 20 b. one of said lines: 1. being connected to a source of electrical signals of magnitude A amperes; 2. feeding N-I of said lines; and c. reflections at said common point from any of said N-I line having a A magnitude not exceeding N-1 3. The structure of claim I or 2, wherein said multiplicity of said lines radiates symmetrically from said common point. L ~PUI~-~aurm~r~ 4. The structure of claim 1 or 2, wherein said multiplicity of said lines radiates symmetrically in a plane from said common point. 5. The structure of claim 4, wherein a line having similar characteristic impedance to each of said multiplicity of said lines, extends orthogonally from said common point in said plane. 6. The structure of claim 1 or 2, wherein said one of said lines is connected into a o first electrical connector for receiving therein a mating second electrical connector, said first electrical connector comprising: i. two halves being mirror images of each other, with each including: a. a longitudinal body having: i. a foot end having a toe portion thereon extending outwardly is from said longitudinal body; and ii. a head end including a head member extending transversely to said head end and said toe: A. said head member having thereon a resi!ient arced member cantilevered therefrom; said arced member having: a convex surface and a concave surface; connected thereto an electrical conductor; iii. a foot member extending transversely to both said longitudinal body and said toe; and 2. said toe portions of said two halves being abutted together to form said connector, with said arced members extending toward each other to grippingly receive said mating electrical connector. 7. The structure in claim 1 or 2, wherein said one of said lines is connected into: a. a multiplicity of flat flexible circuit cables: 1. having thereon two surfaces; and 2. being placed adjacent to one another: b. the surfaces of said cables being separated from one another by insulating members; 1. each of said cables having thereon a multiplicity of electrically conducting extended traces: A. one or more of said traces ending in electrical connectors; i. said electrical connectors for connecting said traces to: sources of electrical energy; sources of said digital current signals; and other electrical elements; B. each of said extended traces including one or more connection I points thereon, one or more of which have: apertures extending between said surfaces of said cables: i. said apertures having extending therethrough connecting .j 6. electrodes connecting with one or more connection points on ,j adjacent cables; c. said multiplicity of cables being held fixed in relationship to each other by 20 clamp blocks: 1. having affixed thereto one or more of said connccting electrodes: A. extending through said apertures, and B. providing electrical connections between two or more of said connection points on two or more of said cables. 8. The structure of claim 6, further comprising: a. a multiplicity of flat flexible circuit cables: 1. each having thereon two surfaces; and 2. being placed adjacent to one another: -26- b. the surfaces of said cables being separated from one another by insulating members: 1. each of said cables having thereon a multiplicity of electrically conducting extended conductors: SA. one or more of said conductors ending in electrical connectors; i. said electrical connectors for connecting said conductors to: sources of electrical energy; sources of said digital current signals; and other electrical elements; i each of said extended conductors including one or more connection points thereon, one or more of which have apertures extending between said surfaces of said cables: i. said apertures having extending therethrough connecting electrodes connecting with one or more connection points on adjacent cables; c. said multiplicity of cables being held fixed in relationship to each other by pressure blocks: 1. having affixed thereto one or more of said connecting electrodes: S 20 A. extending through said apertures, and B. providing electrical connections between two or more of said connection points on two or more of said cables. 9. A structure, substantially as described herein with reference to Fig. 2A or Fig. 2B. DATED this Eighth Day of February 1999 i Peter M. Compton i Patent Attorneys for the Applicant SPRUSON FERGUSON