WO1996002941A1 - Couvercle metallique pour boitier en ceramique et procede de fabrication correspondant - Google Patents

Couvercle metallique pour boitier en ceramique et procede de fabrication correspondant Download PDF

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Publication number
WO1996002941A1
WO1996002941A1 PCT/US1995/009124 US9509124W WO9602941A1 WO 1996002941 A1 WO1996002941 A1 WO 1996002941A1 US 9509124 W US9509124 W US 9509124W WO 9602941 A1 WO9602941 A1 WO 9602941A1
Authority
WO
WIPO (PCT)
Prior art keywords
layer
nickel
μin
palladium
cover
Prior art date
Application number
PCT/US1995/009124
Other languages
English (en)
Inventor
Jianxing Li
Original Assignee
Johnson Matthey Electronics, Inc.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Johnson Matthey Electronics, Inc. filed Critical Johnson Matthey Electronics, Inc.
Publication of WO1996002941A1 publication Critical patent/WO1996002941A1/fr

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/02—Containers; Seals
    • H01L23/10—Containers; Seals characterised by the material or arrangement of seals between parts, e.g. between cap and base of the container or between leads and walls of the container
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/02—Containers; Seals
    • H01L23/04—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]

Definitions

  • This invention relates to a sealing cover which is particularly suitable for sealing ceramic packages for semiconductor devices, and to a method of producing the same.
  • Ceramic packages for semiconductor devices is well-known.
  • a package typically includes a ceramic container to which the cover must be sealed.
  • Sealing covers also known as “lids,” of the type used in connection with containers for semiconductor devices are well known and typically include one or more layers of gold, often of substantial thickness, to aid in corrosion resistance as well as to provide for electrical connection of leads.
  • Such covers are not only expensive, but also introduce a possible health hazard since cyanide solutions are often used in gold plating.
  • the present invention is directed to a novel sealing cover, and to a method of making same, which avoids or at least substantially reduces the use of gold, thus lowering cost and reducing potential health hazards by eliminating or greatly minimizing gold plating.
  • a sealing cover is provided which is not only economical because it replaces gold with palladium, but is also of sufficiently high quality to pass standard tests for temperature cycling and thermal shock as well as resistance to corrosion in a salt atmosphere.
  • the present invention differs from the prior art, and in particular the disclosures in the Levine patents, in that the present invention involves a metallic cover, preferably with an iron-alloy core, and not a ceramic cover. Therefore, there is no need to coat the solder with palladium.
  • the new sealing cover employs separate distinct layers without alternating the layers according to the EMF value of the coatings and only a single palladium-containing layer is employed.
  • the relatively simple construction of the cover of the present invention still imparts sufficient corrosion resistance in salt atmospheres while retaining its solderability, but at a substantially reduced cost over the gold-containing sealing covers heretofore known.
  • a metallic cover for hermetically sealing a semiconductor device package by soldering which includes a substrate comprising a core of iron alloy, a first layer on the core which comprises nickel or nickel alloy, and a second layer on the first layer which comprises palladium or palladium alloy.
  • a coating of gold may be applied as an outer layer, but such a layer would be significantly thinner than that conventionally used. However, in many applications the layer of gold may be eliminated altogether without adversely affecting the desirable characteristics of the cover.
  • the sealing cover of the invention may be made by providing a core of an iron alloy, such as iron-nickel alloy, applying a first layer comprising a nickel or nickel alloy onto the core and then applying a second layer comprising palladium or palladium alloy onto the first layer.
  • a final thin coating of gold may be applied onto the second layer.
  • a semiconductor device package may be assembled using a cover as described by soldering it to a ceramic enclosure having a semiconductor device therein to hermetically seal the package, with a gold-free solder selected from the group consisting of solders containing at least one of lead, tin, silver, indium, bismuth, palladium, platinum and antimony, and which has a melting point in the range of from about 220°C to 300°C to avoid exposing the semiconductor device therein to elevated temperatures that might damage the device.
  • the solder may be incorporated as a solder preform of suitable configuration. In this manner, a soldered hermetically sealed semiconductor package may be assembled using the sealing cover and method previously described.
  • FIG. 1 is a schematic cross-sectional view of a sealing cover showing a metallic core over which is applied a nickel-containing coating and a final gold layer over the nickel-coated core;
  • FIG. 2 is a schematic representation of a sealing cover in accordance with the invention.
  • FIG. 3 is a schematic of a solder preform and cover assembly. Detailed Description of the Invention
  • the final layer consists of a substantially thick layer of gold. If it is possible to reduce the thickness of the gold coating or eliminate it altogether, while retaining the required characteristics of corrosionresistance, etc. a significant reduction in manufacturing costs would occur.
  • FIG. 2 which is an example of the invention wherein a metallic core is coated with a nickel-containing material, but a palladium-containing layer is applied onto the nickel layer.
  • the use of palladium or a palladium alloy in this manner avoids the need for a thick outer layer of gold and, for many applications, allows the gold layer to be omitted altogether.
  • the term "palladium alloy” as used herein refers to an alloy in which palladium is a major constituent and present in an amount of at least about 30 wt. %.
  • a suitable metallic core such as one made of iron-nickel alloy, known as "Alloy 42,” “Alloy 45” or “Alloy 46” or the alloy known 88 “Kovar,” may be provided. Alloys 42, 45 and 46 refer to compositions containing 42, 45 and 46 wt. % nickel, respectively.
  • the particular composition of the core is not critical to the success of the cover of the invention and any iron-based alloy may be used for this purpose provided similar thermal expansion characteristics to ceramic is maintained.
  • a first layer of nickel or nickel alloy is applied to the core.
  • the nickel-containing material may be applied as an electrolytic or "electroless" coating.
  • an electrolytic nickel-containing coating is preferred, because it appears to provide good corrosion resistance and economical and repeatable manufacture process.
  • a first layer of tin, silver, cadmium, indium, lead, copper, cobalt, ruthenium, iridium, zinc, or their alloys may be employed.
  • nickel and nickel alloys are preferred for their combination of cost, relative ease of application and resistance to corrosion.
  • the thickness of the first layer is very important in producing a sealing cover with desirable properties. It has been determined that the thickness of the nickel/nickel-alloy layer should be in the range of 100 to 800 ⁇ in. Although performance characteristics equal to that obtained with present technology can be achieved with as little as 100 ⁇ in, a cover with superior properties is not achieved until the minimum thickness of the nickel/nickel-alloy layer is in the range of 400 to 600 ⁇ in. The nominal thickness of this layer is advantageously about 500 ⁇ in.
  • a layer of palladium or palladium alloy (as defined previously), and in particular, a palladium-nickel alloy.
  • the most preferred composition presently is an alloy of about 80% palladium and about 20% nickel; however, alloys of at least about 30 wt. % palladium, balance nickel, silver or tin, are also particularly advantageous.
  • palladium and palladium alloys as aforesaid, however, it may be possible to use tin, platinum, silver, cadmium, indium, cobalt, lead, rhodium, ruthenium, iridium, or their alloys, and alloys of palladium with the foregoing.
  • the thickness of the palladium-containing layer is not as critical as the thickness of the first layer to achieving desirable properties in the sealing cover. However, it has been determined that the palladium-containing layer should be present in a range of from 10 ⁇ in to 100 ⁇ in for maximum performance. Although performance characteristics equal to covers made with present technology could be achieved with as little as 10 ⁇ in, if the first layer is sufficiently thick, i.e., at least 400 to 600 ⁇ in of electrolytic nickel, superior performance may be achieved with a palladium-containing layer in the range of 20 to 60 ⁇ in.
  • the improvement in performance of a cover employing a second layer of palladium-containing alloy is believed to be related to the statistical probability that each successive layer of plating will cover over porosity defects in the lower layer.
  • each such successive layer may have its own channel sites, the probability that defect sites will coincide with defects in other layers is very small.
  • Palladium and palladium- containing alloys are preferred because of their excellent solderability characteristics and the ability of such materials to supplement the ability of the first layer to minimize pinhole pores which create paths between the iron-containing core and the surrounding, possibly corrosive, atmosphere.
  • a coating of gold may be applied to the palladium-containing layer to provide an outer-surface appearance resembling sealing covers currently in use, which would improve the acceptability of the sealing cover in the marketplace.
  • Some additional advantage may result from the application of the thin layer of gold by assisting tack welding of a preform to the lid.
  • Substitutes for gold in this application may include tin, palladium, platinum, silver, cadmium, indium, cobalt, lead, rhodium, ruthenium, indium, and their alloys.
  • the gold layer is present in the range of from 0 to less than 50 ⁇ in.
  • Performance characteristics equal to covers made with present technology can be achieved without the gold layer if the second layer is a palladium-containing material of sufficient thickness, e.g., at least 50 ⁇ in, and the first layer is a nickel containing layer also of sufficient thickness, e.g., at least 500 ⁇ in.
  • superior performance may be achieved with a nominal gold thickness of 10 ⁇ in, which is believed sufficient to enhance solderability and cover pinhole pores which may be present in the first and/or second layers.
  • the preferred material for the core of the cover is an iron-nickel alloy, such as Alloy 42, Alloy 45, Alloy 46 or Kovar.
  • the preferred composition of the first layer is electrolytic or electroless nickel and/or nickel alloy, with electrolytic nickel and/or nickel alloy considered most advantageous.
  • the palladium-containing layer is formed of a palladium-nickel alloy, optimally 80% palladium and 20% nickel, or 30 to 100% palladium with silver or tin.
  • the sealing cover is hermetically sealed to the ceramic package by soldering.
  • soldering it is desirable to employ a gold-free or substantially gold-free solder for this purpose, but a gold-containing solder may also be used.
  • the solder should be one selected from the group consisting of solders containing at least one of lead, tin, silver, palladium platinum, indium, bismuth, antimony and gold, but which have a melting point in the range of about 220 °C to 310°C. These relatively low melting-point solders are additionally preferred so as to avoid the necessity of exposing the semiconductor device within the package to elevated temperatures, such as might possibly injure the semiconductor.
  • Solder compositions include solders containing in wt.
  • Other useful solders include 95% Pb-5% Pt.
  • solders useful in accordance with the present invention 12 solder compositions shown in the following table have been prepared:
  • Ceramic packages with sealing covers as described herein have been found to be capable of passing Mil. Std. 883C, Method 1010 for Test Condition C, 1,000 x temperature cycles and thermal shock testing.
  • the essentially three-layer cover described herein is also able to pass salt-atmosphere testing, is very solderable and cosmetically identical to the lid described in Mil-M-38510G (50 to 350 ⁇ in nickel under 50 to 225 ⁇ in gold), with all the same physical properties, but at a much reduced cost.
  • Resistance to corrosion in a salt atmosphere is generally measured as a percentage of surface area which is corroded.
  • Sealing covers of the present invention have less than 1 % corrosion and preferably, less than 1/2% corrosion, in terms of surface area, as determined according to Mil-Std-883, Method 1009.9, Condition A.
  • Preheat 350-450F for 30 minutes, rough roll at 350-450F with reduction of over 0.020" to thickness of 0.010" , finish roll at 200-300F with reduction of 0.001-0.004" to thickness of 0.002-0.005", rolling lubricant 4-B oil or Hexane.
  • Preform tack weld to cover Tack weld the preform to the cover (made from a conductive substrate and plated with a solderable surface layer) to form a preform/cover assembly.
  • Package cover/preform assembly Put the preform/cover assemblies into appropriate plastic packages and fill the package with an inert gas to prevent Pb solder oxidation during shipping and storage.
  • the first layer is nominally 250 ⁇ in and the gold layer is 50 ⁇ in.
  • the usual test to measure salt atmosphere corrosion resistance involves exposing 25 test pieces at a time. Corrosion resistance of conventional covers exhibit test results showing ⁇ 1 % surface area corrosion, with an average of about 0.25% surface area corrosion. In contrast, comparable tests of 25 pieces of 500 ⁇ in Ni on an iron-nickel alloy core with 40 ⁇ in Pd-Ni alloy and 5 ⁇ in Au results in ⁇ 0.5 % surface area corrosion and an average of about 0.1 %.
  • a core of "Alloy 42" is spot welded to a solder ring, i,e., preform. Three steps are used to fabricate a complete lid. A. Plated lid production.
  • Plated Lid Production Alloy 42 (Fe 58%, Ni 42%) is rolled into sheets 0.010" to 0.015" thick, and annealed into a state making it suitable for punching (typically 95,000 psi tensile strength). The sheet is slit into coils wide enough to make them easily punched through a progressive die set.
  • Typical sizes include:
  • the punched squares may then be deburred chemically or mechanically to clean up any rough edges that may result from metal shearing.
  • the cleaned and deburred lids may than be loaded into a plating barrel for degreasing, oxide removal, and electroplating of all desired layers.
  • One barrel of low cost lids were plated using the following sequence:
  • a Sterling System 6" x 12" plating barrel was loaded about 30% full with .605" x .605" x 0.010" alloy 42 squares which had been previously punched and deburred in the manner described above.
  • This barrel was plated with nickel, palladiumnickel and gold using the following sequence: a. Electroclean at 5 volts anodic for 5 minutes; b. Rinse for at least 5 minutes; c. Descale in acid blend for 5 minutes; d. Rinse for 2 minutes; e. Plate in Sulfamate Nickel for ample time to deposit 500 ⁇ in; f. Rinse for 5 minutes; g. Acid activate in 5% HC1 (optional); h. Plate in Pd-Ni for ample time to deposit 40 ⁇ in; i. Rinse for 5 minutes; j. Plate in a high adhesion pure gold bath for ample time to deposit 5 ⁇ in 99.9% pure gold; k. Rinse for 10 minutes in warm cascading deionized water; and 1. Dry in TDFC Freon dryer or suitable substitute. 3. Lids electroplated in the manner described will routinely pass the following tests:
  • a predetermined quantity 99.99% pure lead is brought to its melting point in a bottom draw continuous caster.
  • To the molten lead is added 5.0 wt. % 99.99% pure palladium in powder form.
  • the metal is cast continuous style through a 0.200" x 2.000" die. (Other size die are also suitable.)
  • the resulting 0.200"x 2.000" piece is rolled down to a thickness of 0.0021" +/-
  • the clean strip is punched into "window frame” shapes 0.0021" thick x 0.605" OD x 0.505" ID.
  • a compound punching die set is used, and although the material deforms easily, several thousand pieces are made in this manner.
  • Appropriate tooling for fastening the solder window frames of step B to the plated alloy 42 lids of step A is performed by methods known to the trade and typically produced by specialty manufacturers, usually by resistance welding.
  • the tooling used for this work is generally insulating platform with 8 pins arranged to hold the lid and solder ring in alignment. Arranged 0.025" in from each corner in the block is an electrode extending 0.005" out of the block. By clamping the assembly in place from above, it is possible to spot weld the lid to the solder by passing a high current through the electrodes.
  • This lid-solder combination is the finished product which may be used to hermetically seal a silicon die into a ceramic package.

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  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Other Surface Treatments For Metallic Materials (AREA)
  • Electroplating Methods And Accessories (AREA)

Abstract

Cette invention se rapporte à un couvercle métallique brasable servant à sceller hermétiquement un boîtier en céramique, ce couvercle contenant un noyau en fer ou en alliage de fer, ainsi qu'une couche de nickel ou d'alliage de nickel recouvrant le noyau et une couche de palladium ou d'alliage de palladium recouvrant ladite couche de nickel.
PCT/US1995/009124 1994-07-19 1995-07-19 Couvercle metallique pour boitier en ceramique et procede de fabrication correspondant WO1996002941A1 (fr)

Applications Claiming Priority (2)

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US27714594A 1994-07-19 1994-07-19
US08/277,145 1994-07-19

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Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2000007225A2 (fr) * 1998-07-29 2000-02-10 Silicon Light Machines Procede et appareil permettant de sceller un couvercle hermetique sur une puce de semi-conducteur
US6096576A (en) * 1997-09-02 2000-08-01 Silicon Light Machines Method of producing an electrical interface to an integrated circuit device having high density I/O count
US6785001B2 (en) 2001-08-21 2004-08-31 Silicon Light Machines, Inc. Method and apparatus for measuring wavelength jitter of light signal
US7046420B1 (en) 2003-02-28 2006-05-16 Silicon Light Machines Corporation MEM micro-structures and methods of making the same
US9364529B2 (en) 2007-04-29 2016-06-14 Beijing Wantai Biological Pharmacy Enterprise Co., Ltd. Truncated L1 protein of human papillomavirus type 18
US9698116B2 (en) 2014-10-31 2017-07-04 Nxp Usa, Inc. Thick-silver layer interface for a semiconductor die and corresponding thermal layer

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10468375B2 (en) * 2016-07-04 2019-11-05 Mitsubishi Electric Corporation Semiconductor device and method for manufacturing same

Citations (12)

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US4141029A (en) * 1977-12-30 1979-02-20 Texas Instruments Incorporated Integrated circuit device
US4331258A (en) * 1981-03-05 1982-05-25 Raychem Corporation Sealing cover for an hermetically sealed container
US4331253A (en) * 1980-02-19 1982-05-25 Consolidated Refining Co., Inc. Lid assembly for hermetic sealing of a semiconductor chip
US4601958A (en) * 1984-09-26 1986-07-22 Allied Corporation Plated parts and their production
US4640436A (en) * 1985-03-08 1987-02-03 Sumitomo Metal Mining Co., Ltd. Hermetic sealing cover and a method of producing the same
US4640438A (en) * 1986-03-17 1987-02-03 Comienco Limited Cover for semiconductor device packages
US4666796A (en) * 1984-09-26 1987-05-19 Allied Corporation Plated parts and their production
JPS635550A (ja) * 1986-06-25 1988-01-11 Mitsubishi Electric Corp 半導体装置
US4737418A (en) * 1986-12-22 1988-04-12 Advanced Materials Technology Corp. Nickel clad corrosion resistant lid for semiconductor package
US4835067A (en) * 1988-01-21 1989-05-30 Electro Alloys Corp. Corrosion resistant electroplating process, and plated article
US4842961A (en) * 1988-03-04 1989-06-27 Advanced Materials Technology Corp. Alternate electrolytic/electroless-layered lid for electronics package
US5045639A (en) * 1990-08-21 1991-09-03 Tong Hsing Electronic Industries Ltd. Pin grid array package

Patent Citations (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4141029A (en) * 1977-12-30 1979-02-20 Texas Instruments Incorporated Integrated circuit device
US4331253A (en) * 1980-02-19 1982-05-25 Consolidated Refining Co., Inc. Lid assembly for hermetic sealing of a semiconductor chip
US4331258A (en) * 1981-03-05 1982-05-25 Raychem Corporation Sealing cover for an hermetically sealed container
US4601958A (en) * 1984-09-26 1986-07-22 Allied Corporation Plated parts and their production
US4666796A (en) * 1984-09-26 1987-05-19 Allied Corporation Plated parts and their production
US4640436A (en) * 1985-03-08 1987-02-03 Sumitomo Metal Mining Co., Ltd. Hermetic sealing cover and a method of producing the same
US4640438A (en) * 1986-03-17 1987-02-03 Comienco Limited Cover for semiconductor device packages
JPS635550A (ja) * 1986-06-25 1988-01-11 Mitsubishi Electric Corp 半導体装置
US4737418A (en) * 1986-12-22 1988-04-12 Advanced Materials Technology Corp. Nickel clad corrosion resistant lid for semiconductor package
US4835067A (en) * 1988-01-21 1989-05-30 Electro Alloys Corp. Corrosion resistant electroplating process, and plated article
US4842961A (en) * 1988-03-04 1989-06-27 Advanced Materials Technology Corp. Alternate electrolytic/electroless-layered lid for electronics package
US5045639A (en) * 1990-08-21 1991-09-03 Tong Hsing Electronic Industries Ltd. Pin grid array package

Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6096576A (en) * 1997-09-02 2000-08-01 Silicon Light Machines Method of producing an electrical interface to an integrated circuit device having high density I/O count
WO2000007225A2 (fr) * 1998-07-29 2000-02-10 Silicon Light Machines Procede et appareil permettant de sceller un couvercle hermetique sur une puce de semi-conducteur
WO2000007225A3 (fr) * 1998-07-29 2000-04-27 Silicon Light Machines Inc Procede et appareil permettant de sceller un couvercle hermetique sur une puce de semi-conducteur
US6303986B1 (en) 1998-07-29 2001-10-16 Silicon Light Machines Method of and apparatus for sealing an hermetic lid to a semiconductor die
US6785001B2 (en) 2001-08-21 2004-08-31 Silicon Light Machines, Inc. Method and apparatus for measuring wavelength jitter of light signal
US7046420B1 (en) 2003-02-28 2006-05-16 Silicon Light Machines Corporation MEM micro-structures and methods of making the same
US9364529B2 (en) 2007-04-29 2016-06-14 Beijing Wantai Biological Pharmacy Enterprise Co., Ltd. Truncated L1 protein of human papillomavirus type 18
US9698116B2 (en) 2014-10-31 2017-07-04 Nxp Usa, Inc. Thick-silver layer interface for a semiconductor die and corresponding thermal layer

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