WO1995021459A1 - Halbleiter-speicherbauteil mit mehreren speicherchips in einer gemeinsamen umhüllung - Google Patents
Halbleiter-speicherbauteil mit mehreren speicherchips in einer gemeinsamen umhüllung Download PDFInfo
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- WO1995021459A1 WO1995021459A1 PCT/DE1995/000155 DE9500155W WO9521459A1 WO 1995021459 A1 WO1995021459 A1 WO 1995021459A1 DE 9500155 W DE9500155 W DE 9500155W WO 9521459 A1 WO9521459 A1 WO 9521459A1
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- carrier
- memory chips
- memory
- module board
- semiconductor memory
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 32
- 150000001875 compounds Chemical class 0.000 claims abstract 3
- 238000004519 manufacturing process Methods 0.000 claims description 29
- 239000000969 carrier Substances 0.000 claims description 19
- 238000000034 method Methods 0.000 claims description 14
- 238000001746 injection moulding Methods 0.000 claims description 2
- 101100400378 Mus musculus Marveld2 gene Proteins 0.000 claims 1
- 239000000758 substrate Substances 0.000 abstract 7
- 238000000465 moulding Methods 0.000 abstract 2
- 238000004382 potting Methods 0.000 abstract 2
- 239000011248 coating agent Substances 0.000 abstract 1
- 238000000576 coating method Methods 0.000 abstract 1
- 230000006870 function Effects 0.000 description 7
- 238000012360 testing method Methods 0.000 description 7
- 238000002347 injection Methods 0.000 description 5
- 239000007924 injection Substances 0.000 description 5
- 239000012050 conventional carrier Substances 0.000 description 3
- 238000011990 functional testing Methods 0.000 description 3
- 241000239290 Araneae Species 0.000 description 2
- 238000005538 encapsulation Methods 0.000 description 2
- 238000004026 adhesive bonding Methods 0.000 description 1
- 238000005275 alloying Methods 0.000 description 1
- 239000000919 ceramic Substances 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 230000002950 deficient Effects 0.000 description 1
- 239000011888 foil Substances 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 239000010931 gold Substances 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 238000004806 packaging method and process Methods 0.000 description 1
- 238000000926 separation method Methods 0.000 description 1
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- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
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- G11—INFORMATION STORAGE
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- G11C5/00—Details of stores covered by group G11C11/00
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- G11C5/025—Geometric lay-out considerations of storage- and peripheral-blocks in a semiconductor storage device
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- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
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Definitions
- the invention relates to semiconductor memory components according to the preambles of claims 1 and 2 and to methods for producing the semiconductor memory components according to the preambles of claims 14 and 15.
- SIMM Single in line memory module
- the memory module equipped with memory modules is installed as a whole in the computer (soldered or plugged in) and also, if necessary, replaced or supplemented as a whole.
- FIG. 1 shows a standard memory module (for example 4Mx9 DRAM) with the module board M, nine memory modules S (instead of DRAMS, SRAMs, E (E) PROM etc. would also be possible) and the module connections 1 to 30.
- the module connections 1 to 30 are connected via electrical lines (not shown) to contact points to which the external connection points A of the memory modules S are fastened with plug connections or surface contacts (for example soldered).
- the memory modules S are arranged here in two rows of four and five stones, but other configurations are also possible.
- Figure 2 shows a typical memory chip.
- the memory chip C is mounted on a carrier ⁇ (metal spider, foil etc.) by gluing, alloying etc. Between the contact points K of the memory chip C and the outer connection points A of
- Carrier T-j_ has electrical connections B (e.g. gold wires) attached.
- memory chip C and carrier T] _ are provided with a sheath U, which usually consists of plastic (alternatively, ceramic is used) and is either pre-molded or cast directly around carrier T] _ and chip C.
- Carrier T] _ and casing U together with electrical connections B represent the housing of the memory chip C.
- Figures 3a to 3c show a manufacturing step of the memory module shown in Figure 2, shown here in supervision.
- FIG. 3a shows the carrier T-j_, which is also referred to as a spider because of its shape.
- the memory chip C is fastened in the middle of the carrier T1. With A the outer connection points of the carrier T] _ are designated.
- the memory chip C is connected to the external contact points K by connections which are not shown.
- FIG. 3b shows the same structure that was provided with an envelope U (shown here only in outline).
- envelope U shown here only in outline.
- plastic covering is e.g. has been cast around the carrier T provided with the memory chip C, the outer connection points A of the carrier remaining free.
- FIG. 3c shows the module after the outer connection points A have been bent downward for fastening and contacting, for example on a module board.
- the memory modules produced in this way are also subjected to a functional test, automatic test machines being used today which can test several memory modules in parallel (for example T 5363 from ADVANTEST for 16 modules). The memory modules are then attached to the module board.
- WO-A-81/02367 shows a generic arrangement.
- a memory module is disclosed in which four identical memory chips are accommodated in a common housing, two being on the top and two on the bottom of a laminate carrier provided with lines. In order to keep the memory component compact, the four memory chips share a plurality of the outer connection points of the carrier, for example the address pins.
- such memory modules have not been able to establish themselves on the mass market since they do not meet the memory module standards and are too expensive to manufacture due to the complex assembly of the memory chips in the module on a laminate carrier. These modules do not represent any progress for use in memory modules.
- JP-A-60208851 discloses another semiconductor memory device.
- the memory chips are attached directly to a memory board, provided with electrical connections and covered with a common cap. This arrangement was also unable to establish itself due to the disadvantages of the production process. Due to the direct mounting of the memory chips on the memory board, special boards have to be used, the testing of the memory chips (which can only be carried out after the chips have been electrically connected to the board) is made more difficult because memory chips that are recognized as defective can be used (since they are on the board soldered) are difficult to replace with functional, and the electrical connections between chips and circuit board are complex and expensive.
- JP-OS 64-1270 also shows a generic semiconductor memory component.
- contact points of the individual memory chips which carry the same data signals or potentials during operation, are each connected to a single external connection point.
- this has the consequence that, viewed from a geometrical point of view, a special encapsulation is necessary which, with the number of connection points remaining approximately the same, is larger than the encapsulation used as standard for a single memory chip, so that the connection points have a geometrical arrangement and also the number (data input and / or data output signals for or from different memory chips cannot be assigned to one connection point at a time) does not correspond to the requirements which standardized boards for SIMM modules have, for example, with regard to the number and arrangement of the connection points.
- the aim of the present invention is to provide a memory component which can be handled as simply and inexpensively as possible when used together with module boards, and largely standardized components can be used in its manufacture.
- FIGS. 1 to 3 show a memory module and a memory module according to the prior art
- FIGS. 4 to 9 show a first embodiment of the
- FIGS. 10 to 14 show a second embodiment of the invention along with advantageous configurations.
- FIGS. 4a and 4b show a first advantageous embodiment of the invention.
- a semiconductor memory component F is shown, which has five memory chips C of the same memory type (DRAM, SRAM, E (E) PROM etc.), which are fastened on a common carrier T.
- memory chips C of the same type
- those of different types of memory eg DRAMs, SRAMs and / or EEPROMs, mixed
- the memory chips C (not shown in FIG. 4a, analogously to those from FIG. 2) have contact points K which are electrical Connections B are connected to the outer connection points A of the carrier T.
- the shape of the support T corresponds to five supports T] _ of the type shown in FIGS. 2 and 3a to 3c, which are connected to one another.
- the carrier T thus has five times as many external connection points A as a conventional carrier T-j_.
- the five memory chips C fastened to the middle parts of the conventional carrier structures and attached to the carrier T are connected in the manner shown in FIG. 2 to the external connection points A of the carrier T.
- Each contact point K of each memory chip C is thus assigned exactly one external connection point A of the carrier T, the sum of the number of contact points K of the memory chips C is equal to the number of external connection points A of the carrier T.
- FIG. 4b shows the carrier T with the (not more visible) memory chips * C and their common casing U, which leaves the outer connection points A of the carrier T.
- the invention can also be implemented in such a way that at least those contact points K of the memory chips C which carry data signals during operation (address signals, control signals, data input and output signals) are each assigned to one of the outer connection points A (wire connection, bonding), while the contact points K which conduct supply potentials during operation (typically VDD and VSS) are not necessarily connected to an external connection point A, but, separated according to the type of supply potential, have fewer external connection points A than correspond to a 1: 1 assignment would.
- the contact points K of a respective type of supply potential would have to be electrically connected to one another in another way (for example by means of bond wires inside the casing U or by means of short-circuit bridges outside the casing U).
- the memory component T according to the invention corresponds in structure and function to five of the memory modules shown in FIG. 2. However, it is less expensive to manufacture and use with module boards. The one used in the manufacture of conventional building blocks. The one used in the manufacture of conventional building blocks
- Carrier T ] _ is generally processed in the form of a band of several identical carrier structures T -] _ arranged in series and interconnected.
- the same band of carrier structures can be used for the production of the carrier T, the band being separated into individual carriers T] _ after the memory chips C and their electrical connections B have been applied, or there are five carrier structures in pieces.
- FIG. 5 shows a first advantageous application of the invention.
- two larger memory components V and F according to the invention are fastened on a module board M, one component V the function of four and the other F the function of five conventional ones Memory modules fulfilled.
- the number of outer connection points A of the components V and F and the distances between them correspond exactly to those of conventional individual components arranged in rows.
- a standard module board M such as that shown in FIG. 1, can therefore be used.
- the band of carrier structures used in the production of the memory components V and F must then have a distance between adjacent individual structures which corresponds to the gap between two individual components placed in series.
- FIG. 6 shows schematically the production of the common casing U for a component according to the invention, the outer connection points A of which, at a distance from one another, correspond to those of conventional memory modules when the modules are placed in series and at a distance from one another.
- the band of carrier structures TB provided with memory chips C is surrounded by an injection mold SF which has inlet openings E through which a plastic mass is introduced.
- a distance d is left between each of two conventional individual components corresponding to injection molds, which is the same as that between individual components attached to standard module boards M in the conventional manner. If a different wrapping material or a different manufacturing process is used (e.g. with pre-molded parts, pre-molded), the process step is adjusted accordingly.
- FIG. 7 shows a first variant of the first embodiment and its application.
- a module board M is equipped with two memory components V and F according to the invention, one component V performing the function of four and the other F the function of five conventional memory components.
- the distances of the outer connection points A Memory components V and F correspond to those of nine conventional memory modules which are set in two rows of four and five modules, respectively, without keeping a distance from one another.
- Such an arrangement of the outer connection points A of the memory components V and F according to the invention corresponds to the use of a band of carrier structures TB which has conventional individual module carriers T ] _ corresponding individual structures in direct contact one behind the other and without any spacing from one another.
- FIG. 8 the production of the common envelope U is carried out with an analog injection mold SF.
- An advantage of this variant is the possibility of reducing the dimensions of the module board M.
- Figure 9 shows a second variant of the first embodiment and its application. Analogous to FIGS. 5 and 7, a module board M is shown. A memory component N according to the invention, which fulfills the function of nine conventional memory modules, is fastened on this. The arrangement of the outer connection points A corresponds to that of nine conventional memory chips set in two rows.
- the component N has nine memory chips C, which are fastened to a common carrier T and are surrounded by a common casing U.
- the memory component N e.g. two carriers, which correspond to those used in components V and F from FIG. 7, are connected to one another to form a carrier T, which is then fitted with nine memory chips C and provided with a common casing U.
- the simple modular structure of the component means that the component can easily be separated into areas between individual chips.
- the module board M is then equipped with two or more components.
- Figure 10 shows a second advantageous embodiment of the invention.
- two supports TV and TF are attached, which correspond to the supports T used in the manufacture of components V and F from FIG.
- the brackets TV and TF consist of four or five brackets attached to one another, brackets T ] _ corresponding to individual components, and thus have four or five times as many external connection points A. like individual building blocks.
- a memory chip C is fastened and electrically connected in such a way that exactly one external connection point A of the carrier TV or TF is assigned to each contact point K of each memory chip.
- the carriers TV and TF with the memory chips C thereon thus correspond to the components V and F from FIG. 7 without their common casing U.
- the carriers TV and TF with the memory chips C thereon are both carriers TV and TF and also their outer ones
- connection points A Surrounding connection points A enveloping envelope U. Since the carriers TV and TF, in contrast to those of the components V and F in FIG. 7, are not provided with a sheath which leaves the outer connection points A and are mounted on a module board M, but, mounted on the module board M, with an outer connection points A envelope U are provided, the module board M is part of the envelope U.
- the common covering U could also consist of two parts, each covering one of the two carriers TV and TF fastened on the module board M together with its outer connection points A.
- FIGS. 11 to 14 show different variants of the second embodiment.
- a carrier T is shown with the memory chips C thereon, the electrical connections B and the outer connection points A, which is surrounded by a casing U common to the memory chips C and which includes the outer connection points A.
- two or more carriers could also be surrounded by an envelope U.
- FIGS. 11 to 14 show the component according to the invention in cross section to the longitudinal axis defined by the large extent of the carrier T.
- FIG. 11 shows an envelope U enveloping carrier T with memory chips C and external connection points A, which is composed of the part of the module board M located under the carrier T and a molded part F covering the side of the carrier T facing away from the module board M.
- the fitting F consists of, for example
- the component according to the invention differs significantly from the prior art disclosed in JP-A-60-20 88 51: Since the memory chips C are not fastened directly on a module board M, but on a carrier T, the Production of the component according to the invention does not have any of the disadvantages already mentioned with regard to JP-A-60-20 88 51.
- FIG. 12 shows an envelope U enveloping carrier T with memory chips C and external connection points A, which is composed of the part of the module board M located under the carrier T and a casing mass H enclosing the side of the carrier T facing away from the module board M.
- the envelope mass H consists e.g. made of plastic (post-molded).
- Injection molding analogous to that shown in Figures 6 and 8
- Injection molds SF are used, these having a correspondingly selected shape.
- the enveloping mass H could also extend to the rear of the module board M, as shown in FIG. This would e.g. a greater mechanical stability of the component according to the invention.
- FIG. 14 shows a module board M which is equipped with carriers T-j_ and T2 on both surfaces.
- the beams T] _ and T2 speak to the carriers T of the first embodiment of the component according to the invention and have a plurality of memory chips C] _ or C2 and their electrical connections B.
- the carriers T-j_ and T2 provided with the memory chips are surrounded together with a part of the module board and with their outer connection points A by an enveloping mass H, so that they are enveloped by a part of the module board M and the enveloping mass H as a covering.
- the component according to the invention represented by FIG. 14 has lower costs and simplified manufacture compared to conventional components, since
- Using a plurality of memory chips C common carriers T and a sheath common to all memory chips C together with carriers T reduces the number of process steps required to produce a module board M equipped with memory elements on both surfaces.
- the supports T used in the second embodiment of the invention are produced from standardized elements (strips of support structures) and, for connection and for attachment to the module board M, either plug-in connections or surface connections, i.a. soldered, can have.
- the number of memory chips C used in the semiconductor memory component according to the invention is preferably selected so that the number of n-4 or (n-4) + 1 results for the data input and data output connections of the semiconductor memory component, with n> 0 .
- the latter case allows the use of a so-called parity bit in the semiconductor memory device.
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Computer Hardware Design (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Semiconductor Memories (AREA)
- Dram (AREA)
Abstract
Description
Claims
Priority Applications (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1019960704286A KR970700940A (ko) | 1994-02-07 | 1995-02-06 | 공통 케이싱에서 다수의 메모리 칩을 가진 반도체 메모리 소자(semiconductor storage component with a plurality of storage chips in a shared casing) |
JP7520319A JPH09508496A (ja) | 1994-02-07 | 1995-02-06 | 共通のパッケージに複数個のメモリチップを備えた半導体メモリ素子 |
EP95908875A EP0744084A1 (de) | 1994-02-07 | 1995-02-06 | Halbleiter-speicherbauteil mit mehreren speicherchips in einer gemeinsamen umhüllung |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
DEP4403733.3 | 1994-02-07 | ||
DE4403733 | 1994-02-07 |
Publications (1)
Publication Number | Publication Date |
---|---|
WO1995021459A1 true WO1995021459A1 (de) | 1995-08-10 |
Family
ID=6509654
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
PCT/DE1995/000155 WO1995021459A1 (de) | 1994-02-07 | 1995-02-06 | Halbleiter-speicherbauteil mit mehreren speicherchips in einer gemeinsamen umhüllung |
Country Status (5)
Country | Link |
---|---|
EP (1) | EP0744084A1 (de) |
JP (1) | JPH09508496A (de) |
KR (1) | KR970700940A (de) |
TW (1) | TW354859B (de) |
WO (1) | WO1995021459A1 (de) |
Families Citing this family (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP3955712B2 (ja) * | 2000-03-03 | 2007-08-08 | 株式会社ルネサステクノロジ | 半導体装置 |
US20040178514A1 (en) * | 2003-03-12 | 2004-09-16 | Lee Sang-Hyeop | Method of encapsulating semiconductor devices on a printed circuit board, and a printed circuit board for use in the method |
Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US3341649A (en) * | 1964-01-17 | 1967-09-12 | Signetics Corp | Modular package for semiconductor devices |
GB2096394A (en) * | 1981-04-06 | 1982-10-13 | Int Rectifier Corp | Four-lead dual in-line package module for semiconductor devices |
JPH05243326A (ja) * | 1991-08-20 | 1993-09-21 | Hitachi Cable Ltd | 半導体装置 |
US5280193A (en) * | 1992-05-04 | 1994-01-18 | Lin Paul T | Repairable semiconductor multi-package module having individualized package bodies on a PC board substrate |
US5337216A (en) * | 1992-05-18 | 1994-08-09 | Square D Company | Multichip semiconductor small outline integrated circuit package structure |
-
1995
- 1995-01-26 TW TW084100691A patent/TW354859B/zh active
- 1995-02-06 KR KR1019960704286A patent/KR970700940A/ko not_active Application Discontinuation
- 1995-02-06 JP JP7520319A patent/JPH09508496A/ja active Pending
- 1995-02-06 WO PCT/DE1995/000155 patent/WO1995021459A1/de not_active Application Discontinuation
- 1995-02-06 EP EP95908875A patent/EP0744084A1/de not_active Ceased
Patent Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US3341649A (en) * | 1964-01-17 | 1967-09-12 | Signetics Corp | Modular package for semiconductor devices |
GB2096394A (en) * | 1981-04-06 | 1982-10-13 | Int Rectifier Corp | Four-lead dual in-line package module for semiconductor devices |
JPH05243326A (ja) * | 1991-08-20 | 1993-09-21 | Hitachi Cable Ltd | 半導体装置 |
US5280193A (en) * | 1992-05-04 | 1994-01-18 | Lin Paul T | Repairable semiconductor multi-package module having individualized package bodies on a PC board substrate |
US5337216A (en) * | 1992-05-18 | 1994-08-09 | Square D Company | Multichip semiconductor small outline integrated circuit package structure |
Non-Patent Citations (1)
Title |
---|
PATENT ABSTRACTS OF JAPAN vol. 017, no. 702 (E - 1482) 21 December 1993 (1993-12-21) * |
Also Published As
Publication number | Publication date |
---|---|
EP0744084A1 (de) | 1996-11-27 |
JPH09508496A (ja) | 1997-08-26 |
KR970700940A (ko) | 1997-02-12 |
TW354859B (en) | 1999-03-21 |
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