WO1995010803A1 - Prozessor für zeichenketten variabler länge - Google Patents
Prozessor für zeichenketten variabler länge Download PDFInfo
- Publication number
- WO1995010803A1 WO1995010803A1 PCT/EP1994/003045 EP9403045W WO9510803A1 WO 1995010803 A1 WO1995010803 A1 WO 1995010803A1 EP 9403045 W EP9403045 W EP 9403045W WO 9510803 A1 WO9510803 A1 WO 9510803A1
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- WIPO (PCT)
- Prior art keywords
- chain
- unit
- partial
- strings
- bytes
- Prior art date
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- 238000012545 processing Methods 0.000 claims description 22
- 238000011156 evaluation Methods 0.000 claims description 4
- 238000012546 transfer Methods 0.000 claims description 4
- 230000005540 biological transmission Effects 0.000 abstract description 3
- 230000000295 complement effect Effects 0.000 description 5
- 230000001143 conditioned effect Effects 0.000 description 3
- 230000003750 conditioning effect Effects 0.000 description 3
- 238000010586 diagram Methods 0.000 description 3
- 230000000694 effects Effects 0.000 description 2
- 238000000034 method Methods 0.000 description 2
- 238000004904 shortening Methods 0.000 description 2
- 238000011144 upstream manufacturing Methods 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 1
- 238000004883 computer application Methods 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 230000018109 developmental process Effects 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 238000012360 testing method Methods 0.000 description 1
- 230000001960 triggered effect Effects 0.000 description 1
- 238000010977 unit operation Methods 0.000 description 1
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
- G06F7/02—Comparing digital values
- G06F7/026—Magnitude comparison, i.e. determining the relative order of operands based on their numerical value, e.g. window comparator
Definitions
- the invention relates to a processor for character strings of variable length with a system of memory units for storing character strings, which can be addressed in pairs by program instructions and from which partial strings corresponding to the data flow width are transferred to two operand registers, with an arithmetic / logic unit for executing Processing operations, with a condition code circuit which stores signals derived from the processing results, which are used to control program branches, and with a control unit which successively addresses the partial chains of the character string pairs in the storage unit and, in successive machine cycles, the operation of the units and transfers between the units Controls units.
- a character string is a data element consisting of a byte sequence with a variable length.
- the length of a character string can range from one byte to a number of bytes, which is only limited by the size of a storage unit. It can be determined by a length code or by a special character that is contained in the string and indicates the end of the chain. It is normal for string commands that the strings to be processed have different lengths.
- Common types of processing are the comparison of two character strings and the determination of the first matching or different byte pair, the determination of a chain end character in a character string A and in a character string B, the search for a partial chain within a character string or the shifting of a character string to another storage position.
- Complex character string instructions have three operands: the address of a first character string A, the address of a second character string B, where A and B have variable lengths, and, as third operands, the address of an end-of-chain byte, which mark the end of the character strings A and B.
- Executing such a command requires a number of operations.
- the character string representing the first operand is compared byte-by-byte from left to right with the character string representing the second operand until a non-matching byte pair or a chain end byte is found. Both strings are the same if the end of the byte is found in the same bit position in both strings. If the end of the byte is found in only one of the two strings, this string is the shorter one and is considered the smaller one.
- the command execution therefore comprises the following phases: search for the end-of-chain byte in the character string A, search for the end-of-chain byte of the character string B, comparison of both character strings for mismatch, subtraction of one character string from the other to determine which character string is the smaller.
- search for the end-of-chain byte in the character string A search for the end-of-chain byte of the character string B, comparison of both character strings for mismatch, subtraction of one character string from the other to determine which character string is the smaller.
- Accelerate string commands by operating circuits that allow a number of bytes to be compared in parallel (U.S. Patent No. 4,896,133).
- the comparison operations can be performed by a bank of EXCLUSIVE-NOR circuits or by the arithmetic and logic unit of the processor in which this arrangement is used.
- the arrangement is only suitable for the parallel execution of part of the previously explained operating phases.
- the invention is based on the object of specifying an improved processor for character strings which avoids these disadvantages and which makes greater use of the principle of parallel processing.
- the features of the invention for solving this problem are characterized in claim 1. Claims 2 to 7 indicate advantageous refinements and developments of the invention.
- FIG. 1 is a block diagram of a string processor in accordance with the invention.
- Figure 2 is a table of compliance
- Figure 4 is a flow diagram of a microprogram as used in the control unit of the processor of Figure 1.
- the processor of Figure 1 contains a local memory 10, an arithmetic unit 20 and a control unit 40. These units are constructed in a conventional manner and are therefore not shown in detail here.
- the memory 10 is a fast memory of limited capacity which is arranged on the processor chip and which is connected via a multiplexer 13 to a memory unit 12 which, in a conventional manner, consists of separate semiconductor chips.
- the storage unit 12 contains a large number of character strings which, for example, form a database in their entirety. Each of these strings consists of a number of bytes, each of which represents a character. However, a different assignment between characters and bytes can also be selected, for example the representation of two characters by one byte. The number of characters belonging to a character string is variable and can be freely selected within wide limits.
- the only limitation is the capacity of the memory.
- the length of a character string is determined by an end-of-string character, which is represented by the last byte of the chain and indicates the end of the chain during processing.
- the processing is carried out by means of character string commands contained in the respective application program, which usually address two character strings of different lengths to be related to one another and control their processing.
- Typical Forms of processing are the test for equality or inequality, the determination of which character string is the larger or the smaller or in a given order scheme, such as an alphabetical order before the other character strings.
- the individual bytes of both strings must be checked in pairs to determine which byte position in the order of priority from left to right is the first byte position with different bytes.
- the string commands have three operands *: the address of a first string A, the address of a second string B and, as the third operand, the address of an end-of-chain byte, at the application programmer's choice, which marks the end of the two strings, which are usually of different lengths.
- An application program containing the string commands is stored in the memory 12.
- the microprogram that executes the character string command is located in a control memory (not shown), which is part of the control unit 40.
- the local memory 10 is successively loaded with a part of the character strings from the memory 12.
- the output of the memory 10 is connected via bus lines 14, 15 to operand registers 16, 18, each of which is designed to hold a partial chain of four bytes.
- the registers 16, 18 are loaded under the control of the control unit 40 simultaneously in one machine cycle, starting in each case with the first partial chains of two character strings A and B to be processed, which are addressed by the operand addresses in the respective character string instruction.
- these partial chains are also called A and B, partial chain A being stored in register 16 and partial chain B in register 18.
- the arithmetic unit 20 a logic unit 22 and a comparison unit 24 are connected in parallel to one another via bus lines 17 and 19. These units each receive the partial chains A and B stored in the registers simultaneously via the collecting lines 17, 19.
- the comparison unit 24 has a third input, which is connected to the output of a further register 26, in which the end of chain identifier specified by the character string command as third operands is stored in a preparatory operation from the memory 10 via the register 16 and the bus 17. This takes place before the operand partial chains are fed to the units 20, 22, 24.
- the comparison unit 24 carries out a parallel multiple comparison. It compares the identifier located in register 26 with all bytes of sub-chain A and with all bytes of sub-chain B. These comparison operations are carried out with the help of EXCLUSIVE-OR circuits, not shown.
- the comparison unit 24 has two outputs 28, 30, each with four lines.
- a signal EA (0), EA (1), EA (2) or EA (3) appears in each case on the output lines 28 if one of the four bytes of the partial chain A matches the chain end identifier in the register 26.
- Each of these signals is assigned to a byte position in sub-chain A and provides an indication that the byte supplied to unit 24 in this position matches the end-of-chain identifier.
- a signal EB (0), EB (1), EB (2) or EB (3) appears on the output lines 30 if one of the four bytes of the sub-chain B matches the chain end identifier in the register 26.
- the signal shows the Match for the assigned byte position in sub-chain B.
- the logical unit 22 optionally carries out different logical operand combinations such as AND, OR, EXCLUSIVE OR.
- the comparison operation is of interest to determine a mismatch in the supplied operand bytes.
- the contents of the four byte positions of operand A are compared with the contents of the four corresponding byte positions of operand B. This comparison also takes place in parallel. Since a mismatch is to be determined, the EXCLUSIVE-OR operation is suitable for carrying out the comparison, which delivers an output signal for each pair of operand bits if the two bits are unequal. In relation to an operand byte, this means that the output signal of one bit position is sufficient to indicate a mismatch for the respective operand byte pair.
- the logic unit 22 supplies four signals MC (0), MC (1), MC (2) and MC (3) on an output 32, each of which is assigned to a byte position of the two operands A and B. If one or more of these signals occur, this indicates that the operand bytes of the assigned position are not the same.
- the arithmetic unit 20 performs the subtraction BA. This is done by adding the two's complement of the partial chain A to the partial chain B.
- the partial chain A is fed from the register 16 to the operand A input of the arithmetic unit 20 via a complementing circuit 36.
- a complementing circuit 38 connected to the operand B input remains ineffective.
- the arithmetic unit 20 has a carry output line 34 in the highest byte position. This is the output signal of the unit 20 which is of interest in the present context.
- a carry signal "1" on line 34 indicates that operand A is smaller than operand B and the absence of such a signal indicates that operand A is larger than operand B.
- the Sub-chains A and B are understood as arithmetic operands. The following examples illustrate the operation of arithmetic unit 52 in generating these signals.
- Chain B 'binary' 0000 0000 1010 1010 0000 Olli xxxx xxxx Chain A 'binary' 00000000 1010 10100000 0110 xxxx xxxx
- Chain B 'binary' 0000 0000 1010 1010 0000 Olli xxxx xxxx Chain A 'binary' 1111 1111 0101 0101 1111 1001 xxxx xxxx
- the top line of the example specifies the byte position of the character strings (partial strings) A and B of the example, which are shown in hexadecimal form in the next two lines and in binary form in the two lines below.
- the "x" in bit position 3 means that the bytes in this position have no influence on the result and can therefore contain any characters. It can be seen that there is a mismatch (MC) in byte position 2 of both chains and that the value of the Chain A in this position is smaller than the corresponding value in chain B.
- the binary representation of chain B is repeated in the third to last line, while the penultimate line represents chain A in two's complement form, as it is for operand input A of the arithmetic unit is supplied to carry out an addition.
- the last line shows the transfers that occur during the addition.
- the lowest byte position ie byte 3 is carried as part of the two's complement formation. This is done in a known manner by a signal from the control unit 40 on line 48, which also controls the arithmetic unit 20 to carry out a subtraction.
- a carry is generated in byte position 2, which runs into byte position 1 and from there also into position 0, which in turn generates a carry on line 34. This carry serves as an indication that the chain A is smaller than the chain B.
- the logic unit 22 has compared chains A and B, which are supplied to it in real, ie not complementary binary division according to lines 4 and 5 of the example above have been.
- the logic unit 22 provides on its output line 32 an MC (2) signal which indicates that the position 2 bytes are not equal.
- This indication and the carry on line 34 are independent of the bytes in byte position 3. If this position does not generate a carry in the example above, the result is as shown. This does not change if it is assumed that a carryover occurs in position 3. In this case, the byte of chain B in position 2 is increased by one. However, this does not change the fact that a carry is still generated in this position, which leads to a carry signal on line 34.
- control unit 40 This unit generates control signals on lines 46 to 51 which lead to the individual units. These signals are generated at predefined cycle times. Access to the memory 10 is via a bus 46 in order to load the registers 16 and 18, each with four bytes of the character strings A and B. A control signal on line 47 causes these bytes to be transmitted to units 20, 22 and 24 and the complement circuit 36 is activated.
- a subtraction control signal SUB BA occurs on line 48 and a control signal VGL (A, B) on line 49 which activates the logic unit to carry out an EXCLUSIVE-OR operation, and on line 50 a control signal VGL EZ (A, B) which the Transmission of the chain end identifier EZ transmits from the register 26 to the comparison unit and activates this to carry out the multiple comparison explained above.
- the operations triggered by the control signals on lines 47 through 50 take up one machine cycle.
- the result of the processing of the sub-chains A and B in the form of the display signals EA (0..3), EB (0..3), MC (0..3) and TRANSL (O) is on the lines 28 , 30, 32 and 34. These signals arrive at a display circuit 60, which is explained with reference to FIGS. 2 and 3.
- the possible combinations of the signals MC, EA and EB are shown schematically in the left part of the table in FIG. 2 and the selection of the effective signal combinations is shown in the right part.
- the display logic 60 has a circuit 62 for shortening the effective partial chains, which takes into account a missing or incorrect alignment of the partial chains, as can occur when a physical memory limit is exceeded when accessing the character strings in the memory 12.
- the display logic 60 also has a circuit 64 for determining priority and a selection circuit 66 controlled by the carry signal on line 34.
- the circuit 62 for shortening the effective partial chains consists of AND circuits 72, 73, 74, which are selectively conditioned via a bus 70.
- Each of the four lines in the manifolds 28, 30, 32 from the output of the units 24 and 22 are each connected to one of the AND circuits 72, 73, 74 which output signals corresponding to the signals on these lines to a manifold 76 when on the manifold 70 for all four in these Units of processed bytes
- Conditioning signal on the cores of the bus that correspond to the byte positions in which no significant byte was processed. These can be, for example, bytes 2 and 3, to which the wires 71 are assigned, so that their AND circuits 72, 73 74 do not emit a signal to the bus 70.
- the connections on the input side are designated AO to A3, B0 to B3 and MO to M3, connections A0 to A3 being assigned to lines 28, connections B0 to B3 to lines 30 and connections MO to M3 to lines 32 are.
- the priority logic 64 determines in which byte position an end-of-chain character in sub-chains A or B is displayed and in which byte position a mismatch between these sub-chains is displayed.
- AND circuits 82 to 85 which inverters 78 to 80 are connected upstream.
- the AND circuit 82 receives an input signal MO from the bus which indicates a mismatch in byte position 0. This signal is only transmitted to a bus if there are no signals A0, B0, ie if no end-of-chain character is displayed in the same byte position. In this case, the AND circuit 82 is conditioned by output signals from the upstream inverters 78.
- the AND circuit 83 transmits a mismatch signal M1 to the bus 88 if neither in byte position 0 nor in byte position 1 there is a chain end Character is displayed and no mismatch is displayed in byte position 0.
- the mismatch signals M2 and M3 are transmitted to the bus 88 through AND circuits, not shown.
- the signals AO and B0 lead from the bus 76 directly to the bus 88.
- the AND circuit 84 transmits the signal AI to the bus 88 if neither an end-of-chain character nor a mismatch is indicated for byte positions 0. A corresponding transmission of the signal B1 takes place via the AND circuit 85.
- the remaining end-of-chain indication signals A2, A3 and B2, B3 are transmitted to bus 88 via AND circuits (not shown) if none of the lower byte positions indicates an end-of-chain character or a mismatch.
- Signals AO to A3, B0 to B3 and MO to M3 from the bus 88 are combined by OR circuits 89 to form signals EA, EB and MC, which are fed via a further bus 90 to the carry evaluation logic 66, which are also provided with the carry line 34 is connected from the highest byte position of the arithmetic unit 20.
- the carry evaluation logic 66 has AND circuits 91, 93, 94 and an inverter 92 and indicates on lines 95 and 96 which of the two partial chains A, B is the larger and the smaller, respectively.
- the AND circuit 91 transmits the signal MC to line 95 when it has been conditioned by a carry signal on line 34.
- Signal MC is further transmitted via AND circuit 93 to line 96 when there is no carry signal is present and the inverter 92 supplies a conditioning signal to the AND circuit 93.
- the AND circuit 94 also provides an output signal on line 97 if the signals EA and EB occur together on the bus 90, ie if an end-of-chain character has been found in both the sub-chain A and the sub-chain B.
- these signals are used to set the same condition codes as the signals on lines 95 and 96, ie that the end of sub-chain A also indicates that it is smaller than sub-chain B and that the end of sub-chain B also indicates that it is smaller than the sub-chain A.
- the byte position for which a match was found during the last sub-chain processing was displayed on a bus 100 connected to the bus 88. This display, which results directly from the input signals A0 to A3 and B0 to B3 of the bus 88, is temporarily stored in a register (not shown) for use in the execution of subsequent program instructions.
- FIG. 4 shows, in a simplified representation, the essential steps of the microprogram routine, which becomes active repeatedly in the control circuit 40 when two strings A and B are to be processed.
- This microprogram routine is stored as part of the microprogram of the processor in a memory of the control unit, not shown.
- step 101 starting with the start address specified by the string command to be executed, the first eight bytes of the string A are transferred from the storage unit 12 to the local data memory 10. At the same time, the start address is increased by eight.
- step 102 the same process takes place for the character string B.
- step 103 the first four of the bytes of the character strings A and B located in the storage unit 103 are each transferred to the registers 16 and 18. This transfer takes place in one machine cycle.
- step 104 the partial chains of A and B in the registers 16, 18 are processed in parallel in the units 20, 22 and 24 in the manner described. This processing also takes place in just one machine cycle.
- step 105 loads the second four bytes of character strings A and B from memory 10 as new partial strings of A and B into registers 16, 18.
- step 106 which corresponds to step 104.
- step 107 an inquiry is made as to whether an output signal EA, EB or MC has been determined in steps 104 or 106.
- step 101 This is done by scanning the signal state of lines 97, 98 and 99 (Fig. 3). If there is no output signal EA, EB or MC, the microprogram branches back to step 101, with which the next eight bytes in the memory unit 12 are accessed. On the other hand, if such an output signal has been detected, this means that the processing of the character strings A and B has ended. Usually, this will not already be the case after the first run of the microprogram routine according to FIG. 4, but several such runs will be necessary in order to process longer character strings. Regardless of how many runs are necessary, a YES result in step 107 branches to step 108, which sets the condition codes CC in accordance with the signal state of lines 95 to 99.
- the following step 109 ends the microprogram and at the same time the execution of the string instruction.
- the next instruction of the respective application instruction can be a branch instruction which uses the previously set condition codes CC to carry out a program branching to a program section in which the processing result of the executed string processing instruction including the address of the byte position indicating a match indicated on the output bus 100 is further used.
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Abstract
Description
Claims
Priority Applications (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
EP94928335A EP0722583A1 (de) | 1993-10-08 | 1994-09-12 | Prozessor für zeichenketten variabler länge |
US08/619,496 US5761521A (en) | 1993-10-08 | 1994-09-12 | Processor for character strings of variable length |
JP51121995A JP3183669B2 (ja) | 1993-10-08 | 1994-09-12 | 可変長の文字ストリング用のプロセッサ |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
DE4334294A DE4334294C1 (de) | 1993-10-08 | 1993-10-08 | Prozessor für Zeichenketten variabler Länge |
DEP4334294.9 | 1993-10-08 |
Publications (1)
Publication Number | Publication Date |
---|---|
WO1995010803A1 true WO1995010803A1 (de) | 1995-04-20 |
Family
ID=6499679
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
PCT/EP1994/003045 WO1995010803A1 (de) | 1993-10-08 | 1994-09-12 | Prozessor für zeichenketten variabler länge |
Country Status (5)
Country | Link |
---|---|
US (1) | US5761521A (de) |
EP (1) | EP0722583A1 (de) |
JP (1) | JP3183669B2 (de) |
DE (1) | DE4334294C1 (de) |
WO (1) | WO1995010803A1 (de) |
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US6114945A (en) * | 1997-05-08 | 2000-09-05 | Texas Instruments Incorporated | Apparatus and method for programmable fast comparison of a result of a logic operation with an selected result |
JPH1145211A (ja) * | 1997-07-28 | 1999-02-16 | Fujitsu Ltd | 情報処理装置用試験装置および情報処理装置用試験方法 |
US5944772A (en) * | 1997-11-07 | 1999-08-31 | International Business Machines Corporation | Combined adder and logic unit |
US6061775A (en) * | 1997-12-12 | 2000-05-09 | Advanced Micro Devices, Inc. | Apparatus and method for predicting a first microcode instruction of a cache line and using predecode instruction data to identify instruction boundaries and types |
US7191318B2 (en) * | 2002-12-12 | 2007-03-13 | Alacritech, Inc. | Native copy instruction for file-access processor with copy-rule-based validation |
KR20060014600A (ko) * | 2004-08-11 | 2006-02-16 | 삼성전자주식회사 | 외부 메모리에 저장된 데이터의 변경유무를 체크하는 장치및 방법 |
JP4147423B2 (ja) * | 2004-11-12 | 2008-09-10 | セイコーエプソン株式会社 | 任意精度演算器、任意精度演算方法、および電子機器 |
US7613755B1 (en) * | 2005-04-01 | 2009-11-03 | Netlogic Microsystems, Inc. | Signature searching system |
CA2604043C (en) | 2005-04-05 | 2013-08-06 | Sun-Fish Studio, Llc | Modal interval processor |
US8073893B1 (en) | 2005-08-25 | 2011-12-06 | Robert T. Jenkins | Method and/or system for comparing character expressions |
US8484236B1 (en) | 2006-06-30 | 2013-07-09 | Robert T. Jenkins and Virginia T. Jenkins | Method and/or system for processing data streams |
US7849399B2 (en) * | 2007-06-29 | 2010-12-07 | Walter Hoffmann | Method and system for tracking authorship of content in data |
WO2009105332A1 (en) * | 2008-02-18 | 2009-08-27 | Sandbridge Technologies, Inc. | Method to accelerate null-terminated string operations |
US8380779B2 (en) * | 2009-05-29 | 2013-02-19 | Freescale Semiconductor, Inc. | Technique for determining if a logical sum of a first operand and a second operand is the same as a third operand |
US9323534B2 (en) | 2013-03-15 | 2016-04-26 | Freescale Semiconductor, Inc. | Method and apparatus for detecting a collision between multiple threads of execution for accessing a memory array |
US9116799B2 (en) | 2013-06-30 | 2015-08-25 | Freescale Semiconductor, Inc. | Method for detecting bank collision at a memory and device therefor |
US20180367673A1 (en) * | 2016-12-27 | 2018-12-20 | Bronson Picket | Enhanced communication using variable length strings of alphanumerics, symbols, and other input |
US10564965B2 (en) * | 2017-03-03 | 2020-02-18 | International Business Machines Corporation | Compare string processing via inline decode-based micro-operations expansion |
US10678506B2 (en) * | 2017-08-01 | 2020-06-09 | Arm Limited | Matching consecutive values in a data processing apparatus |
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1993
- 1993-10-08 DE DE4334294A patent/DE4334294C1/de not_active Expired - Fee Related
-
1994
- 1994-09-12 US US08/619,496 patent/US5761521A/en not_active Expired - Fee Related
- 1994-09-12 EP EP94928335A patent/EP0722583A1/de not_active Ceased
- 1994-09-12 WO PCT/EP1994/003045 patent/WO1995010803A1/de not_active Application Discontinuation
- 1994-09-12 JP JP51121995A patent/JP3183669B2/ja not_active Expired - Fee Related
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Also Published As
Publication number | Publication date |
---|---|
DE4334294C1 (de) | 1995-04-20 |
JPH09503327A (ja) | 1997-03-31 |
JP3183669B2 (ja) | 2001-07-09 |
EP0722583A1 (de) | 1996-07-24 |
US5761521A (en) | 1998-06-02 |
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