WO1995001667A1 - A protection device using field effect transistors - Google Patents

A protection device using field effect transistors Download PDF

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Publication number
WO1995001667A1
WO1995001667A1 PCT/AU1994/000358 AU9400358W WO9501667A1 WO 1995001667 A1 WO1995001667 A1 WO 1995001667A1 AU 9400358 W AU9400358 W AU 9400358W WO 9501667 A1 WO9501667 A1 WO 9501667A1
Authority
WO
WIPO (PCT)
Prior art keywords
channel fet
channel
fets
terminal
unit
Prior art date
Application number
PCT/AU1994/000358
Other languages
English (en)
French (fr)
Inventor
Richard Allen Harris
Original Assignee
The University Of Queensland
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by The University Of Queensland filed Critical The University Of Queensland
Priority to DE4494617T priority Critical patent/DE4494617T1/de
Priority to GB9526606A priority patent/GB2294598B/en
Priority to KR1019950706035A priority patent/KR960703496A/ko
Priority to CA002166418A priority patent/CA2166418A1/en
Priority to AU70635/94A priority patent/AU683271B2/en
Priority to JP50316595A priority patent/JP3547135B2/ja
Publication of WO1995001667A1 publication Critical patent/WO1995001667A1/en

Links

Classifications

    • HELECTRICITY
    • H02GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02HEMERGENCY PROTECTIVE CIRCUIT ARRANGEMENTS
    • H02H9/00Emergency protective circuit arrangements for limiting excess current or voltage without disconnection
    • H02H9/02Emergency protective circuit arrangements for limiting excess current or voltage without disconnection responsive to excess current
    • H02H9/025Current limitation using field effect transistors
    • HELECTRICITY
    • H02GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02HEMERGENCY PROTECTIVE CIRCUIT ARRANGEMENTS
    • H02H9/00Emergency protective circuit arrangements for limiting excess current or voltage without disconnection
    • H02H9/04Emergency protective circuit arrangements for limiting excess current or voltage without disconnection responsive to excess voltage
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001Technical content checked by a classifier
    • H01L2924/0002Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Definitions

  • THIS INVENTION concerns a protection device.
  • the invention concerns a protection device which may function to prevent the flow of undesirable transients or isolate a load from undesirably high voltages or currents.
  • the device of the invention may be used as an alternative to a fuse. Fuses employing thermal elements or magnetic elements for effecting control are known.
  • the invention provides a protection device connectable between a supply and a load or in a circuit, the device including a unit having at least two depletion mode field effect transistors
  • FET field effect transistor
  • depletion mode transistors such as depletion mode junction field effect transistors (JFET), static induction JFET or depletion mode metal oxide semiconductor field effect transistors (OSFET) may be used to provide the device of the invention, it is preferred that JFET transistors be employed.
  • JFET depletion mode junction field effect transistors
  • OSFET depletion mode metal oxide semiconductor field effect transistors
  • the device of the invention may be either unipolar or bipolar in its operation. Where unipolar operation is required the device has only one unit of the type described above. Depending upon the direction of current flow in the circuit with which the device is associated either the p-channel or the n-channel JFET transistor is nearer the supply than the other JFET transistor and with its drain terminal coupled to the supply.
  • two units of the type described may be present connected to each other in mirror symmetry in series with the load with the p-channel JFET transistors separated by two n- channel JFET transistors.
  • one of the n-channel JFET transistors may be eliminated and by employing a respective polling diode extending between the gate terminal of the n-channel JFET transistor and the drain terminal of each p-channel JFET transistor. In this way the JFET count may be minimised.
  • the diodes connect the n-channel JFET gate appropriately for forward and reverse current polarities. The conductive state resistance of the device is reduced by eliminating one of the JFETs in this way.
  • a single unit may be employed and incorporated into a bridge rectifier circuit.
  • additional n-channel JFET transistors may be connected with their drain/source path in series with the n-channel and between the two p- channel JFET transistors to achieve a higher breakdown performance.
  • Each additional JFET transistor has two polling diodes associated with it.
  • Figure 1 is a circuit diagram illustrative of a protection device in its most basic form in accordance with an embodiment of the invention
  • FIG. 2 is a circuit diagram of a bipolar protection device in accordance with another embodiment of the invention.
  • Figure 3 is a circuit diagram of a bipolar protection device similar in operation to the device of Figure 2 except that the number of active components has been minimised;
  • Figure 4 is a circuit diagram of a bipolar protection device having higher breakdown performance than the device illustrated in Figure 3;
  • Figure 5 is an alternative embodiment of the device of the invention adapted for bipolar operation;
  • Figure 6 is a further embodiment of the device of the invention adapted for unipolar operation; and
  • Figure 7 is a further embodiment of the device according to the invention adapted for unipolar operation and similar in configuration to the embodiment shown in Figure 3.
  • a source or supply voltage is connected across terminals 1 and 2 with the polarity shown.
  • a load (not shown) is coupled across terminals 3 and 4 of the circuit.
  • the active components of the device are present as a unit 5 connected in series with the load.
  • the unit 5 consists of two depletion mode junction field effect transistors (JFETs) 6 and 7.
  • JFET 6 is an n-channel device while JFET 7 is a p-channel device.
  • the JFETs 6 and 7 are connected, the source terminals coupled to each other, and the drain terminal of JFET 6 is coupled to the gate terminal of JFET 7 and the drain terminal of JFET 7 is coupled to the gate terminal of JFET 6.
  • JFET transistors are shown in this circuit, any depletion mode field effect transistor may be used.
  • the JFET transistors illustrated may be replaced with depletion mode OSFET transistors.
  • the protection device of Figure 1 is a unipolar device and can operate as a fuse only for the flow of positive current from terminal 1 through to terminal 3 or to inhibit the flow of transients from terminal 1 to terminal 2. Because of the small junction resistance of JFET transistors 6 and 7, a small potential drop is developed across terminals 1 and 3 with the bulk of the potential drop occurring across the load connected between terminals 3 and 4. The voltage drop across JFET 7 tends to turn off JFET 6 and the small voltage drop across JFET 6 tends to turn off JFET 7. Until a threshold voltage is reached, both JFETs 6 and 7 function as small resistors.
  • the condition described holds until the potential across the channels reaches a predetermined magnitude and at a threshold current this action avalanches to a stable point where both JFET transistors are firmly in the cut-off phase and as a consequence the unit 5 will then isolate the load from the supply voltage. Removal of the driving potential which provided the threshold current resets the device to its pretriggered fully conducting state.
  • the device of Figure 1 described above functions as a fuse for positive current flowing from terminal 1 through to terminal 3.
  • Figure 2 of the drawings illustrates a device which is bipolar in its operation.
  • the active fuse of Figure 2 has a bipolar supply voltage applied across terminals 10 and 11 and the load (not shown) is coupled across terminals 12 and 13.
  • Units 14 and 15 provide for isolation of the load from the supply in response to excessive positive and negative excursions respectively.
  • Unit 14 is identical in its construction to unit 5 of Figure 1.
  • Unit 14 has an n-channel JFET transistor 16 and a p-channel JFET transistor 17 connected with the source terminals coupled to each other and the gate of each transistor connected to the drain terminal of the other transistor.
  • Unit 14 is similar in operation to unit 5 of Figure 1 in that it is operative to limit positive excursions.
  • Unit 15 consists of a p-channel JFET transistor 18 and an n-channel JFET transistor 19 with the gate of each transistor connected to the drain of the other and their source terminals connected together.
  • Unit 15 operates in a similar manner to unit 14 except that it is responsive to limit negative going excursions of current from the source or supply to the load.
  • unit 14 is shown connected in series with the load and closer to supply terminal 10, the circuit would function in the same fashion with the relative positions of units 14 and 15 transposed, that is with unit 15 in series with the load and closer to terminal 10 than unit 14.
  • the device illustrated in Figure 3 is arrived at by minimising the number of active JFET transistors employed in the bipolar protection device of Figure 2.
  • the unit 20 in Figure 3 includes a centrally located n- channel JFET transistor 21.
  • a supply potential or source is coupled between terminals 22 and 23 and a load (not shown) is coupled across terminals 24, 25.
  • the unit 20 also includes two p-channel, JFET transistors 26 and 27 as well as two diodes 28 and 29.
  • JFET transistor 26 has its gate terminal coupled to the source terminal of JFET transistor 27 and its drain terminal coupled to terminal 22.
  • the drain terminal of JFET transistor 27 is coupled to load terminal 24 while the gate terminal of that transistor is coupled to the source terminal of JFET transistor 26.
  • Diodes 28 and 29 provide for the desired poling of JFET transistor 21.
  • the device of Figure 3 operates as follows. With positive current flowing from terminal 22 to terminal 24, diodes 28, 29, 26A, 26B, 27A switch to effectively connect the gate of transistor 21 to the drain of transistor 27, the gate of transistor 27 to the source of transistor 26 and the drain terminal of FET 26 to the gate terminal of FET 26. This results in a circuit with the same electrical performance of Unit 14 ( Figure 2). With negative current flowing from terminal 22 to terminal 24, diodes 28, 29, 26A, 26B, 27A switch to effectively connect the gate of transistor 21 to the drain of transistor 26, the gate of transistor 26 to the source of transistor 27 and the drain terminal of FET 27 to the gate terminal of FET 27. This results in a circuit of the same electrical performance as Unit 15 ( Figure 2).
  • Diodes 26B extend between the drain and gate terminals of transistors 26 and 27 and ensure that positive current is able to flow from the drain to the gate of each transistor 26, 27. This allows the device to reset after a current reversal. Diodes 26B are commutation diodes.
  • the embodiment of Figure 2 may also be minimised by eliminating one of the p-channel JFETS and thereby arriving at the device shown in Figure 7.
  • the conductive channels of all three JFETs 40, 41, 42 are in series.
  • JFETs 40, 42 are n-channel JFETS while JFET 41 is a p-channel JFET.
  • Diodes 43, 44 and 45, 46 are necessary for proper biasing and poling of the transistors.
  • the device of Figure 3 has a limitation in that commercially available depletion mode JFET transistors have a relatively low breakdown strength. This characteristic limits the basic implementation of the device of Figure 3 to low voltage blocking operations.
  • the protection device of Figure 4 overcomes the low breakdown strength limitation of the device of Figure 3.
  • a supply or source potential is applied across terminals 30 and 31 and a load is coupled across terminals 32 and 33.
  • a p-channel JFET transistor 34 is coupled with its drain terminal connected to terminal 30.
  • P-channel JFET transistor 35 is coupled with its drain terminal connected to terminal 32.
  • a plurality of n- channel JFET transistors 36A, 36B, 36C, 36D, 36E may be arranged in a ladder network as shown.
  • N-channel JFET transistors 36 function in a like manner to JFET 21 of Figure 3.
  • a diode network consisting of diodes 37 is provided to ensure that the gate terminals of n-channel FET transistors 36A to 36E are appropriately biased for both positive and negative current operation.
  • a commutation diode 38 is associated with each transistor 34, 35 and function in a like fashion to diodes 26B in Figure 3.
  • the components within the broken outline A may be considered as a block and if higher breakdown protection is required further like blocks may be included in series with the JFETS 36A and 36E to achieve this. If the block A is deleted the circuit remaining resembles the circuit of Figure 2 except that additional diodes are present.
  • FIG. 5 shows a circuit diagram of another way in which the basic unit 5 in Figure 1 may be used to provide a bipolar protection device in accordance with the invention.
  • unit 50 consists of JFETs 51, 52 which are n and p-channel JFETs respectively.
  • the unit functions in exactly the same manner as unit 5 in Figure 1.
  • Diode bridge consisting of diodes 53, 54, 55, 56 is connected in series with the source and load.
  • Unit 50 is connected between the junctions 57, 58 and the diodes ensure that positive current always flows through unit 50 in the same direction. When unit 50 is conducting current may flow between the source and load. When unit 50 is non-conducting, no flow of current is possible.
  • a device like that shown in Figure 5 would only be used where the source voltage was greater than the junction voltage drop of two of the diodes in the circuit.
  • Figure 6 shows a device including a unit 60 identical to the unit 5 in Figure 1.
  • Unit 60 includes a p-channel JFET 61 with its conductive channel in series with the conductive channel, of n-channel JFET 62 connected as shown.
  • JFET 63 is an n-channel JFET of high breakdown voltage and such JFETs are typically more expensive than low breakdown voltage JFETs 61, 62.
  • JFETs 61 and 62 may be replaced with a unitary p-channel JFET having the same breakdown voltage characteristics as JFET 63 and those two JFETS configured as a unit, the circuit shown in Figure 6 is more economical.
  • the Figure 6 circuit is unipolar. If desired the unit 60 and the series connected JFET 63 may be used in the circuit of Figure 5 in place of unit 50 to provide a high voltage protection device.

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Junction Field-Effect Transistors (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Emergency Protection Circuit Devices (AREA)
  • Electronic Switches (AREA)
PCT/AU1994/000358 1993-07-01 1994-06-29 A protection device using field effect transistors WO1995001667A1 (en)

Priority Applications (6)

Application Number Priority Date Filing Date Title
DE4494617T DE4494617T1 (de) 1993-07-01 1994-06-29 Schutzvorrichtung unter Verwendung von Feldeffekttransistoren
GB9526606A GB2294598B (en) 1993-07-01 1994-06-29 A protection device using field effect transistors
KR1019950706035A KR960703496A (ko) 1993-07-01 1994-06-29 보호 디바이스(a protection device using field effect transistors)
CA002166418A CA2166418A1 (en) 1993-07-01 1994-06-29 A protection device using field effect transistors
AU70635/94A AU683271B2 (en) 1993-07-01 1994-06-29 A protection device using field effect transistors
JP50316595A JP3547135B2 (ja) 1993-07-01 1994-06-29 電界効果トランジスタを用いた保護デバイス

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
AUPL9711 1993-07-01
AUPL971193 1993-07-01

Publications (1)

Publication Number Publication Date
WO1995001667A1 true WO1995001667A1 (en) 1995-01-12

Family

ID=3777023

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/AU1994/000358 WO1995001667A1 (en) 1993-07-01 1994-06-29 A protection device using field effect transistors

Country Status (7)

Country Link
JP (1) JP3547135B2 (de)
KR (1) KR960703496A (de)
CA (1) CA2166418A1 (de)
DE (1) DE4494617T1 (de)
GB (1) GB2294598B (de)
NZ (1) NZ267940A (de)
WO (1) WO1995001667A1 (de)

Cited By (18)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1998049762A1 (de) * 1997-04-25 1998-11-05 Siemens Aktiengesellschaft Vorrichtung zum begrenzen elektrischer wechselströme, insbesondere im kurzschlussfall
DE19725870A1 (de) * 1997-06-18 1999-01-07 Siemens Ag Begrenzerschaltung für Wechselströme
EP1815573A2 (de) * 2004-11-09 2007-08-08 Fultec Semiconductor Inc. Mit sehr hohen spannungen kompatible integrierte transiente blockiereinheit
US7262946B2 (en) 2003-08-21 2007-08-28 Fultec Semiconductor, Inc. Integrated electronic disconnecting circuits, methods, and systems
US7342433B2 (en) 2004-11-09 2008-03-11 Fultec Semiconductor, Inc. Apparatus and method for enhanced transient blocking
US7369387B2 (en) 2004-11-09 2008-05-06 Fultec Semiconductor, Inc. Apparatus and method for temperature-dependent transient blocking
WO2008137312A1 (en) * 2007-05-03 2008-11-13 Dsm Solutions, Inc. Jfet passgate circuit and method of operation
US7492566B2 (en) 2005-01-14 2009-02-17 Bourns, Inc. Low resistance transient blocking unit
WO2009035643A1 (en) * 2007-09-10 2009-03-19 Fultec Semiconductor, Inc. Common gate connected high voltage transient blocking unit
US7576962B2 (en) 2005-06-16 2009-08-18 Bourns, Inc. Transient blocking apparatus with reset
US7646576B2 (en) 2004-11-09 2010-01-12 Bourns, Inc. Apparatus and method for high-voltage transient blocking using low voltage elements
WO2010020898A1 (en) * 2008-08-19 2010-02-25 Nxp B.V. A surge protection circuit
WO2012093177A3 (en) * 2011-01-07 2013-01-10 Infineon Technologies Austria Ag Semiconductor device arrangement with a first semiconductor device and with a plurality of second semi conductor devices
US8455948B2 (en) 2011-01-07 2013-06-04 Infineon Technologies Austria Ag Transistor arrangement with a first transistor and with a plurality of second transistors
US8866253B2 (en) 2012-01-31 2014-10-21 Infineon Technologies Dresden Gmbh Semiconductor arrangement with active drift zone
US9400513B2 (en) 2014-06-30 2016-07-26 Infineon Technologies Austria Ag Cascode circuit
EP3386056A1 (de) * 2017-03-28 2018-10-10 Semtech Corporation Verfahren und vorrichtung zum schutz vor elektrischer überlastung und elektrostatischer entladung
CN109115308A (zh) * 2018-09-26 2019-01-01 惠州华阳通用电子有限公司 一种车辆油量检测装置及方法

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
AUPS045702A0 (en) * 2002-02-12 2002-03-07 Fultech Pty Ltd A protection device
EP2634882B1 (de) 2012-02-29 2014-09-17 ABB Technology Ltd Gleichstromversorgungseinheit für eine Stromversorgungseinheit

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US4533970A (en) * 1983-06-27 1985-08-06 Motorola, Inc. Series current limiter
JPH0348456A (ja) * 1989-07-14 1991-03-01 Masaya Maruo 過電流保護回路と半導体装置
JPH0353613A (ja) * 1989-07-21 1991-03-07 Masaya Maruo 過電流保護回路と半導体装置
JPH0365020A (ja) * 1989-07-31 1991-03-20 Masaya Maruo 過電流保護回路と半導体装置
JPH03145918A (ja) * 1989-10-31 1991-06-21 Masaya Maruo 過電圧過電流保護回路
AU7503591A (en) * 1990-04-28 1991-11-07 Alcatel N.V. Current limiter circuit
DE4022253A1 (de) * 1990-07-11 1992-01-16 Krone Ag Strombegrenzungsschaltung

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US5696659A (en) * 1993-02-10 1997-12-09 Maruo; Masaya Overcurrent protective circuit and semiconductor device

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US4533970A (en) * 1983-06-27 1985-08-06 Motorola, Inc. Series current limiter
JPH0348456A (ja) * 1989-07-14 1991-03-01 Masaya Maruo 過電流保護回路と半導体装置
JPH0353613A (ja) * 1989-07-21 1991-03-07 Masaya Maruo 過電流保護回路と半導体装置
JPH0365020A (ja) * 1989-07-31 1991-03-20 Masaya Maruo 過電流保護回路と半導体装置
JPH03145918A (ja) * 1989-10-31 1991-06-21 Masaya Maruo 過電圧過電流保護回路
AU7503591A (en) * 1990-04-28 1991-11-07 Alcatel N.V. Current limiter circuit
DE4022253A1 (de) * 1990-07-11 1992-01-16 Krone Ag Strombegrenzungsschaltung

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PATENT ABSTRACTS OF JAPAN, E-1070, page 43; & JP,A,03 053 613 (MASAYA MARUO) 7 March 1991. *
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Cited By (31)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1998049762A1 (de) * 1997-04-25 1998-11-05 Siemens Aktiengesellschaft Vorrichtung zum begrenzen elektrischer wechselströme, insbesondere im kurzschlussfall
DE19725870A1 (de) * 1997-06-18 1999-01-07 Siemens Ag Begrenzerschaltung für Wechselströme
US7262946B2 (en) 2003-08-21 2007-08-28 Fultec Semiconductor, Inc. Integrated electronic disconnecting circuits, methods, and systems
EP1815573A4 (de) * 2004-11-09 2011-06-01 Fultec Semiconductor Inc Mit sehr hohen spannungen kompatible integrierte transiente blockiereinheit
EP1815573A2 (de) * 2004-11-09 2007-08-08 Fultec Semiconductor Inc. Mit sehr hohen spannungen kompatible integrierte transiente blockiereinheit
US7342433B2 (en) 2004-11-09 2008-03-11 Fultec Semiconductor, Inc. Apparatus and method for enhanced transient blocking
US7369387B2 (en) 2004-11-09 2008-05-06 Fultec Semiconductor, Inc. Apparatus and method for temperature-dependent transient blocking
US7646576B2 (en) 2004-11-09 2010-01-12 Bourns, Inc. Apparatus and method for high-voltage transient blocking using low voltage elements
US7492566B2 (en) 2005-01-14 2009-02-17 Bourns, Inc. Low resistance transient blocking unit
US7576962B2 (en) 2005-06-16 2009-08-18 Bourns, Inc. Transient blocking apparatus with reset
WO2008137312A1 (en) * 2007-05-03 2008-11-13 Dsm Solutions, Inc. Jfet passgate circuit and method of operation
GB2466393B (en) * 2007-09-10 2012-12-05 Bourns Inc Common gate connected high voltage transient blocking unit
WO2009035643A1 (en) * 2007-09-10 2009-03-19 Fultec Semiconductor, Inc. Common gate connected high voltage transient blocking unit
GB2466393A (en) * 2007-09-10 2010-06-23 Fultec Semiconductor Inc Common gate connected high voltage transient blocking unit
US8593772B2 (en) 2008-08-19 2013-11-26 Nxp, B.V. Surge protection circuit
WO2010020898A1 (en) * 2008-08-19 2010-02-25 Nxp B.V. A surge protection circuit
US9431382B2 (en) 2011-01-07 2016-08-30 Infineon Technologies Austria Ag Semiconductor device arrangement with a first semiconductor device and with a plurality of second semiconductor devices
WO2012093177A3 (en) * 2011-01-07 2013-01-10 Infineon Technologies Austria Ag Semiconductor device arrangement with a first semiconductor device and with a plurality of second semi conductor devices
US8455948B2 (en) 2011-01-07 2013-06-04 Infineon Technologies Austria Ag Transistor arrangement with a first transistor and with a plurality of second transistors
CN103503138A (zh) * 2011-01-07 2014-01-08 英飞凌科技奥地利有限公司 具有第一半导体器件并具有多个第二半导体器件的半导体器件装置
US8569842B2 (en) 2011-01-07 2013-10-29 Infineon Technologies Austria Ag Semiconductor device arrangement with a first semiconductor device and with a plurality of second semiconductor devices
US8970262B2 (en) 2011-01-07 2015-03-03 Infineon Technologies Austria Ag Semiconductor device arrangement with a first semiconductor device and with a plurality of second semiconductor devices
EP2924735A1 (de) * 2011-01-07 2015-09-30 Infineon Technologies Austria AG Schaltungsanordnung mit einem ersten halbleiterbauelement und mit einer vielzahl von sekundären halbleiterbauelementen
US9972619B2 (en) 2011-01-07 2018-05-15 Infineon Technologies Austria Ag Semiconductor device arrangement with a first semiconductor device and with a plurality of second semiconductor devices
US8866253B2 (en) 2012-01-31 2014-10-21 Infineon Technologies Dresden Gmbh Semiconductor arrangement with active drift zone
US9530764B2 (en) 2012-01-31 2016-12-27 Infineon Technologies Dresden Gmbh Semiconductor arrangement with active drift zone
US9400513B2 (en) 2014-06-30 2016-07-26 Infineon Technologies Austria Ag Cascode circuit
EP3386056A1 (de) * 2017-03-28 2018-10-10 Semtech Corporation Verfahren und vorrichtung zum schutz vor elektrischer überlastung und elektrostatischer entladung
US10692854B2 (en) 2017-03-28 2020-06-23 Semtech Corporation Method and device for electrical overstress and electrostatic discharge protection
US11380672B2 (en) 2017-03-28 2022-07-05 Semtech Corporation Method and device for electrical overstress and electrostatic discharge protection
CN109115308A (zh) * 2018-09-26 2019-01-01 惠州华阳通用电子有限公司 一种车辆油量检测装置及方法

Also Published As

Publication number Publication date
JPH08512191A (ja) 1996-12-17
GB2294598A (en) 1996-05-01
KR960703496A (ko) 1996-08-17
GB2294598B (en) 1997-11-19
GB9526606D0 (en) 1996-02-28
DE4494617T1 (de) 1996-11-21
CA2166418A1 (en) 1995-01-12
JP3547135B2 (ja) 2004-07-28
NZ267940A (en) 1996-09-25

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