CA2166418A1 - A protection device using field effect transistors - Google Patents
A protection device using field effect transistorsInfo
- Publication number
- CA2166418A1 CA2166418A1 CA002166418A CA2166418A CA2166418A1 CA 2166418 A1 CA2166418 A1 CA 2166418A1 CA 002166418 A CA002166418 A CA 002166418A CA 2166418 A CA2166418 A CA 2166418A CA 2166418 A1 CA2166418 A1 CA 2166418A1
- Authority
- CA
- Canada
- Prior art keywords
- channel fet
- terminal
- diode
- fets
- gate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Abandoned
Links
Classifications
-
- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02H—EMERGENCY PROTECTIVE CIRCUIT ARRANGEMENTS
- H02H9/00—Emergency protective circuit arrangements for limiting excess current or voltage without disconnection
- H02H9/02—Emergency protective circuit arrangements for limiting excess current or voltage without disconnection responsive to excess current
- H02H9/025—Current limitation using field effect transistors
-
- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02H—EMERGENCY PROTECTIVE CIRCUIT ARRANGEMENTS
- H02H9/00—Emergency protective circuit arrangements for limiting excess current or voltage without disconnection
- H02H9/04—Emergency protective circuit arrangements for limiting excess current or voltage without disconnection responsive to excess voltage
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Junction Field-Effect Transistors (AREA)
- Semiconductor Integrated Circuits (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
- Emergency Protection Circuit Devices (AREA)
- Electronic Switches (AREA)
Abstract
A device which may protect circuits or equipment from overload or transients is disclosed. The device includes a unit (5) consisting of a p-channel FET (7) and an n-channel FET (6) connected with their conductive channels in series and the gate of each transistor coupled to the drain terminal of the other.
Description
W095/01667 2 1 6 6 ~ ~ ~ PCT/AU94/00358 TITLE
A PROTECTION DEVICE USING FIELD EPFECT TRANSISTORS
FIELD OF THE INVENTION
THIS INVENTION roncerns a ~o~euLion device.
In particular, the invention con~ns a protection device which may function to ~lUVU~t the flow of undesirable transients or isolate a load from undesirably high voltages or currents.
BA~K~KOuND OF THE INVENTION
The device of the invention may be used as an alternative to a fuse. Fuses employing thermal elements or magnetic elements for effecting control are known.
It is an ob~ect of the present invention to provide an active fuse which may serve as an alternative to these known types of fuses or for inhibiting the flow of transients.
DT~rosuRE OF THE INVENTION
According to one aspect, the invention provides a protection device ~-onnectable between a supply and a loaid or in a circuit, the device including a unit having at least two depletion mode field effect transistors (FET) with one being an n-chAnnel FET and the other a p-chAnn~l FET with the gate terminal of one transistor co~n~cted to the drain terminal of the other transistor and the source terminals conn~ted to each other.
While any suitable depletion mode transistors suGh as depletion mode ~unction field effect transistors (J~ET), static induction JFET or depletion mode metal oxide semiconductor field effect transistors (MOSFET) may be used to provide the device of the invention, it is preferred that JFET transistors be employed.
The device of the invention may be either unipolar or bipolar in its operation. Where unipolar operation is required the device has only one unit of the type described above. Depen~ ng upon the direction of current flow in the circuit with which the device is associated either the p-chAnnel or the n-chAnn~l JFET
transistor is nearer the supply than the other JFET
WO9S/01667 i~ PCTIAU94/00358 21~4~ 2 transistor and with its drain terminal coupled to the supply.
For bipolar operation it is preferred that two units of the type described may be present ~-onn~ted to each other in mirror symmetry in series with the load with the p-ch~nnel JFET transistors separated by two n-ch~nnel JFET transistors. With such a configuration, one of the n-~hAnn~l JFET transistors may be eliminated and by employing a respective polling diode exten~ng between the gate te~ in~l of the n-ch~nn~l JFET transistor and the drain terminal of each p-c~nnel JFET transistor. In this way the JFET count may be minimised. The diodes connect the n-ch~nnel JFET gate appropriately for forward and reverse current polarities. The con~llctive state resistance of the device is re~-)re~ by eliminating one of the JFETs in this way. As an alternative to employing two units of the abovementioned type to provide a bipolar e~ion device, a single unit may be employed and incorporated into a bridge rectifier circuit.
If desired, additional n-chAnnel JFET
transistors may be con~e.,~ed with their drain/source path in series with the n-chAn~el and between the two p-ch~nnel JFET transistors to achieve a higher breakdown performance. Each additionAl JFET transistor has two polling diodes ~c~oci~ted with it.
DTs~r~cuRE OF THE DRAWINGS
Particular preferred ~ ho~iments of the invention will now be descrlbed by way of example with reference to the drawings in which:
Figure l is a circuit diagram illustrative of a protection device in its most basic form in accordance with an embodiment of the invention:
Figure 2 is a circuit diagram of a bipolar protection device in accordance with another embodiment of the invention;
Figure 3 is a circuit diagram of a bipolar protection device similar in operation to the device of Figure 2 except that the nll~her of active ~o~ ents has 2 ~ ~ 6 41 S PCT/AU94/00358 .
been minimised;
Figure 4 is a circuit diagram of a bipolar protection device having h ~ g~e~ breakdown performance than the device illustrated in Figure 3, 5Figure 5 is an alternative embodiment of the device of the invention adapted for bipolar operation;
Figure 6 is a further embodiment of the device of the invention adapted for unipolar operation; and Figure 7 is a further embodiment of the device acaording to the invention adapted for unipolar operation and similar in configuration to the embodiment shown in Fiyure 3.
DETAILED DESCRIPTION OF THE DRAWINGS
As shown in Figure 1, a source or supply voltage is ~onnected across terminals 1 and 2 with the polarity shown. A load (not shown) is coupled across te ~nAl~ 3 and 4 of the circuit. The active components of the device are present as a unit 5 connected in series wi~h the load. The unit 5 cons~cts of two depletion mode ~unction field effect transistors (JFETs) 6 and 7. JFET
6 is an n-rhAnnel device while JFET 7 is a p-~h~nn~l device. The JFETs 6 and 7 are con~cted, the source terminals coupled to each other, and the drain terminal of JFET 6 is coupled to the gate terminal of JFET 7 and the drain terminal of JFET 7 is coupled to the gate terminal of JFET 6. Although JFET transistors are shown in this circuit, any depletion mode field effect tr2nsistor may be used. For example, the JFET
tr2nsistors illustrated may be replaced with depletion mode MOSFET transistors.
The operation of the circuit shown in Figure 1 is as follows. With a supply voltage conn~r-ted across term~nAl~ 1 and 2 with the polarity shown, the protection device of Figure 1 is a unipolar device and can operate as a fuse only for the flow of positive current from terminal 1 through to terminal 3 or to inhibit the flow of transients from terminal 1 to terminal 2. Because of the small ~unction resistance of JFET transistors 6 and 21G~418 7, a small potential drop is developed across terminals 1 and 3 with the bulk of the potentlal drop occurring across the load conne~ted between terminals 3 and 4. The t voltage drop across JFET 7 tends to turn off JFET 6 and the small voltage drop across JFET 6 tends to turn off JFET 7. Until a threshold voltage is reach~, both JFETs 6 and 7 function as small resistors. Dep~n~ ng upon the pinch off voltage characteristics of the JFET transistors employed, the condition described holds until the potential across the r,h~nnel ~ re~hes a predetermined magnitude and at a threshold current this action avAlAnch~ to a stable point where both JFET transistors are firmly in the cut-off phase and as a con~e~uence the unit 5 will then isolate the load from the supply voltage. Removal of the driving potential which provided the thr~chnl~ current resets the device to its pretriggered fully conAl~cting state.
The device of Figure 1 described above functions as a fuse for positive current flowing from terminal 1 through to terminal 3.
Figure 2 of the drawings illustrates a device which is bipolar in its operation. The active fuse of Figure 2 has a bipolar supply voltage applied across terminals lO and 11 and the load (not shown) is coupled across terminals 12 and 13. Units 14 and 15 provide for isolation of the load from the supply in response to ~Y~e~c~ve positive and negative excursions respectively.
Unit 14 is identical in its construction to unit 5 of Figure 1. Unit 14 has an n-~hAnnel JFET transistor 16 and a p-chAnn~l JFET transistor 17 ~-onnected with the source terminals coupled to each other and the gate of each transistor co~nected to the drain terminal of the other transistor. Unit 14 is similar in operation to unit 5 of Figure 1 in that it is operative to limit positive excursions. Unit 15 consists of a p-ch~n~el JFET transistor 18 and an n-~h~nn~l JFET transistor 19 with the gate of each transistor co~nected to the drain of the other and their source terminals connected W095/01667 2 ~ PCT/AU94/00358 together. Unit 15 operates in a similar manner to unit 14 except that it is responsive to limit negative going excursions of current from the source or supply to the load. Although in Figure 2 unit 14 is shown connected in series with the load and closer to supply terminal 10, the circuit would function in the same fashion with the relative positions of units 14 and 15 transposed, that is wit;h unit 15 in series with the load and closer to terminal 10 than unit 14.
The device illustrated in Figure 3 is arrived at by minimising the number of active JFET transistors employed in the bipolar protection device of Figure 2.
With the units 14 and 15 of Figure 2 transposed in the manner described above, n-ch~nnel JFET transistors 16 and 19 would be adjacent to one another and as a consequence one of these JFET transistors may be eliminated. This is how the configuration of Figure 3 is arrived at. The unit 20 in Figure 3 includes a centrally located n-ch~nnel JFET transistor 21. A supply potential or source is coupled between terminals 22 and 23 and a load (not shown) is coupled across tel ~n~l ~ 24, 25. The unit 20 also includes two p-ch~nn~l~ JFET transistors 26 and 27 as well as two diodes 28 and 29. JFET transistor 26 has its gate terminal coupled to the source terminal of JFET
transistor 27 and its drain terminal coupled to terminal 22. The drain terminal of JFET transistor 27 is coupled to load terminal 24 while the gate te, i n~ 1 of that transistor is coupled to the source ter~i n~ 1 of JFET
transistor 26. Diodes 28 and 29 provide for the desired poling of JFET transistor 21.
The device of Figure 3 operates as follows.
With positive current flowing from terminal 22 to terminal 24, diodes 28, 29, 26A, 26B, 27A switch to effectively conn~ct the gate of transistor 21 to the drain of transistor 27, the gate of transistor 27 to the source of transistor 26 and the drain terminal of FET 26 to the gate te, in~l of FET 26. This results in a circuit with the same electrical performance of Unit 14 -~641~
(Figure 2). With negative current flowing from terminal 22 to terminal 24, diodes 28, 29, 26A, 26B, 27A switch to effectively co~nect the gate of transistor 21 to the drain of transistor 26, the gate of transistor 26 to the source of transistor 27 and the drain terminal of FET 27 to the gate terminal of FET 27. This results in a circuit of the same electrical performance as Unit 15 (Figure 2). Diodes 26B extend between the drain and gate terminals of transistors 26 and 27 and ensure that positive current is able to flow from the drain to the gate of each transistor 26, 27. This allows the device to reset after a current reversal. Diodes 26B are commutation diodes.
The embodiment of Figure 2 may also be minimised by eliminating one of the p-ch~nn~l JFETS and thereby arriving at the device shown in Figure 7. In Figure 7 the conductive chAnn~l~ of all three JFETs 40, 41, 42 are in series. JFETs 40, 42 are n-~h~nn~l JFETS
while JFET 41 is a p-chAnn~l JFET. Diodes 43, 44 and 45, 46 are n~-e~y for proper biasing and poling of the transistors.
The device of Figure 3 has a limitation in that commercially available depletion mode JFET transistors have a relatively low breakdown strength. This characteristic limits the basic implementation of the device of Figure 3 to low voltage blocking operations.
The protection device of Figure 4 overcomes the low breakdown strength limitation of the device of Figure 3. In Figure 4 a supply or source potential is applied across terminals 30 and 31 and a load is coupled across terminals 32 and 33. A p-ch~nnel JFET transistor 34 is coupled with its drain teL ~nAl co~cted to teL i n~ 1 30.
p-~h~nn~l JFET transistor 35 is coupled with its drain terminal ~onnected to terminal 32. A plurality of n- r ~h~nnel JFET transistors 36A, 36B, 36C, 36D, 36E may be arranged in a ladder network as shown. N-~h~nn~l JFET
transistors 36 function in a like manner to JFET 21 of Figure 3. A diode network consisting of diodes 37 is W095/01667 PCTtAU94/00358 4 1 ~
provided to ensure that the gate terminals of n-ch~nnel FET transistors 36A to 36E are appropriately biased for both positive and negative current operation. A
co~mutation diode 38 is ACCOC~ ated with each transistor 534, 35 and function in a like fashion to diodes 26B in Figure 3. The components within the broken outline A may be considered as a block and if higher breakdown o~ ion is required further like blocks may be included in series with the JFETS 36A and 36E to achieve this. If the block A is deleted the circuit rem~ining resembles the circuit of Figure 2 except that additional c are present.
Figure 5 shows a circuit diagram of another way in which the basic unit 5 in Figure 1 may be used to provide a bipolar protection device in accordance with the invention. In Figure 5 unit 50 consists of JFETs 51, 52 which are n and p-rh~n~l JFETs respectively. The unit functions in exactly the same manner as unit 5 in Figure 1. Diode bridge, consisting of diodes 53, 54, 55, 56 is connected in series with the source and load. Unit 50 is ~o~n~ted between the ~unctions 57, 58 and the diodes ensure that positive current always flows through unit 50 in the same direction. When unit 50 is conducting current may flow between the source and load.
When unit 50 is non-conducting, no flow of current is possible.
A device like that shown in Figure 5 would only be used where the source voltage was greater than the ~unction voltage drop of two of the diodes in the circuit.
Figure 6 shows a device including a unit 60 identical to the unit 5 in Figure 1. Unit 60 includes a p-rh~nnel JFET 61 with its conductive ~h~nn~l in series with the conductive channel, of n-rh~nn~l JFET 62 co~nected as shown. JFET 63 is an n-ch~nnel JFET of high breakdown voltage and such JFETs are typically more expensive than low breakdown voltage JFETs 61, 62.
Although JFETs 61 and 62 may be replaced with a unitary ~,~66~ 8 ~
p-nhAnnel JFET having the same breakdown voltage characterlstics as JFET 63 and those two JFETS configured as a unit, the circuit shown in Figure 6 is more economical. The Figure 6 circuit is unipolar. If desired the unit 60 and the series co~nected JFET 63 may be used in the circuit of Figure 5 in place of unit 50 to provide a high voltage protection device.
A PROTECTION DEVICE USING FIELD EPFECT TRANSISTORS
FIELD OF THE INVENTION
THIS INVENTION roncerns a ~o~euLion device.
In particular, the invention con~ns a protection device which may function to ~lUVU~t the flow of undesirable transients or isolate a load from undesirably high voltages or currents.
BA~K~KOuND OF THE INVENTION
The device of the invention may be used as an alternative to a fuse. Fuses employing thermal elements or magnetic elements for effecting control are known.
It is an ob~ect of the present invention to provide an active fuse which may serve as an alternative to these known types of fuses or for inhibiting the flow of transients.
DT~rosuRE OF THE INVENTION
According to one aspect, the invention provides a protection device ~-onnectable between a supply and a loaid or in a circuit, the device including a unit having at least two depletion mode field effect transistors (FET) with one being an n-chAnnel FET and the other a p-chAnn~l FET with the gate terminal of one transistor co~n~cted to the drain terminal of the other transistor and the source terminals conn~ted to each other.
While any suitable depletion mode transistors suGh as depletion mode ~unction field effect transistors (J~ET), static induction JFET or depletion mode metal oxide semiconductor field effect transistors (MOSFET) may be used to provide the device of the invention, it is preferred that JFET transistors be employed.
The device of the invention may be either unipolar or bipolar in its operation. Where unipolar operation is required the device has only one unit of the type described above. Depen~ ng upon the direction of current flow in the circuit with which the device is associated either the p-chAnnel or the n-chAnn~l JFET
transistor is nearer the supply than the other JFET
WO9S/01667 i~ PCTIAU94/00358 21~4~ 2 transistor and with its drain terminal coupled to the supply.
For bipolar operation it is preferred that two units of the type described may be present ~-onn~ted to each other in mirror symmetry in series with the load with the p-ch~nnel JFET transistors separated by two n-ch~nnel JFET transistors. With such a configuration, one of the n-~hAnn~l JFET transistors may be eliminated and by employing a respective polling diode exten~ng between the gate te~ in~l of the n-ch~nn~l JFET transistor and the drain terminal of each p-c~nnel JFET transistor. In this way the JFET count may be minimised. The diodes connect the n-ch~nnel JFET gate appropriately for forward and reverse current polarities. The con~llctive state resistance of the device is re~-)re~ by eliminating one of the JFETs in this way. As an alternative to employing two units of the abovementioned type to provide a bipolar e~ion device, a single unit may be employed and incorporated into a bridge rectifier circuit.
If desired, additional n-chAnnel JFET
transistors may be con~e.,~ed with their drain/source path in series with the n-chAn~el and between the two p-ch~nnel JFET transistors to achieve a higher breakdown performance. Each additionAl JFET transistor has two polling diodes ~c~oci~ted with it.
DTs~r~cuRE OF THE DRAWINGS
Particular preferred ~ ho~iments of the invention will now be descrlbed by way of example with reference to the drawings in which:
Figure l is a circuit diagram illustrative of a protection device in its most basic form in accordance with an embodiment of the invention:
Figure 2 is a circuit diagram of a bipolar protection device in accordance with another embodiment of the invention;
Figure 3 is a circuit diagram of a bipolar protection device similar in operation to the device of Figure 2 except that the nll~her of active ~o~ ents has 2 ~ ~ 6 41 S PCT/AU94/00358 .
been minimised;
Figure 4 is a circuit diagram of a bipolar protection device having h ~ g~e~ breakdown performance than the device illustrated in Figure 3, 5Figure 5 is an alternative embodiment of the device of the invention adapted for bipolar operation;
Figure 6 is a further embodiment of the device of the invention adapted for unipolar operation; and Figure 7 is a further embodiment of the device acaording to the invention adapted for unipolar operation and similar in configuration to the embodiment shown in Fiyure 3.
DETAILED DESCRIPTION OF THE DRAWINGS
As shown in Figure 1, a source or supply voltage is ~onnected across terminals 1 and 2 with the polarity shown. A load (not shown) is coupled across te ~nAl~ 3 and 4 of the circuit. The active components of the device are present as a unit 5 connected in series wi~h the load. The unit 5 cons~cts of two depletion mode ~unction field effect transistors (JFETs) 6 and 7. JFET
6 is an n-rhAnnel device while JFET 7 is a p-~h~nn~l device. The JFETs 6 and 7 are con~cted, the source terminals coupled to each other, and the drain terminal of JFET 6 is coupled to the gate terminal of JFET 7 and the drain terminal of JFET 7 is coupled to the gate terminal of JFET 6. Although JFET transistors are shown in this circuit, any depletion mode field effect tr2nsistor may be used. For example, the JFET
tr2nsistors illustrated may be replaced with depletion mode MOSFET transistors.
The operation of the circuit shown in Figure 1 is as follows. With a supply voltage conn~r-ted across term~nAl~ 1 and 2 with the polarity shown, the protection device of Figure 1 is a unipolar device and can operate as a fuse only for the flow of positive current from terminal 1 through to terminal 3 or to inhibit the flow of transients from terminal 1 to terminal 2. Because of the small ~unction resistance of JFET transistors 6 and 21G~418 7, a small potential drop is developed across terminals 1 and 3 with the bulk of the potentlal drop occurring across the load conne~ted between terminals 3 and 4. The t voltage drop across JFET 7 tends to turn off JFET 6 and the small voltage drop across JFET 6 tends to turn off JFET 7. Until a threshold voltage is reach~, both JFETs 6 and 7 function as small resistors. Dep~n~ ng upon the pinch off voltage characteristics of the JFET transistors employed, the condition described holds until the potential across the r,h~nnel ~ re~hes a predetermined magnitude and at a threshold current this action avAlAnch~ to a stable point where both JFET transistors are firmly in the cut-off phase and as a con~e~uence the unit 5 will then isolate the load from the supply voltage. Removal of the driving potential which provided the thr~chnl~ current resets the device to its pretriggered fully conAl~cting state.
The device of Figure 1 described above functions as a fuse for positive current flowing from terminal 1 through to terminal 3.
Figure 2 of the drawings illustrates a device which is bipolar in its operation. The active fuse of Figure 2 has a bipolar supply voltage applied across terminals lO and 11 and the load (not shown) is coupled across terminals 12 and 13. Units 14 and 15 provide for isolation of the load from the supply in response to ~Y~e~c~ve positive and negative excursions respectively.
Unit 14 is identical in its construction to unit 5 of Figure 1. Unit 14 has an n-~hAnnel JFET transistor 16 and a p-chAnn~l JFET transistor 17 ~-onnected with the source terminals coupled to each other and the gate of each transistor co~nected to the drain terminal of the other transistor. Unit 14 is similar in operation to unit 5 of Figure 1 in that it is operative to limit positive excursions. Unit 15 consists of a p-ch~n~el JFET transistor 18 and an n-~h~nn~l JFET transistor 19 with the gate of each transistor co~nected to the drain of the other and their source terminals connected W095/01667 2 ~ PCT/AU94/00358 together. Unit 15 operates in a similar manner to unit 14 except that it is responsive to limit negative going excursions of current from the source or supply to the load. Although in Figure 2 unit 14 is shown connected in series with the load and closer to supply terminal 10, the circuit would function in the same fashion with the relative positions of units 14 and 15 transposed, that is wit;h unit 15 in series with the load and closer to terminal 10 than unit 14.
The device illustrated in Figure 3 is arrived at by minimising the number of active JFET transistors employed in the bipolar protection device of Figure 2.
With the units 14 and 15 of Figure 2 transposed in the manner described above, n-ch~nnel JFET transistors 16 and 19 would be adjacent to one another and as a consequence one of these JFET transistors may be eliminated. This is how the configuration of Figure 3 is arrived at. The unit 20 in Figure 3 includes a centrally located n-ch~nnel JFET transistor 21. A supply potential or source is coupled between terminals 22 and 23 and a load (not shown) is coupled across tel ~n~l ~ 24, 25. The unit 20 also includes two p-ch~nn~l~ JFET transistors 26 and 27 as well as two diodes 28 and 29. JFET transistor 26 has its gate terminal coupled to the source terminal of JFET
transistor 27 and its drain terminal coupled to terminal 22. The drain terminal of JFET transistor 27 is coupled to load terminal 24 while the gate te, i n~ 1 of that transistor is coupled to the source ter~i n~ 1 of JFET
transistor 26. Diodes 28 and 29 provide for the desired poling of JFET transistor 21.
The device of Figure 3 operates as follows.
With positive current flowing from terminal 22 to terminal 24, diodes 28, 29, 26A, 26B, 27A switch to effectively conn~ct the gate of transistor 21 to the drain of transistor 27, the gate of transistor 27 to the source of transistor 26 and the drain terminal of FET 26 to the gate te, in~l of FET 26. This results in a circuit with the same electrical performance of Unit 14 -~641~
(Figure 2). With negative current flowing from terminal 22 to terminal 24, diodes 28, 29, 26A, 26B, 27A switch to effectively co~nect the gate of transistor 21 to the drain of transistor 26, the gate of transistor 26 to the source of transistor 27 and the drain terminal of FET 27 to the gate terminal of FET 27. This results in a circuit of the same electrical performance as Unit 15 (Figure 2). Diodes 26B extend between the drain and gate terminals of transistors 26 and 27 and ensure that positive current is able to flow from the drain to the gate of each transistor 26, 27. This allows the device to reset after a current reversal. Diodes 26B are commutation diodes.
The embodiment of Figure 2 may also be minimised by eliminating one of the p-ch~nn~l JFETS and thereby arriving at the device shown in Figure 7. In Figure 7 the conductive chAnn~l~ of all three JFETs 40, 41, 42 are in series. JFETs 40, 42 are n-~h~nn~l JFETS
while JFET 41 is a p-chAnn~l JFET. Diodes 43, 44 and 45, 46 are n~-e~y for proper biasing and poling of the transistors.
The device of Figure 3 has a limitation in that commercially available depletion mode JFET transistors have a relatively low breakdown strength. This characteristic limits the basic implementation of the device of Figure 3 to low voltage blocking operations.
The protection device of Figure 4 overcomes the low breakdown strength limitation of the device of Figure 3. In Figure 4 a supply or source potential is applied across terminals 30 and 31 and a load is coupled across terminals 32 and 33. A p-ch~nnel JFET transistor 34 is coupled with its drain teL ~nAl co~cted to teL i n~ 1 30.
p-~h~nn~l JFET transistor 35 is coupled with its drain terminal ~onnected to terminal 32. A plurality of n- r ~h~nnel JFET transistors 36A, 36B, 36C, 36D, 36E may be arranged in a ladder network as shown. N-~h~nn~l JFET
transistors 36 function in a like manner to JFET 21 of Figure 3. A diode network consisting of diodes 37 is W095/01667 PCTtAU94/00358 4 1 ~
provided to ensure that the gate terminals of n-ch~nnel FET transistors 36A to 36E are appropriately biased for both positive and negative current operation. A
co~mutation diode 38 is ACCOC~ ated with each transistor 534, 35 and function in a like fashion to diodes 26B in Figure 3. The components within the broken outline A may be considered as a block and if higher breakdown o~ ion is required further like blocks may be included in series with the JFETS 36A and 36E to achieve this. If the block A is deleted the circuit rem~ining resembles the circuit of Figure 2 except that additional c are present.
Figure 5 shows a circuit diagram of another way in which the basic unit 5 in Figure 1 may be used to provide a bipolar protection device in accordance with the invention. In Figure 5 unit 50 consists of JFETs 51, 52 which are n and p-rh~n~l JFETs respectively. The unit functions in exactly the same manner as unit 5 in Figure 1. Diode bridge, consisting of diodes 53, 54, 55, 56 is connected in series with the source and load. Unit 50 is ~o~n~ted between the ~unctions 57, 58 and the diodes ensure that positive current always flows through unit 50 in the same direction. When unit 50 is conducting current may flow between the source and load.
When unit 50 is non-conducting, no flow of current is possible.
A device like that shown in Figure 5 would only be used where the source voltage was greater than the ~unction voltage drop of two of the diodes in the circuit.
Figure 6 shows a device including a unit 60 identical to the unit 5 in Figure 1. Unit 60 includes a p-rh~nnel JFET 61 with its conductive ~h~nn~l in series with the conductive channel, of n-rh~nn~l JFET 62 co~nected as shown. JFET 63 is an n-ch~nnel JFET of high breakdown voltage and such JFETs are typically more expensive than low breakdown voltage JFETs 61, 62.
Although JFETs 61 and 62 may be replaced with a unitary ~,~66~ 8 ~
p-nhAnnel JFET having the same breakdown voltage characterlstics as JFET 63 and those two JFETS configured as a unit, the circuit shown in Figure 6 is more economical. The Figure 6 circuit is unipolar. If desired the unit 60 and the series co~nected JFET 63 may be used in the circuit of Figure 5 in place of unit 50 to provide a high voltage protection device.
Claims (26)
1. An isolation device connectable between a supply and a load or in a circuit, the device including a unit having at least two depletion mode field effect transistors with one said transistor being an n-channel FET and the other said transistor being a p-channel FET
with the gate terminal of the one transistor being connected to the drain terminal of the other transistor, the gate terminal of the other transistor being connected to the drain terminal of the one transistor and the source terminals of the transistors being connected to each other whereby the device is operative to present an effective open circuit when threshold voltage of at least a predetermined magnitude is developed across the drain and source terminals of the transistors.
with the gate terminal of the one transistor being connected to the drain terminal of the other transistor, the gate terminal of the other transistor being connected to the drain terminal of the one transistor and the source terminals of the transistors being connected to each other whereby the device is operative to present an effective open circuit when threshold voltage of at least a predetermined magnitude is developed across the drain and source terminals of the transistors.
2. The device of Claim 1 wherein the gate terminal of the one transistor is directly connected to the drain terminal of the other transistor, the gate terminal of the other transistor is directly connected to the drain terminal of the one transistor and the source terminals of the transistors are directly connected to each other.
3. The device of Claim 2 including a high breakdown voltage FET having its conductive channel in series with the unit to provide a high voltage protection unit.
4. The device of Claim 3 wherein the high breakdown voltage FET is an n-channel FET.
5. The device of Claim 1 including a diode bridge circuit consisting of a first diode with its anode coupled to input terminal and its cathode being connected to a first intermediate terminal, a second diode with its cathode coupled to the first intermediate terminal and its anode connected to an output terminal, a third diode having its cathode connected to the input terminal and its anode connected to a second intermediate terminal, a fourth diode having its cathode connected to the output terminal and its anode connected to the second intermediate terminal and the unit connected between the intermediate terminals.
6. The device of Claim 5 wherein the anode of the first diode is directly connected to the input terminal, the cathode of the second diode is directly coupled to the first intermediate terminal, the cathode of the third diode is directly connected to the input terminal and its anode is directly connected to the second intermediate terminal and the cathode of the fourth diode is directly connected to the output terminal.
7. The device of Claim 3 including a diode bridge circuit consisting of a first diode with its anode connected to input terminal and its cathode connected to a first intermediate terminal, a second diode with its cathode connected to a first intermediate terminal and its anode connected to an output terminal, a third diode having its cathode connected to the input terminal and its anode connected to a second intermediate terminal, a fourth diode having its cathode connected to the output terminal and its anode connected to the second intermediate terminal and said high voltage protection unit connected between the intermediate terminals.
8. The device of Claim 7 wherein the anode of the first dfiode in the bridge is directly connected to the input terminal and its cathode is directly connected to the first intermediate terminal, the cathode of the second diode of the bridge is directly connected to the first intermediate terminal and its anode is directly connected to an output terminal, the cathode of a third diode of the bridge is directly connected to the input terminal and its anode is directly connected to the second intermediate terminal, the cathode of the fourth diode of the bridge is directly connected to the output terminal and its anode is directly connected to the second intermediate terminal.
9. The device of Claim 1 including two said units connected in mirror symmetry and connectable in series in the circuit or between the supply and the load.
10. An isolation device connectable between a supply and a load or in a circuit, the device including a first p-channel FET, a second p-channel FET, and an n-channel FET having its conductive channel between and in series with the conductive channels of the p-channel FETs, a respective diode connected between the gate terminal of the n-channel FET and each said p-channel FET
with the anode of the diodes coupled to the gate of the n-channel FET and the cathode connected to the drain of each said p-channel FET, a respective diode connected between the source of the second p-channel FET and the gate of the first p-channel FET and between the source of the first p-channel FET and the gate of the second p-channel FET wherein the FETs are depletion mode FETs whereby the device is operative to present an effective open circuit when a threshold voltage of at least a predetermined magnitude is developed across the conductive channels of the FETs.
with the anode of the diodes coupled to the gate of the n-channel FET and the cathode connected to the drain of each said p-channel FET, a respective diode connected between the source of the second p-channel FET and the gate of the first p-channel FET and between the source of the first p-channel FET and the gate of the second p-channel FET wherein the FETs are depletion mode FETs whereby the device is operative to present an effective open circuit when a threshold voltage of at least a predetermined magnitude is developed across the conductive channels of the FETs.
11. The device of Claim 10 wherein the diodes are directly connected.
12. The device of Claim 11 including a respective diode directly coupled between the drain and gate terminals of each of the p-channel FETs.
13. An isolation device connectable between a supply and a load or in a circuit, the device including a first n-channel FET, a second n-channel FET and a p-channel FET having its conductive channel between and in series with the conductive channels of the n-channel FETs, a respective diode connected between the gate terminal of the p-channel FET and each said n-channel FET
with the cathode of the diodes coupled to the gate of the p-channel FET and the anode coupled to the drain terminal of the p-channel FET, a respective diode connected between the source of the second n-channel FET and the gate of the first n-channel FET and between the source of the first n-channel FET and the gate of the second n-channel FET and wherein the FETs are depletion mode FETs.
with the cathode of the diodes coupled to the gate of the p-channel FET and the anode coupled to the drain terminal of the p-channel FET, a respective diode connected between the source of the second n-channel FET and the gate of the first n-channel FET and between the source of the first n-channel FET and the gate of the second n-channel FET and wherein the FETs are depletion mode FETs.
14. The device of Claim 13 wherein the diodes are directly connected.
15. The device of Claim 13 including a respective diode directly coupled between the drain and gate terminals of each of the n-channel FETs.
16. An isolation device connectable between a supply and a load or in a circuit, the device including an upstream unit consisting of a p-channel FET and an n-channel FET downstream thereof with their conductive channels in series, the gate terminal of the p-channel FET being connected to the drain terminal of the n-channel FET and the source terminals of the FETS being connected to each other, a downstream unit configured like the upstream unit but in mirror symmetry and having a p-channel FET and an n-channel FET with their conductive channels in series with the p-channel FET of the downstream unit being connectable to the load, and at least one circuit block for enhancing breakdown performance of the device arranged between and in series with the upstream unit and the downstream unit whereby the device is operative to present an effective open circuit when a threshold voltage of at least a predetermined magnitude is developed across the conductive channels of the FETs.
17. The device of Claim 16 wherein the circuit block includes three n-channel FET transistors with their conductive channels in series, a respective commutating diode connected between the gate terminal of each FET of the circuit block and an adjacent said FET of the block and two of the FETS of the circuit block having their gate terminal connected to an adjacent FET of the upstream and the downstream unit.
18. The device of Claim 17 wherein the gate of the p-channel FET in each of the upstream and the downstream units is connected to the drain terminal of the n-channel FET in the respective said upstream and said downstream unit via a diode.
19. The device of Claim 18 including a respective diode connected between the gate and drain terminals of each said p-channel FET of the upstream and the downstream units.
20. The device of Claim 18 or 19 wherein the diodes are directly connected.
21. An isolation device connectable between a supply and a load or in a circuit, the device including an upstream unit consisting of an n-channel FET and a p-channel FET downstream thereof with their conductive channels in series, the gate terminal of the n-channel FET being connected to the drain terminal of the p-channel FET and the source terminals of the FETS being connected to each other, a downstream unit configured like the upstream unit but in mirror symmetry and having an n-channel FET and a p-channel FET with their conductive channels in series with the n-channel FET of the downstream unit being connectable to the load, and at least one circuit block for enhancing breakdown performance of the device arranged between and in series with the upstream and downstream units and wherein the FETS are depletion mode FETS whereby the device is operative to present an effective open circuit when a threshold voltage of at least a predetermined magnitude is developed across the conductive channels of the FETS.
22. The device of Claim 21 wherein the circuit block includes three p-channel FETS with their conductive channels in series, a respective commutating diode connected between the gate terminal of each FET of the circuit block and an adjacent said FET of the block and two of the FETS of the circuit block having their gate terminal connected to an adjacent FET of the upstream and the downstream unit.
23. The device of Claim 22 including a respective diode connected between the gate and drain terminals of each said n-channel FET of the upstream and the downstream units.
24. The device of any one of Claims 1 to 23 wherein said FETS are JFETS.
25. The device of any one of Claims 1 to 23 wherein said FETS are MOSFETS.
26. The device of any one of Claims 1 to 23 wherein said FETs are static induction FETs.
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| AUPL971193 | 1993-07-01 | ||
| AUPL9711 | 1993-07-01 | ||
| PCT/AU1994/000358 WO1995001667A1 (en) | 1993-07-01 | 1994-06-29 | A protection device using field effect transistors |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CA2166418A1 true CA2166418A1 (en) | 1995-01-12 |
Family
ID=3777023
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CA002166418A Abandoned CA2166418A1 (en) | 1993-07-01 | 1994-06-29 | A protection device using field effect transistors |
Country Status (7)
| Country | Link |
|---|---|
| JP (1) | JP3547135B2 (en) |
| KR (1) | KR960703496A (en) |
| CA (1) | CA2166418A1 (en) |
| DE (1) | DE4494617T1 (en) |
| GB (1) | GB2294598B (en) |
| NZ (1) | NZ267940A (en) |
| WO (1) | WO1995001667A1 (en) |
Families Citing this family (20)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TW407371B (en) * | 1997-04-25 | 2000-10-01 | Siemens Ag | Equipment to limited alternative current, especially in short-circuit case |
| DE19725870A1 (en) * | 1997-06-18 | 1999-01-07 | Siemens Ag | AC limiting circuit based on silicon-carbide FETs |
| AUPS045702A0 (en) * | 2002-02-12 | 2002-03-07 | Fultech Pty Ltd | A protection device |
| WO2005020402A1 (en) | 2003-08-21 | 2005-03-03 | Fultec Pty Ltd | Integrated electronic disconnecting circuits methods, and systems |
| US7342433B2 (en) | 2004-11-09 | 2008-03-11 | Fultec Semiconductor, Inc. | Apparatus and method for enhanced transient blocking |
| US7646576B2 (en) | 2004-11-09 | 2010-01-12 | Bourns, Inc. | Apparatus and method for high-voltage transient blocking using low voltage elements |
| US7369387B2 (en) | 2004-11-09 | 2008-05-06 | Fultec Semiconductor, Inc. | Apparatus and method for temperature-dependent transient blocking |
| US20060098363A1 (en) * | 2004-11-09 | 2006-05-11 | Fultec Semiconductors, Inc. | Integrated transient blocking unit compatible with very high voltages |
| US7492566B2 (en) | 2005-01-14 | 2009-02-17 | Bourns, Inc. | Low resistance transient blocking unit |
| US7576962B2 (en) | 2005-06-16 | 2009-08-18 | Bourns, Inc. | Transient blocking apparatus with reset |
| US20080272823A1 (en) * | 2007-05-03 | 2008-11-06 | Dsm Solutions, Inc. | JFET Passgate Circuit and Method of Operation |
| WO2009035643A1 (en) * | 2007-09-10 | 2009-03-19 | Fultec Semiconductor, Inc. | Common gate connected high voltage transient blocking unit |
| WO2010020898A1 (en) * | 2008-08-19 | 2010-02-25 | Nxp B.V. | A surge protection circuit |
| US8455948B2 (en) | 2011-01-07 | 2013-06-04 | Infineon Technologies Austria Ag | Transistor arrangement with a first transistor and with a plurality of second transistors |
| US8569842B2 (en) * | 2011-01-07 | 2013-10-29 | Infineon Technologies Austria Ag | Semiconductor device arrangement with a first semiconductor device and with a plurality of second semiconductor devices |
| US8866253B2 (en) | 2012-01-31 | 2014-10-21 | Infineon Technologies Dresden Gmbh | Semiconductor arrangement with active drift zone |
| EP2634882B1 (en) | 2012-02-29 | 2014-09-17 | ABB Technology Ltd | DC supply unit for a power provision unit |
| US9400513B2 (en) | 2014-06-30 | 2016-07-26 | Infineon Technologies Austria Ag | Cascode circuit |
| US10692854B2 (en) | 2017-03-28 | 2020-06-23 | Semtech Corporation | Method and device for electrical overstress and electrostatic discharge protection |
| CN109115308B (en) * | 2018-09-26 | 2020-11-06 | 惠州华阳通用电子有限公司 | Vehicle oil quantity detection device and method |
Family Cites Families (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS579291B2 (en) * | 1974-02-04 | 1982-02-20 | ||
| US4533970A (en) * | 1983-06-27 | 1985-08-06 | Motorola, Inc. | Series current limiter |
| JPH07112045B2 (en) * | 1989-07-14 | 1995-11-29 | 昌也 圓尾 | Overcurrent protection circuit and semiconductor device |
| JPH0353613A (en) * | 1989-07-21 | 1991-03-07 | Masaya Maruo | Overcurrent protection circuit and semiconductor device |
| JPH0365020A (en) * | 1989-07-31 | 1991-03-20 | Masaya Maruo | Overcurrent protective circuit and semiconductor device |
| JPH03145918A (en) * | 1989-10-31 | 1991-06-21 | Masaya Maruo | Overvoltage/overcurrent protecting circuit |
| DE4013731C2 (en) * | 1990-04-28 | 1995-07-13 | Sel Alcatel Ag | Circuit arrangement for limiting the inrush current |
| DE4022253A1 (en) * | 1990-07-11 | 1992-01-16 | Krone Ag | Current limiting circuit for telecommunication installation - couples source electrodes of two FETs via resistance |
| EP0684677B1 (en) * | 1993-02-10 | 2003-12-17 | Line Electronics Corporation | Overcurrent protective circuit and semiconductor device |
-
1994
- 1994-06-29 DE DE4494617T patent/DE4494617T1/en not_active Ceased
- 1994-06-29 JP JP50316595A patent/JP3547135B2/en not_active Expired - Lifetime
- 1994-06-29 GB GB9526606A patent/GB2294598B/en not_active Expired - Lifetime
- 1994-06-29 WO PCT/AU1994/000358 patent/WO1995001667A1/en active Application Filing
- 1994-06-29 NZ NZ267940A patent/NZ267940A/en unknown
- 1994-06-29 CA CA002166418A patent/CA2166418A1/en not_active Abandoned
- 1994-06-29 KR KR1019950706035A patent/KR960703496A/en not_active Application Discontinuation
Also Published As
| Publication number | Publication date |
|---|---|
| GB9526606D0 (en) | 1996-02-28 |
| JP3547135B2 (en) | 2004-07-28 |
| KR960703496A (en) | 1996-08-17 |
| GB2294598B (en) | 1997-11-19 |
| JPH08512191A (en) | 1996-12-17 |
| DE4494617T1 (en) | 1996-11-21 |
| NZ267940A (en) | 1996-09-25 |
| WO1995001667A1 (en) | 1995-01-12 |
| GB2294598A (en) | 1996-05-01 |
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| Date | Code | Title | Description |
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| EEER | Examination request | ||
| FZDE | Dead |