JPH0365020A - Overcurrent protective circuit and semiconductor device - Google Patents

Abstract

PURPOSE:To interrupt overcurrent by employing the differential potential of an N-type DFET as the gate voltage of a P-type DFET and the differential potential of the P-type DFET as the gate voltage of the N-type DFET. CONSTITUTION:Gate voltage of a P-type JFET 2 increases as the differential voltage of an N-type junction field effect semiconductor (N-type JFET) 1 increases while the gate voltage of the N-type JFET 1 increases as the differential potential of the P-type JFET 2 increases. Consequently, the N-type JFET 1 and the P-type JFET 2 are saturated and the current is suppressed. When the voltage VAB between points A, B increases further, differential potential of the N-type JFET 1 and the P-type JFET 2 increases further and the gate voltage thereof increases further thus reducing the current. When the gate voltage of the N-type JFET 1 and the P-type JFET 2 increases further, the gate voltage thereof increases further thus reducing the current furthermore. Current can be interrupted by repeating the operation.

Description

DETAILED DESCRIPTION OF THE INVENTION (1) Field of Industrial Application The present invention relates to an overcurrent protection circuit and a semiconductor device using a depletion type field effect semiconductor that protects a circuit as a load from overcurrent.

(2) Conventional Technology Protection circuits such as fuses, breakers, transistors, thyristors, etc. are used as devices connected in series to a load to protect the load from overcurrent. Fuses melt when excessive current flows, so they must be replaced each time.

Breakers cannot be used in circuits that require quick action because their breaking speed is slow. Protection circuits such as transistors and thyristors not only need to be connected in series to the load, but also require a separate power source to operate them. Also, if a separate power supply is not required, this protection circuit must be connected in parallel to the load, just like a constant voltage circuit or constant current circuit. For these, this protection circuit is
Unlike fuses and breakers, they cannot be easily installed where needed in series with the load.

(3) Purpose of the Invention The present invention can be easily installed in series with a load where necessary, like a fuse or breaker, and there is no need to replace it every time an overcurrent flows. Another object of the present invention is to provide an overcurrent protection circuit using N-type/P-type depletion field effect semiconductors, which can be of a fast acting type or a delayed type and does not require a separate power source, and a semiconductor device thereof. .

(4) Summary of the Invention The present invention is an overcurrent protection circuit using a depletion type (both junction type and insulated gate type) field effect semiconductor and its semiconductor device. An overview of the overcurrent protection circuit will be explained. The source of an N-type depletion type field effect semiconductor (hereinafter abbreviated as N-type DFET) and the source of a P-type depletion type field effect semiconductor (hereinafter abbreviated as P-type DFET) are connected, and the gate of the P-type DFET is connected through a resistor. , or directly N
The drain of the N-type DFET and the gate of the N-type DFET are connected through a capacitor to the drain of the N-type DFET and through a resistor to the drain of the P-type DFET. With this connection, the potential difference in the N-type DFET is
This becomes the gate voltage of the P-type DFET, and the potential difference in the P-type DFET becomes the gate voltage of the N-type DFET. N type D
A positive voltage is applied to the drain of the FET and a negative voltage is applied to the drain of the P-type DFET, and as the voltage gradually increases, the currents flowing through the N-type DFET and the P-type DFET gradually increase. When the voltage increases, the current increases beyond a certain value, and the potential difference between the N-type and P-type DFETs increases beyond a certain value, the gate voltage of the N-type and P-type DFET increases, so the N-type and P-type The DFET will suppress the current. As the voltage becomes larger, the potential difference across the N-type and P-type DFET becomes larger, the gate voltage of the N-type and P-type DFET becomes larger, and the current decreases. The larger the voltage, the larger the gate voltage and the smaller the current. This is repeated and the current is cut off. In this way, in this overcurrent protection circuit, the potential difference in the N-type DFET is
The potential difference in the P-type DFET becomes the gate voltage of the N-type DFET, so that the N-type D
The FET and the P-type DFET act complementary to each other to cut off overcurrent (abnormal current). This is an overcurrent protection circuit that protects the load from overcurrent by connecting a capacitor to the gate and connecting it in series to the load to make the interrupting characteristic interlocking or delaying.

In another circuit, the gate of the N-type DFET is
Connect to the drain of N-type DFET through a capacitor, and connect to the drain of P-type DFET through a resistor. P
The gate of the DFET is connected to the drain of the P-type DFET through a resistor and to the drain of the N-type DFET through a diode. A diode begins to conduct current little by little when its forward voltage reaches approximately 0.3V, 0.4V (hereinafter abbreviated as approximately 0.4V). Therefore, the diode is non-conductive when the forward voltage is below about 0.4V, and becomes conductive when the forward voltage is above about 0.4V. For this reason,
P until the forward voltage of the diode reaches about 0.4V.
The gate of the type DFET is connected to the drain of the P type DFET, and the P type DFET is connected to the drain of the P type DFET.
A current larger than the saturation current can flow when the gate of the N-type DFET is connected to the drain of the N-type DFET. When the forward voltage of the diode becomes approximately 0.4 V or more, the gate of the P-type DFET is connected to the drain of the N-type DFET, and the current in the P-type DFET gradually decreases. After that, the drain of N-type DFET and the drain of P-type DFE are connected.
When the voltage applied to the drain of T becomes larger, the potential difference across the N-type DFET becomes the gate voltage of the P-type DFET, and the potential difference across the P-type DFET becomes the gate voltage of the N-type DFET.
By becoming the gate voltage of T, the N-type DFET and P
type DFETs work complementarily to block overcurrent.

This is an overcurrent protection circuit that protects the load from overcurrent by connecting a capacitor to the gate and connecting it in series to the load to make the cutoff characteristic fast or slow. And this is the semiconductor device.

(5) Examples of the Invention The present invention will be explained in detail with reference to Examples. One embodiment of a protection circuit using a junction field effect semiconductor will be described with reference to FIG. N-type junction field effect semiconductor (hereinafter referred to as N-type JFET)
The source of a P-type junction field effect semiconductor (hereinafter abbreviated as P-type JFET) 2 is connected to the source of a P-type junction field effect semiconductor (hereinafter abbreviated as P-type JFET) 2. N type J
FETI gate line, N type JF through capacitor 3
Connected to the drain of ETI and connected to P-type JFE through resistor 4.
Connect to the drain of T2. The gate of the P-type JFET 2 is connected through the resistor 5 or directly to the drain of the N-type JFETI. With this connection, N-type JFETI
The potential difference in the P-type JFET2 becomes the gate voltage of the P-type JFET2, and the potential difference in the P-type JFET2 becomes the gate voltage of the N-type JFETI.

With the drain of N-type JFET1 being positive and the drain of P-type JFET2 being negative, the voltage vAB applied between the drain of N-type JFET1 and the drain of P-type JFET2 (hereinafter abbreviated as A-B) gradually increases. Then, N type J
The current (2) flowing through the FETI and the P-type JFET2 increases little by little. Until the voltage VAB reaches a certain value, the current I
becomes larger, but the voltage VA! When l becomes larger than a certain value, the gate voltage of P-type JFET2 becomes larger and P-type JFET2 becomes larger.
When the potential difference in type JFET2 increases, the N type JFET2 increases.
The gate voltage of ETI increases, and N-type JFETI and P
The type JFET2 is saturated and the current is suppressed. When the voltage VAN between A and B further increases, the N-type JF
The potential difference between ETI and P-type JFET2 becomes larger, the gate voltages of N-type JFET1 and P-type JIFET2 become larger, and the current decreases. And the voltage v
As AB becomes larger, the gate voltage becomes larger and the current decreases more. This is repeated and the current I is cut off. In this way, this overcurrent protection circuit
N-type JFETI and P-type JFET2 act complementarily to interrupt overcurrent (abnormal current). Figure 9 shows A-B.
Voltage between vA! The outline of the interrupting characteristics is shown with l on the horizontal axis and current ■ on the vertical axis.

By changing the semiconductor characteristics (conductance, pinch-off voltage, etc.) of the N-type JFETI and P-type JFET 2, the cutoff characteristics can be changed as shown in (A) and (D).

When the load circuit is powered on, an inrush current flows through the load circuit, but the protection circuit allows the inrush current to flow without being shut off.
A certain range of delay is required.

In addition, even if a short-term pulse-like abnormal current flows into the load circuit when a normal current is flowing, the permissible abnormal current of a certain value or less for a certain period of time must be allowed to flow without being interrupted. It is necessary to have a cutoff characteristic that can cut off abnormal currents that are not permissible. By connecting a capacitor, the cut-off time can be adjusted by the time constant determined by the capacitor and the resistor connected in series.

The gate of N type JFETI is connected to N by capacitor 3.
It is connected to the drain of the type JFET I, and is connected to the drain of the P type JFET 2 by a resistor 4. Now, when an inrush current at power-on or an allowable abnormal current within the time constant of the capacitor and resistor flows in the load circuit, N
Since the gate of type JFETI is connected to the drain of N-type JFET1 by capacitor 3, even if an inrush current or abnormal current flows, N-type JFETI will not shut off.
Since the voltage drop between the drain and source of the N-type JFETI is small, the gate voltage of the P-type JFET2 is small, and the P-type JFET2 is not cut off. If an abnormal current exceeding the time constant due to the capacitor and resistor flows, the N-type JFET
The gate of I is now connected to the drain of P-type JFET 2, and N-type JFETI and P-type JFET 2 act complementary to each other to cut off abnormal current.

The capacitor can be connected to the gate of P-type JFET2, or to the gates of both N-type JFETI and P-type JFET2.

A variable capacitance diode can also be used as the capacitor.

It is also possible to replace the N-type JFETI and the P-type JFET 2 with depression type joint gate type field effect semiconductor devices.

By connecting N-type JFETs and P-type JFETs with different semiconductor characteristics (conductance, pinch-off voltage, etc.) in parallel to N-type JFETI and P-type JFET2, the cutoff characteristics can be changed.

Next, referring to FIG. 2, one embodiment of a semiconductor device that combines the overcurrent protection circuit of FIG. 1 will be described.

A P+ type silicon region 7 is formed on an N type silicon substrate 6,
An N-type silicon region 8 is formed in the P+-type silicon region 7, and an N-type J FET 8 is provided. Further, a P-type silicon region 9 is formed on the N-type silicon substrate 6, and a P-type JFET 9 is provided. The P1 type silicon region 7 is connected to the P type J through a resistor.
Connected to the drain of FET9. The capacitance between the N type silicon substrate 6 and the P+ type silicon region 7 is used as a variable capacitance diode. Then, each electrode is formed and wired in the same manner as in FIG. The N-type silicon substrate 6 is assumed to be positive, and the t' rain of P-type JFET 9 is assumed to be negative.

Next, an embodiment of another overcurrent protection circuit using a junction field effect semiconductor will be described with reference to FIG.

Connect the source of N-type JFETIO and the source of P-type JFETII. The gate of N-type JFETIO is connected through a capacitor 12 to the drain of N-type JFETIO, and through a resistor 13 to the drain of P-type JFETII. The gate of P-type JFETII is connected to the drain of P-type JFETII through a resistor 14 and to the drain of N-type JFETIO through a diode. With this connection, the potential difference at N-type JFETIO is reduced to P-type JFETIO.
This becomes the gate voltage of ETII, and the potential difference at P-type JFETII becomes the gate voltage of N-type JFETIO. N
Plus the drain of type JFETIO, P type JFETII
between the drain of N-type JFETIO and the drain of P-type JFETII (hereinafter C-D
As the voltage vcI) applied to
becomes larger little by little. The diode is non-conductive when the forward voltage is about 0.4V or less, and becomes conductive when the forward voltage is about 0.4V or more. Therefore, the gate of the P-type JFET II is connected to the drain of the P-type JFET II until the voltage VCt) becomes large and the forward voltage of the diode reaches about 0.4V. P-type JFET11
If the pinch-off voltage of is set to be lower than the voltage at which the diode becomes conductive, such as 0.1 V, about 0°4■,
P-type JFETII is P-type JFETII (7) game) 7
5 (F't of N-type JFETIo.

Saturation current when connected to in ((ke) in Figure 12)
) can flow a larger current ((g) in Figure 12). The forward voltage of the diode is approximately 0.4V.
In this case, the gate 1 of the P-type rFETII is connected to the drain of the tN-type JFETIO, and the current of the P-type JFETII gradually decreases ((r) in FIG. 12). Then the voltage V. When I) becomes even larger, N-type JFETIO, P-type, and rFETII act complementary to each other to cut off overcurrent and protect the load from overcurrent, and by changing the time constant by capacitor 12 and resistor 13. , is an overcurrent protection circuit that can change the delay of the cutoff characteristic.

FIG. 10 shows an outline of the interrupting characteristics with the voltage vo between CD and D on the horizontal axis and the current I on the vertical axis. N type JFETIO
By changing the semiconductor characteristics (conductance, pinch-off voltage, etc.) of P-type JFET II and
) (o) (force). You can also connect a diode to an N-type JFET and a capacitor to a P-type JFET.

Figure 4 shows the addition of the second N-type JFETI6 to Figure 3.
During or after interrupting the abnormal current, the second N-type JF
A large abnormal voltage is applied to ET, and N-type JFETIO and P
This prevents large abnormal voltages from being applied to type JFET II.

Next, one embodiment of a semiconductor device incorporating the overcurrent protection circuit shown in FIG. 4 will be described with reference to FIG. N-type silicon substrate 1
7, a P+ type silicon region 18.21 is formed. P”
forming an N-type silicon region 19 in the type silicon region 18;
A P-type silicon region 20 is formed in the N-type silicon region 19 to provide a P-type JFE 720.

The area between the P1 type silicon region 18 and the N type silicon region 18 is used as a diode. The diode is P type JF
It can also be provided in the P+ type silicon region 18 that is not under the E720 or in a place other than the P+ type silicon region 18. An N-type silicon region 22 is formed in the P1-type silicon region 2I so that one side communicates with the outside of the P+-type silicon region 21, and an N-type JFE 722 is provided. In the N-type silicon region 23 sandwiched between the two P4-type silicon regions 21, an N-type J
FET23 is provided. The capacitance between the N-type silicon substrate 17 and the P1-type silicon region 2I is used as a variable capacitance diode.

P+ type silicon region 21 and N type silicon region 19 are connected to the drain of P type J-FE 720 through their respective resistors. P4″ type silicon lti area] 8c, N
Type J F ET 22 (7) connected to the drain. Then, each electrode is formed and wired as shown in FIG. The N-type silicon substrate 17 is a positive terminal, and the drain of the PlJFET 20 is a negative terminal.

Next, an embodiment of another overcurrent protection circuit using a junction anti-field effect semiconductor will be described with reference to FIG.

The source of the N-type JFET 24 and the source of the P-type JFET 25 are connected. The gate of N-type JFET24 is connected to resistor 30
It is connected to the drain of the N-type JFET 24 through a capacitor 29, and connected to the drain of the P-type JFET 25 through a resistor 3I and a diode 32. P type J F E
T25(7)'7'-to is a P-type JFE through a resistor.
Connected to the drain of T25 and connected to N through diode 26.
Connect to the drain of type JFET24.

Plus the drain of N-type JFET24, P-type JFET2
between the drain of N-type JFET 24 and the drain of P-type JFET 25 (hereinafter E-
When the voltage vtF applied across
becomes larger little by little. Until the forward voltage of the diode reaches approximately 0.4V, the gate of N-type JFET24 is
This means that it is connected to the drain of the N-type JFET 24, and the gate of the P-type JFET 25 is connected to the drain of the P-type JFET 25. Therefore, the pinch-off voltage of N-type JFET24 and P-type JFET25 is set to 0.
．． The voltage at which the diode becomes conductive, such as lV, is approximately 0.
゜When set smaller than 4V, the N type JFET24 becomes N
A current larger than the saturation current can flow when the gate of the P-type JFET 24 is connected to the drain of the P-type JFET 25. It is possible to flow a current larger than the saturation current when the current is present. Then, when the forward voltage of the diode becomes approximately 0.4 V or more, the gate of the N-type JFET 24 is switched to the P-type JFET 25.
is connected to the drain of P-type JFET25.
The gate of is connected to the drain of N-type JFET24, and N-type JFET24 and P-type JFET25 are
Gradually reduce the current. Then the voltage V. When becomes even larger, the N-type JFET 24 and the P-type JFET 25 act complementary to each other to cut off the overcurrent, protecting the load from the overcurrent, and by changing the time constant of the capacitor 29 and resistor 31. This is an overcurrent protection circuit that can change the delay characteristics. FIG. 11 shows the voltage y+! between E and F! The outline of the interrupting characteristics is shown with , on the horizontal axis and current 2 on the vertical axis. The capacitor can be attached to P-type JFET25, or it can be attached to N-type JFET24 and P-type JFET.
It is also possible to attach it to both 25.

Next, one embodiment of a semiconductor device incorporating the overcurrent protection circuit shown in FIG. 6 will be described with reference to FIG. 7.

P+ type silicon region 34.37 on N type silicon substrate 33
゜39 is formed. An N-type silicon region 35 is formed in the P+ type silicon region 34, a P-type silicon region 36 is formed in the N-type silicon region 35, and a P-type JFET 36 is provided. A diode (corresponding to (26) in FIG. 6) is provided between the P+ type silicon region 34 and the N type silicon region 35.

An N-type silicon region 40 is formed in the P"-type silicon region 39 to provide an N-type JFET 40.
3 and the P+ type silicon region 39 is used as a variable capacitance diode. An N-type silicon region 38 is formed in the P1-type silicon region 37 to form a diode (corresponding to (32) in FIG. 6). N-type silicon region 35 is connected to the drain of P-type JFET 36 through a resistor.
The P+ type silicon region 34 is connected to the drain of the N type JFET 40, and the P+ type silicon region 39 is connected to the N type JFET 40 through a resistor.
The P1 type silicon region 37 is connected to the drain of the JFET 40, and the P1 type silicon region 37 is connected to the P+ type silicon region 39 through a resistor. Each electrode is formed and wired in the same manner as in FIG. If the capacity of the internal capacitor is insufficient, you can also install a capacitor externally by providing a terminal for the capacitor.

Although embodiments using junction type field effect semiconductors have been described here, these junction type field effect semiconductors can also be replaced with depletion type field effect semiconductor devices.

Next, the junction field effect semiconductor of the semiconductor device in FIG.
Depletion shadow edge gate type field effect semiconductor (hereinafter referred to as
An embodiment of the semiconductor device replaced with the DMO 5 will be described with reference to FIG.

P+ type silicon region 42.46 on N type silicon substrate 4I
An N-type silicon region 43 is formed in the P+ type silicon region 42, and a P-type DMO 545 is provided. A P type silicon region 47 is formed in the P+ type silicon region 46, and an N type D
MOS48 is provided. One of the N+ type silicon regions 49 of the N type DMO 548 (7) drain is formed so as to communicate with the outside of the P+ type silicon region 46, and the N type silicon region sandwiched between the two P" type silicon regions 46 has an N type JFET
50. A diode is formed between the P+ type silicon region 42 and the N type silicon region 43, and the capacitance between the N type silicon substrate 41 and the P+ type silicon region 46 is used as a variable capacitance diode. P+ type silicon region 42 is connected to the drain of N type DMO 548, and N type silicon region 43 and P+ type silicon region 46 are connected to the drain of P type DMO 345 through their respective resistors. Each electrode is formed and wired in the same manner as in FIG. 4.

(6) Effects of the Invention The overcurrent protection circuit and semiconductor device (in this (6), both are hereinafter abbreviated as protection circuits) of the present invention consist of a depletion type field effect semiconductor, a capacitor (variable capacitance diode), and a resistor. It consists of Therefore, if a field-effect semiconductor with a small pinch-off voltage is selected to configure the protection circuit, the voltage drop in the protection circuit can be reduced when normal or abnormal current flows, and the circuit current can be reduced to one PN.
Since no junction is crossed, the voltage drop in the protection circuit when normal current is flowing can be reduced to about 0.2V or less.

For this reason, if this protection circuit is connected to the load circuit,
Since the voltage drop in the protection circuit is small, it can be used without substantially reducing the voltage applied to the load of the load circuit. For example, even if it is used in a load circuit with a low power supply voltage of 12V or 5V, the effect of the voltage drop in the protection circuit is very small, so it can be used in any circuit, and it can be used where necessary. Easy to connect and use.

Furthermore, the protection circuit of the present invention switches the connection of the gate of the depletion type field effect semiconductor from the drain side to the source side to cut off or suppress abnormal current. Since it is possible to flow a current many times the saturation current when the gate is connected to the source side, the protection circuit can be made smaller.

In addition, in the protection circuit of the present invention, as shown in the cutoff characteristic diagram, the current continues until close to the maximum value of the abnormal current to be cut off.
Since the normal current increases almost linearly, the normal current can be set close to the maximum value of the abnormal current, so the protection circuit can be made smaller.

In addition, it is possible to create a protection circuit in which the magnitude of the normal current (rated current) and cut-off current during use ranges over a wide range from uA (microampere) to A (ampere).

In the semiconductor device of the present invention, N-type and P-type field effect semiconductors are provided on an N-type silicon substrate.
A type Pfi field effect semiconductor can also be provided.

For AC circuits, two of these protection circuits can be connected in series in opposite directions.

[Brief explanation of drawings]

FIG. 1, FIG. 3, FIG. 4, and FIG. 6 are circuit diagrams showing examples of overcurrent protection circuits using junction field effect semiconductors of the present invention. FIG. 2, FIG. 5, FIG. 7, and FIG. 8 are cross-sectional views illustrating a semiconductor device including an overcurrent protection circuit using a junction field effect semiconductor according to the present invention. Figures 9, 1O, and 11 are
FIG. 7 is a characteristic diagram showing the voltage-current characteristics (blocking characteristics) of the respective overcurrent protection circuits of FIG. FIG. 12 is a characteristic diagram showing general voltage-current characteristics of a depletion type field effect semiconductor. ◎ Overcurrent protection circuit 1.10.16.24- N-type junction field effect semiconductor
2.11゜25-P type junction field effect semiconductor +5.2
6.32-Diode 3.12.29-Capacitor 4.5. ]3.14.27゜30.31-Resistance■ Semiconductor device

Claims (7)

[Claims] (1) Depletion type (both junction type and insulated gate type) field effect semiconductor P-type field effect semiconductor (2) Source and N
The gate of the P-type field-effect semiconductor (2) is connected to the drain of the N-type field-effect semiconductor (1) through a resistor or directly.
The gate of the type field effect semiconductor (1) is connected to the drain of the N type field effect semiconductor (1) through a capacitor and to the drain of the P type field effect semiconductor (2) through a resistor. A depletion type field effect is characterized in that field effect semiconductors act complementary to each other to interrupt overcurrent, and the delay of the interrupting characteristic can be changed by the time constant of the capacitor and resistor. Overcurrent protection circuit using semiconductor. (2) A semiconductor device using a junction field-effect semiconductor that combines the overcurrent protection circuit in (1) above, with an N-type silicon substrate (
A P^+ type silicon region (7) is formed in 6), an N type silicon region is formed in the P^+ type silicon region (7), and an N type silicon region is formed in the P^+ type silicon region (7).
type field effect semiconductor (8) is provided, and an N type silicon substrate (6) is provided.
), a P-type field effect semiconductor (9) is provided, a variable capacitance diode is formed between the N-type silicon substrate (6) and the P^+ type silicon region (7), and a P^-type field effect semiconductor (9) is provided.
The +-type silicon region (7) is connected to the drain of the P-type field-effect semiconductor (9) through a resistor, and a junction-type N-type field-effect semiconductor is formed on one N-type silicon substrate. 1. A semiconductor device comprising a P-type field-effect semiconductor and a P-type field-effect semiconductor, the N-type and P-type field-effect semiconductors acting complementarily to interrupt overcurrent. (3) Connect the source of the N-type field effect semiconductor (10) of the depletion type (both junction type and insulated gate type) field effect semiconductor and the source of the P-type field effect semiconductor (11), and 10) is connected to the drain of the N-type field-effect semiconductor (10) through a capacitor, and to the drain of the P-type field-effect semiconductor (11) through a resistor. Through the resistor, the drain of the P-type field-effect semiconductor (11) is connected, and through the diode, the N-type field-effect semiconductor (11) is connected to the drain of the P-type field-effect semiconductor (11).
connected to the drain of the N-type field effect semiconductor (10).
) and the source of another N-type field-effect semiconductor (16), and connect the gate of another N-type field-effect semiconductor (16) to the drain of the P-type field-effect semiconductor (11) through a resistor. It is characterized by a P-type field effect semiconductor (1
Overcurrent can be reduced by switching the gate connection in 1) from the drain side to the source side, and by the complementary interaction of the N-type field effect semiconductor (10) and the P-type field effect semiconductor (11). An overcurrent protection circuit using a depletion type field effect semiconductor, which is characterized by the ability to shut off. (4) A semiconductor device using a junction field effect semiconductor that combines the overcurrent protection circuit in (3) above, with an N-type silicon substrate (
17), a P^+ type silicon region (18) (21) is formed, an N type silicon region (19) is formed in the P^+ type silicon region (18), and a P type silicon region (19) is formed in the N type silicon region (19). A silicon region is formed and a P-type field effect semiconductor (20) is provided, and an N-type silicon region is formed in the P^+ type silicon region (21) so that one side communicates with the outside of the P^+* type silicon region (21). Then, an N-type field effect semiconductor (22) is provided, and 2
An N-type field effect semiconductor (23) is provided in an N-type silicon region sandwiched between two P^+-type silicon regions (21).
A diode is provided between the N type silicon region (18) and the N type silicon region (19), and the N type silicon substrate (17) and the P
The capacitance between the ^+ type silicon region (21) is a variable capacitance diode, and the N type silicon region (19) and the P^+ type silicon region (21) are connected to the P type field effect semiconductor (20) through their respective resistors. The P^+ type silicon region (18) is connected to the drain of the N type field effect semiconductor (22), and the junction type silicon region (18) is connected to the drain of the N type field effect semiconductor (22). N-type field effect semiconductor and P
and changing the connection of the gate of the P-type field-effect semiconductor from the drain side to the source side;
N-type field effect semiconductor (22) and P-type field effect semiconductor (2
0) act complementary to each other to cut off overcurrent. (5) Connect the source of the N-type field effect semiconductor (24) of the depletion type (both junction type and insulated gate type) field effect semiconductor and the source of the P-type field effect semiconductor (25), and 24) is connected to the drain of the N-type field-effect semiconductor (24) through a capacitor and a resistor, and to the drain of the P-type field-effect semiconductor (25) through a resistor and a diode. is connected to the drain of the P-type field-effect semiconductor (25) through the resistor, and to the drain of the N-type field-effect semiconductor (24) through the diode.
It is characterized by switching the connection of the gate of the N-type field-effect semiconductor and the gate of the P-type field-effect semiconductor from the respective drain side to the source side, and 1. An overcurrent protection circuit using depletion type field effect semiconductors, which is characterized in that two types of field effect semiconductors act complementary to each other to interrupt overcurrent. (6) A semiconductor device using a junction field effect semiconductor that combines the overcurrent protection circuit in (5) above, with an N-type silicon substrate (
33) with P^+ type silicon regions (34) (37) (39
), an N-type silicon region (35) is formed in the P^+ type silicon region (34), and an N-type silicon region (35) is formed in the P^+ type silicon region (34).
A P-type silicon region is formed in the P-type field effect semiconductor (
36), an N-type silicon region is formed in the P^+ type silicon region (39), an N-type field effect semiconductor (40) is provided, and an N-type silicon region ( 38) to form a diode, a diode is formed between the P^+ type silicon region (34) and the N type silicon region (35), and the N type silicon substrate (33) and the P^+ type silicon region (39) The capacitance between is a variable capacitance diode, the N type silicon region (35) is connected to the drain of the P type field effect semiconductor (36) through a resistor, and the P^+ type silicon region (34) is connected to the drain of the P type field effect semiconductor (36). (40), the P^+ type silicon region (39) is connected to the drain of the N-type field effect semiconductor (40) through a resistor, and the P^+ type silicon region (37) is connected to the P^+ type silicon region (37) through a resistor.
It is characterized by being connected to the + type silicon region (39),
An N-type field-effect semiconductor and a P-type field-effect semiconductor are provided on one N-type silicon substrate, and the gates of the N-type field-effect semiconductor and the P-type field-effect semiconductor are connected, respectively. 1. A semiconductor device characterized by switching from the drain side to the source side, and N-type and P-type field effect semiconductors working complementarily to interrupt overcurrent. (7) A semiconductor device using a depletion type insulated gate field effect semiconductor that combines the overcurrent protection circuit in (3) above, in which P^+ type silicon regions (42) (46) are formed on an N type silicon substrate (41). and form a P^+ type silicon region (
An N-type silicon region (43) is formed in 42) to provide a P-type insulated gate field effect semiconductor (45), and a P-type silicon region (47) is formed in the P^+-type silicon region (46) to provide an N-type insulated gate field effect semiconductor (45). type insulated gate type field effect semiconductor (48) is provided;
An N-type junction field effect semiconductor (50) is provided in an N-type silicon region sandwiched between two P^+-type silicon regions (46),
P^+ type silicon region (42) and N type silicon region (4
3), and an N-type silicon substrate (41
) and the P^+ type silicon region (46) is used as a variable capacitance diode, and the P^+ type silicon region (42) is used as the drain (48) of the N type insulated gate field effect semiconductor (48).
49), and connects the N type silicon region (43) and the P^+ type silicon region (46) through their respective resistors.
It is characterized in that it is connected to the drain of a type insulated gate type field effect semiconductor (45), and N type and P type depression type insulated gate type field effect semiconductors and an N type junction type By changing the gate connection of the P-type insulated gate field-effect semiconductor from the drain side to the source side, the N-type and P-type insulated gate field-effect semiconductors act complementary to each other. Accordingly, a semiconductor device is characterized in that it interrupts overcurrent.