WO1994027317A1 - Procede permettant de realiser des composants sur un substrat de silicium sur isolant (soi) - Google Patents

Procede permettant de realiser des composants sur un substrat de silicium sur isolant (soi) Download PDF

Info

Publication number
WO1994027317A1
WO1994027317A1 PCT/DE1994/000484 DE9400484W WO9427317A1 WO 1994027317 A1 WO1994027317 A1 WO 1994027317A1 DE 9400484 W DE9400484 W DE 9400484W WO 9427317 A1 WO9427317 A1 WO 9427317A1
Authority
WO
WIPO (PCT)
Prior art keywords
silicon
layer
substrate
functional elements
soi
Prior art date
Application number
PCT/DE1994/000484
Other languages
German (de)
English (en)
Inventor
Josef Winnerl
Franz Neppl
Original Assignee
Siemens Aktiengesellschaft
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Siemens Aktiengesellschaft filed Critical Siemens Aktiengesellschaft
Publication of WO1994027317A1 publication Critical patent/WO1994027317A1/fr

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76264—SOI together with lateral isolation, e.g. using local oxidation of silicon, or dielectric or polycristalline material refilled trench or air gap isolation regions, e.g. completely isolated semiconductor islands
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76264—SOI together with lateral isolation, e.g. using local oxidation of silicon, or dielectric or polycristalline material refilled trench or air gap isolation regions, e.g. completely isolated semiconductor islands
    • H01L21/76275—Vertical isolation by bonding techniques
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76264—SOI together with lateral isolation, e.g. using local oxidation of silicon, or dielectric or polycristalline material refilled trench or air gap isolation regions, e.g. completely isolated semiconductor islands
    • H01L21/76283—Lateral isolation by refilling of trenches with dielectric material

Definitions

  • the present invention relates to a method for the production of semiconductor components on SOI substrates which, in addition to the SOI functional elements, contain further integrated functional elements in bulk silicon.
  • CMOS transistors on SOI substrates are particularly important with channel lengths below 0.25 ⁇ m and for applications with extremely low supply voltage and power loss.
  • the SOI substrates used have extremely thin silicon layers (approx. 50 nm). These substrates are manufactured using wafer bonding or SI OX. It is difficult to implement functional elements in such thin silicon layers that can dissipate high currents. Examples of such functional elements are structures for protection against electrostatic discharge or power components for smart power applications.
  • a method for the simultaneous implementation of SOI and bulk Si functional elements uses SIMOX technology.
  • an entire silicon wafer is not implanted with 0 + to form the insulation layer, as is usual, but only the areas which are provided as SOI areas are used using a mask. In the remaining areas, the silicon of the substrate remains at full strength, so that the bulk functional elements can be integrated there.
  • the object of the present invention is to provide a simplified production method for the integration of SOI functional elements and Bulk-S functional elements on a silicon substrate. This object is achieved with the method having the features of claim 1. Further configurations result from the dependent claims.
  • FIGS. 1 and 2 each of which shows a cross section through the component to be produced according to different method steps.
  • a conventional SOI substrate is used, which, for. B. can be produced by means of wafer bonding or SIMOX.
  • a photomask is applied to the thin silicon layer of this substrate, leaving the areas that are intended for the bulk Si functional elements free.
  • the thin silicon layer 3 (FIG. 1) and the insulator layer 2 (for example SiO 2) are removed, so that the silicon of the substrate 1 (ie the carrier wafer) of the SOI substrate in the resulting openings 4 is exposed.
  • the known production methods can then be used to manufacture the functional elements in the SOI areas and these exposed areas.
  • This method according to the invention has the advantage over the production method described at the outset that the SOI substrates, as are commercially available, can be used and that the IC manufacturer does not require any costly masked high-energy implantation with 0 + .
  • the SOI functional elements e.g. the CMOS transistors
  • bulk Si functional elements with high current carrying capacity can be implemented in the exposed areas of the substrate 1, in particular if the high current is directed towards the rear of the substrate 1, ie towards the not provided with the insulator layer 2, is removed.
  • protective structures such as. B. diodes, the inputs and outputs of the chip protect against damage from electrostatic discharges.
  • the functional elements trained in the SOI area are insulated from the high currents in the substrate 1 by the insulator layer 2.
  • a further improvement of the method according to the invention is achieved by, in an additional method step, filling the silicon of the substrate 1 in the openings 4 by epitaxial deposition up to the height of the thin silicon layer 3.
  • the thin silicon layer 3 of the SOI regions then forms a planar surface together with this epitaxially deposited silicon 6 (see FIG. 2).
  • This epitaxially deposited silicon 6 can be provided with a suitable doping profile for the production of the functional elements to be integrated. In this way, e.g. B. bipolar transistors in these areas of the substrate.
  • flanks of the thin silicon layer 3 are covered with a dielectric layer 5 (for example SiO 2) become.
  • the thin silicon layer 3 of the SOI regions is then completely electrically insulated from the bulk silicon by dielectric layers.
  • This flank covering with a dielectric layer 5 is obtained, for. B. by first depositing the material of this dielectric layer over the entire surface isotropically onto the surface of the structure in FIG. 1 and then etching it back anisotropically.

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Thin Film Transistor (AREA)

Abstract

L'invention concerne un procédé permettant de réaliser un composant au silicium avec des éléments fonctionnels SOI et des éléments fonctionnels sur silicium. La fine couche de silicium (3) et la couche d'isolant (2) d'un substrat de silicium sur isolant (1) sont enlevées par attaque chimique dans des zones prévues pour les éléments fonctionnels sur silicium. Les éléments fonctionnels sur silicium sont réalisés dans les zones de ces ouvertures (4).
PCT/DE1994/000484 1993-05-06 1994-05-02 Procede permettant de realiser des composants sur un substrat de silicium sur isolant (soi) WO1994027317A1 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
DEP4315063.2 1993-05-06
DE4315063 1993-05-06

Publications (1)

Publication Number Publication Date
WO1994027317A1 true WO1994027317A1 (fr) 1994-11-24

Family

ID=6487375

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/DE1994/000484 WO1994027317A1 (fr) 1993-05-06 1994-05-02 Procede permettant de realiser des composants sur un substrat de silicium sur isolant (soi)

Country Status (1)

Country Link
WO (1) WO1994027317A1 (fr)

Cited By (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0661735B1 (fr) * 1993-12-29 2001-03-07 Consorzio per la Ricerca sulla Microelettronica nel Mezzogiorno Procédé pour fabriquer des circuits intégrés, en particulier des dispositifs semi-conducteurs intelligents de puissance
WO2004114400A1 (fr) * 2003-06-17 2004-12-29 International Business Machines Corporation Dispositif cmos soi haute performance forme sur des substrats cristallins hybrides
KR100488379B1 (ko) * 2001-09-26 2005-05-11 가부시끼가이샤 도시바 반도체 장치용 기판을 제조하는 방법 및 반도체 장치용 기판
US6991998B2 (en) 2004-07-02 2006-01-31 International Business Machines Corporation Ultra-thin, high quality strained silicon-on-insulator formed by elastic strain transfer
US7037794B2 (en) 2004-06-09 2006-05-02 International Business Machines Corporation Raised STI process for multiple gate ox and sidewall protection on strained Si/SGOI structure with elevated source/drain
US7217949B2 (en) 2004-07-01 2007-05-15 International Business Machines Corporation Strained Si MOSFET on tensile-strained SiGe-on-insulator (SGOI)
US7220626B2 (en) 2005-01-28 2007-05-22 International Business Machines Corporation Structure and method for manufacturing planar strained Si/SiGe substrate with multiple orientations and different stress levels
US7274084B2 (en) 2005-01-12 2007-09-25 International Business Machines Corporation Enhanced PFET using shear stress
US7432553B2 (en) 2005-01-19 2008-10-07 International Business Machines Corporation Structure and method to optimize strain in CMOSFETs
US7479688B2 (en) 2003-05-30 2009-01-20 International Business Machines Corporation STI stress modification by nitrogen plasma treatment for improving performance in small width devices
US7550364B2 (en) 2005-09-29 2009-06-23 International Business Machines Corporation Stress engineering using dual pad nitride with selective SOI device architecture
US7564081B2 (en) 2005-11-30 2009-07-21 International Business Machines Corporation finFET structure with multiply stressed gate electrode
US7655511B2 (en) 2005-11-03 2010-02-02 International Business Machines Corporation Gate electrode stress control for finFET performance enhancement
US7863197B2 (en) 2006-01-09 2011-01-04 International Business Machines Corporation Method of forming a cross-section hourglass shaped channel region for charge carrier mobility modification
EP3996132A1 (fr) * 2020-11-10 2022-05-11 Commissariat à l'énergie atomique et aux énergies alternatives Procédé de formation d'une structure de piégeage d'un substrat utile

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4393574A (en) * 1980-12-05 1983-07-19 Kabushiki Kaisha Daini Seikosha Method for fabricating integrated circuits
WO1987006060A1 (fr) * 1986-03-28 1987-10-08 Fairchild Semiconductor Corporation Procede permettant d'unir deux ou plusieurs tranches de semi-conducteurs et structure resultante
EP0405183A2 (fr) * 1989-06-06 1991-01-02 National Semiconductor Corporation Isolation diélectrique pour procédé IC de haute puissance à haute tension
JPH03283636A (ja) * 1990-03-30 1991-12-13 Nippon Soken Inc 半導体基板の製造方法

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4393574A (en) * 1980-12-05 1983-07-19 Kabushiki Kaisha Daini Seikosha Method for fabricating integrated circuits
WO1987006060A1 (fr) * 1986-03-28 1987-10-08 Fairchild Semiconductor Corporation Procede permettant d'unir deux ou plusieurs tranches de semi-conducteurs et structure resultante
EP0405183A2 (fr) * 1989-06-06 1991-01-02 National Semiconductor Corporation Isolation diélectrique pour procédé IC de haute puissance à haute tension
JPH03283636A (ja) * 1990-03-30 1991-12-13 Nippon Soken Inc 半導体基板の製造方法

Non-Patent Citations (2)

* Cited by examiner, † Cited by third party
Title
B. EL-KAREH ET AL.: "BIPOLAR ONE-DEVOICE RANDOM-ACCES MEMORY CELL.", IBM TECHNICAL DISCLOSURE BULLETIN., vol. 25, no. 11A, April 1983 (1983-04-01), NEW YORK US, pages 5672 - 5673 *
PATENT ABSTRACTS OF JAPAN vol. 16, no. 108 (E - 1179) 17 March 1992 (1992-03-17) *

Cited By (21)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0661735B1 (fr) * 1993-12-29 2001-03-07 Consorzio per la Ricerca sulla Microelettronica nel Mezzogiorno Procédé pour fabriquer des circuits intégrés, en particulier des dispositifs semi-conducteurs intelligents de puissance
KR100488379B1 (ko) * 2001-09-26 2005-05-11 가부시끼가이샤 도시바 반도체 장치용 기판을 제조하는 방법 및 반도체 장치용 기판
US7479688B2 (en) 2003-05-30 2009-01-20 International Business Machines Corporation STI stress modification by nitrogen plasma treatment for improving performance in small width devices
US7329923B2 (en) 2003-06-17 2008-02-12 International Business Machines Corporation High-performance CMOS devices on hybrid crystal oriented substrates
WO2004114400A1 (fr) * 2003-06-17 2004-12-29 International Business Machines Corporation Dispositif cmos soi haute performance forme sur des substrats cristallins hybrides
KR100843489B1 (ko) * 2003-06-17 2008-07-04 인터내셔널 비지네스 머신즈 코포레이션 하이브리드 결정-방향 기판상의 고성능 ｃｍｏｓ ｓｏｉ디바이스
US7713807B2 (en) 2003-06-17 2010-05-11 International Business Machines Corporation High-performance CMOS SOI devices on hybrid crystal-oriented substrates
US7737502B2 (en) 2004-06-09 2010-06-15 International Business Machines Corporation Raised STI process for multiple gate ox and sidewall protection on strained Si/SGOI sructure with elevated source/drain
US7037794B2 (en) 2004-06-09 2006-05-02 International Business Machines Corporation Raised STI process for multiple gate ox and sidewall protection on strained Si/SGOI structure with elevated source/drain
US7217949B2 (en) 2004-07-01 2007-05-15 International Business Machines Corporation Strained Si MOSFET on tensile-strained SiGe-on-insulator (SGOI)
US7442993B2 (en) 2004-07-02 2008-10-28 International Business Machines Corporation Ultra-thin, high quality strained silicon-on-insulator formed by elastic strain transfer
US6991998B2 (en) 2004-07-02 2006-01-31 International Business Machines Corporation Ultra-thin, high quality strained silicon-on-insulator formed by elastic strain transfer
US7274084B2 (en) 2005-01-12 2007-09-25 International Business Machines Corporation Enhanced PFET using shear stress
US7432553B2 (en) 2005-01-19 2008-10-07 International Business Machines Corporation Structure and method to optimize strain in CMOSFETs
US7220626B2 (en) 2005-01-28 2007-05-22 International Business Machines Corporation Structure and method for manufacturing planar strained Si/SiGe substrate with multiple orientations and different stress levels
US7550364B2 (en) 2005-09-29 2009-06-23 International Business Machines Corporation Stress engineering using dual pad nitride with selective SOI device architecture
US7655511B2 (en) 2005-11-03 2010-02-02 International Business Machines Corporation Gate electrode stress control for finFET performance enhancement
US7564081B2 (en) 2005-11-30 2009-07-21 International Business Machines Corporation finFET structure with multiply stressed gate electrode
US7863197B2 (en) 2006-01-09 2011-01-04 International Business Machines Corporation Method of forming a cross-section hourglass shaped channel region for charge carrier mobility modification
EP3996132A1 (fr) * 2020-11-10 2022-05-11 Commissariat à l'énergie atomique et aux énergies alternatives Procédé de formation d'une structure de piégeage d'un substrat utile
FR3116151A1 (fr) * 2020-11-10 2022-05-13 Commissariat A L'energie Atomique Et Aux Energies Alternatives Procede de formation d’une structure de piegeage d’un substrat utile

Similar Documents

Publication Publication Date Title
DE3145231C3 (de) Halbleiterbauelement
WO1994027317A1 (fr) Procede permettant de realiser des composants sur un substrat de silicium sur isolant (soi)
DE102006045214B4 (de) Halbleitervorrichtung mit einem LDMOS-Transistor und Verfahren zur Herstellung derselben
DE2832388C2 (de) Verfahren zum Herstellen von MNOS- und MOS-Transistoren in Silizium-Gate-Technologie auf einem Halbleitersubstrat
DE112014003481B4 (de) GaN-TRANSISTOREN MIT POLYSILIZIUMSCHICHTEN ZUR BILDUNG VON ZUSÄTZLICHEN KOMPONENTEN UND VERFAHREN ZU DEREN HERSTELLUNG
EP0010596B1 (fr) Méthode de formation d'ouvertures dans des masques pour la production de circuits semiconducteurs
DE4235534C2 (de) Verfahren zum Isolieren von Feldeffekttransistoren
DE10138951A1 (de) SOI-MOSFET und Herstellungsverfahren hierfür
DE2923995A1 (de) Verfahren zum herstellen von integrierten mos-schaltungen mit und ohne mnos-speichertransistoren in silizium-gate-technologie
DE3105118A1 (de) Verfahren zur herstellung einer integrierten schaltung mit komplementaeren bipolaren transistoren und komplementaeren isolierschicht-gate-feldeffekttransistoren auf einem gemeinsamen substrat
DE102013211374A1 (de) Transistor und Verfahren zur Herstellung eines Transistors
DE10338480B4 (de) Halbleitervorrichtung mit dielektrischer Trennung und Verfahren zur Herstellung derselben
DE1589705A1 (de) Mehrere elektrische Funktionsstufen enthaltende integrierte Schaltung
DE10234601A1 (de) Halbleiterbauelement mit SOI-Substrat und Herstellungsverfahren hierfür
DE102014200429A1 (de) Trench-MOSFET-Transistorvorrichtung, Substrat für Trench-MOSFET-Transistorvorrichtung und entsprechendes Herstellungsverfahren
DE2140108A1 (de) Halbleiteranordnung und Verfahren zur Herstellung derselben
DE10124038A1 (de) Verfahren zur Herstellung vergrabener Bereiche
EP0095658A2 (fr) Dispositif semi-conducteur planaire et son procédé de fabrication
DE2902665A1 (de) Verfahren zum herstellen von integrierten mos-schaltungen in silizium-gate- technologie
EP1139432A2 (fr) Diode Schottky
DE10250204B4 (de) Verfahren zur Herstellung von Kollektorbereichen einer Transistorstruktur
DE3331631A1 (de) Halbleiter-bauelement
DE4006158C2 (fr)
DE102021123323A1 (de) Schemata zur Integration von Vorrichtungen unter Einsatz eines Bulk-Halbleitersubstrats mit einer <111>-Kristallorientierung
DE2800240A1 (de) Integrierte halbleiterschaltung

Legal Events

Date Code Title Description
AK Designated states

Kind code of ref document: A1

Designated state(s): JP KR US

AL Designated countries for regional patents

Kind code of ref document: A1

Designated state(s): AT BE CH DE DK ES FR GB GR IE IT LU MC NL PT SE

DFPE Request for preliminary examination filed prior to expiration of 19th month from priority date (pct application filed before 20040101)
121 Ep: the epo has been informed by wipo that ep was designated in this application
122 Ep: pct application non-entry in european phase