WO1994027317A1 - Process for producing components on an soi substrate - Google Patents

Process for producing components on an soi substrate Download PDF

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Publication number
WO1994027317A1
WO1994027317A1 PCT/DE1994/000484 DE9400484W WO9427317A1 WO 1994027317 A1 WO1994027317 A1 WO 1994027317A1 DE 9400484 W DE9400484 W DE 9400484W WO 9427317 A1 WO9427317 A1 WO 9427317A1
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WO
WIPO (PCT)
Prior art keywords
silicon
layer
substrate
functional elements
soi
Prior art date
Application number
PCT/DE1994/000484
Other languages
German (de)
French (fr)
Inventor
Josef Winnerl
Franz Neppl
Original Assignee
Siemens Aktiengesellschaft
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Siemens Aktiengesellschaft filed Critical Siemens Aktiengesellschaft
Publication of WO1994027317A1 publication Critical patent/WO1994027317A1/en

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76264—SOI together with lateral isolation, e.g. using local oxidation of silicon, or dielectric or polycristalline material refilled trench or air gap isolation regions, e.g. completely isolated semiconductor islands
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76264—SOI together with lateral isolation, e.g. using local oxidation of silicon, or dielectric or polycristalline material refilled trench or air gap isolation regions, e.g. completely isolated semiconductor islands
    • H01L21/76275—Vertical isolation by bonding techniques
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76264—SOI together with lateral isolation, e.g. using local oxidation of silicon, or dielectric or polycristalline material refilled trench or air gap isolation regions, e.g. completely isolated semiconductor islands
    • H01L21/76283—Lateral isolation by refilling of trenches with dielectric material

Definitions

  • the present invention relates to a method for the production of semiconductor components on SOI substrates which, in addition to the SOI functional elements, contain further integrated functional elements in bulk silicon.
  • CMOS transistors on SOI substrates are particularly important with channel lengths below 0.25 ⁇ m and for applications with extremely low supply voltage and power loss.
  • the SOI substrates used have extremely thin silicon layers (approx. 50 nm). These substrates are manufactured using wafer bonding or SI OX. It is difficult to implement functional elements in such thin silicon layers that can dissipate high currents. Examples of such functional elements are structures for protection against electrostatic discharge or power components for smart power applications.
  • a method for the simultaneous implementation of SOI and bulk Si functional elements uses SIMOX technology.
  • an entire silicon wafer is not implanted with 0 + to form the insulation layer, as is usual, but only the areas which are provided as SOI areas are used using a mask. In the remaining areas, the silicon of the substrate remains at full strength, so that the bulk functional elements can be integrated there.
  • the object of the present invention is to provide a simplified production method for the integration of SOI functional elements and Bulk-S functional elements on a silicon substrate. This object is achieved with the method having the features of claim 1. Further configurations result from the dependent claims.
  • FIGS. 1 and 2 each of which shows a cross section through the component to be produced according to different method steps.
  • a conventional SOI substrate is used, which, for. B. can be produced by means of wafer bonding or SIMOX.
  • a photomask is applied to the thin silicon layer of this substrate, leaving the areas that are intended for the bulk Si functional elements free.
  • the thin silicon layer 3 (FIG. 1) and the insulator layer 2 (for example SiO 2) are removed, so that the silicon of the substrate 1 (ie the carrier wafer) of the SOI substrate in the resulting openings 4 is exposed.
  • the known production methods can then be used to manufacture the functional elements in the SOI areas and these exposed areas.
  • This method according to the invention has the advantage over the production method described at the outset that the SOI substrates, as are commercially available, can be used and that the IC manufacturer does not require any costly masked high-energy implantation with 0 + .
  • the SOI functional elements e.g. the CMOS transistors
  • bulk Si functional elements with high current carrying capacity can be implemented in the exposed areas of the substrate 1, in particular if the high current is directed towards the rear of the substrate 1, ie towards the not provided with the insulator layer 2, is removed.
  • protective structures such as. B. diodes, the inputs and outputs of the chip protect against damage from electrostatic discharges.
  • the functional elements trained in the SOI area are insulated from the high currents in the substrate 1 by the insulator layer 2.
  • a further improvement of the method according to the invention is achieved by, in an additional method step, filling the silicon of the substrate 1 in the openings 4 by epitaxial deposition up to the height of the thin silicon layer 3.
  • the thin silicon layer 3 of the SOI regions then forms a planar surface together with this epitaxially deposited silicon 6 (see FIG. 2).
  • This epitaxially deposited silicon 6 can be provided with a suitable doping profile for the production of the functional elements to be integrated. In this way, e.g. B. bipolar transistors in these areas of the substrate.
  • flanks of the thin silicon layer 3 are covered with a dielectric layer 5 (for example SiO 2) become.
  • the thin silicon layer 3 of the SOI regions is then completely electrically insulated from the bulk silicon by dielectric layers.
  • This flank covering with a dielectric layer 5 is obtained, for. B. by first depositing the material of this dielectric layer over the entire surface isotropically onto the surface of the structure in FIG. 1 and then etching it back anisotropically.

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Thin Film Transistor (AREA)

Abstract

A process for producing a silicon component with SOI and bulk functional units in which the thin silicon layer (3) and the insulation layer (2) of an SOI substrate (1) are etched away in the regions intended for the bulk functional elements and the bulk functional elements are produced in the regions of these apertures.

Description

Herstellungsverfahren für Bauelemente auf SOI-SubstratManufacturing process for components on SOI substrate
Die vorliegende Erfindung betrifft ein Verfahren zur Herstel¬ lung von Halbleiterbauelementen auf SOI-Substraten, die zu¬ sätzlich zu den SOI-Funktionselementen weitere integrierte Funktionselemente in Bulk-Silizi m enthalten.The present invention relates to a method for the production of semiconductor components on SOI substrates which, in addition to the SOI functional elements, contain further integrated functional elements in bulk silicon.
CMOS-Transistoren auf SOI-Substrat, insbesondere solche mit vollständig verarmtem Kanalbereich, sind insbesondere bei Ka¬ nallängen unter 0,25 um und für Anwendungen mit extrem nied¬ riger Versorgungsspannung und Verlustleistung von Bedeutung. Die verwendeten SOI-Substrate besitzen extrem dünne Silizium¬ schichten (ca. 50 nm) . Diese Substrate werden mittels wafer bonding oder SI OX hergestellt. Es ist schwierig, in derart dünnen Siliziumschichten Funktionselemente zu realisieren, die hohe Ströme abführen können. Beispiele für solche Funkti- onselemente sind Strukturen zum Schutz gegen elektrostatische Entladungen oder Leistungsbauelemente für Smart-Power-Anwen- dungen. Ein Verfahren zur gleichzeitigen Realisierung von SOI- und Bulk-Si-Funktionselementen bedient sich der SIMOX- Technik. Dabei wird nicht wie üblich eine ganze Silizium- scheibe zur Ausbildung der Isolationsschicht mit 0+ implan¬ tiert, sondern unter Verwendung einer Maske nur die Bereiche, die als SOI-Bereiche vorgesehen sind. In den übrigen Berei¬ chen bleibt das Silizium des Substrates in voller Stärke ste¬ hen, so daß dort die Bulk-Funktionselemente integriert werden können.CMOS transistors on SOI substrates, in particular those with a completely depleted channel region, are particularly important with channel lengths below 0.25 μm and for applications with extremely low supply voltage and power loss. The SOI substrates used have extremely thin silicon layers (approx. 50 nm). These substrates are manufactured using wafer bonding or SI OX. It is difficult to implement functional elements in such thin silicon layers that can dissipate high currents. Examples of such functional elements are structures for protection against electrostatic discharge or power components for smart power applications. A method for the simultaneous implementation of SOI and bulk Si functional elements uses SIMOX technology. In this case, an entire silicon wafer is not implanted with 0 + to form the insulation layer, as is usual, but only the areas which are provided as SOI areas are used using a mask. In the remaining areas, the silicon of the substrate remains at full strength, so that the bulk functional elements can be integrated there.
Aufgabe der vorliegenden Erfindung ist es, ein vereinfachtes Herstellungsverfahren für die Integration von SOI-Funktions¬ elementen und Bulk-S -Funktionselementen auf einem Silizium- εubstrat anzugeben. Diese Aufgabe wird mit dem Verfahren mit den Merkmalen des Anspruches 1 gelöst. Weitere Ausgestaltungen ergeben sich aus den abhängigen Ansprüchen.The object of the present invention is to provide a simplified production method for the integration of SOI functional elements and Bulk-S functional elements on a silicon substrate. This object is achieved with the method having the features of claim 1. Further configurations result from the dependent claims.
Es folgt eine Beschreibung des erfindungsgemäßen Verfahrens anhand der Figuren 1 und 2, die jeweils einen Querschnitt durch das herzustellende Bauelement nach verschiedenen Ver¬ fahrensschritten zeigen.There follows a description of the method according to the invention with reference to FIGS. 1 and 2, each of which shows a cross section through the component to be produced according to different method steps.
Bei dem erfindungεgemäßen Verfahren wird von einem üblichen SOI-Substrat ausgegangen, das z. B. mittels wafer bonding oder SIMOX hergestellt sein kann. Es wird eine Fotomaske auf der dünnen Siliziumschicht dieses Substrates aufgebracht, die diejenigen Bereiche, die für die Bulk-Si-Funktionselemente vorgesehen sind, frei läßt. In den Öffnungen dieser Fotomaske werden die dünne Siliziumschicht 3 (ε. Fig. 1) und die Isola¬ torschicht 2 (z. B. Siθ2) entfernt, so daß das Silizium des Substrates 1 (d. h. der Trägerscheibe) des SOI-Substrates in den entstehenden Öffnungen 4 freigelegt ist. Es können dann mit den bekannten Herstellungsverfahren die Funktionselemente in den SOI-Bereichen und diesen freigelegten Bereichen herge¬ stellt werden. Dieses erfindungsgemäße Verfahren hat gegen¬ über der eingangs beschriebenen Herstellungsmethode den Vor¬ teil, daß die SOI-Substrate, wie sie handelsüblich geliefert werden, verwendet werden können und beim IC-Hersteller keine kostenintensive maskierte Hochenergieimplantation mit 0+ erforderlich ist. Zu den SOI-Funktionselementen (z. B. den CMOS-Transistoren) können in den freigelegten Bereichen des Substrates 1 Bulk-Si-Funktionselemente mit hoher Strombelastbarkeit realisiert werden, insbesondere, wenn der hohe Strom zur Rückseite des Substrates 1 hin, d. h. zu der nicht mit der Isolatorschicht 2 versehenen Oberseite, abgeführt wird. Typische Beispiele dafür sind Schutzstrukturen, wie z. B. Dioden, die Ein- und Ausgänge des Chips vor Schäden durch elektrostatische Entladungen schüt¬ zen. Die in dem SOI-Bereich ausgebildeten Funktionselemente sind gegenüber den hohen Strömen im Substrat 1 durch die Iso- latorschicht 2 isoliert.In the method according to the invention, a conventional SOI substrate is used, which, for. B. can be produced by means of wafer bonding or SIMOX. A photomask is applied to the thin silicon layer of this substrate, leaving the areas that are intended for the bulk Si functional elements free. In the openings of this photomask, the thin silicon layer 3 (FIG. 1) and the insulator layer 2 (for example SiO 2) are removed, so that the silicon of the substrate 1 (ie the carrier wafer) of the SOI substrate in the resulting openings 4 is exposed. The known production methods can then be used to manufacture the functional elements in the SOI areas and these exposed areas. This method according to the invention has the advantage over the production method described at the outset that the SOI substrates, as are commercially available, can be used and that the IC manufacturer does not require any costly masked high-energy implantation with 0 + . For the SOI functional elements (e.g. the CMOS transistors), bulk Si functional elements with high current carrying capacity can be implemented in the exposed areas of the substrate 1, in particular if the high current is directed towards the rear of the substrate 1, ie towards the not provided with the insulator layer 2, is removed. Typical examples of this are protective structures, such as. B. diodes, the inputs and outputs of the chip protect against damage from electrostatic discharges. The functional elements trained in the SOI area are insulated from the high currents in the substrate 1 by the insulator layer 2.
Eine weitere Verbesserung des erfindungsgemäßen Verfahrens erreicht man, indem man in einem zusätzlichen Verfahrens¬ schritt das Silizium des Substrates 1 in den Öffnungen 4 durch epitaktisches Abscheiden bis zur Höhe der dünnen Sili¬ ziumschicht 3 hin auffüllt. Die dünne Siliziumschicht 3 der SOI-Bereiche bildet dann zusammen mit diesem epitaktisch ab- geschiedenen Silizium 6 (s. Fig. 2) eine planare Oberfläche. Dieses epitaktiεch abgeschiedene Silizium 6 kann für die Her¬ stellung der zu integrierenden Funktionselemente mit einem geeigneten Dotierungsprofil versehen werden. Auf diese Weise können z. B. Bipolartransistoren in diesen Bereichen des Substrates hergestellt werden. Um die Bulk-Si-Funktionsele¬ mente von den SOI-Funktionselementen vollständig elektrisch zu isolieren, ist es vorteilhaft, wenn vor dem epitaktischen Aufwachsen des weiteren Siliziums 6 die Flanken der dünnen Siliziumschicht 3 mit einer Dielektrikumschicht 5 (z. B. Siθ2) bedeckt werden. Die dünne Siliziumschicht 3 der SOI-Be¬ reiche ist dann zu dem Bulk-Silizium vollständig durch die¬ lektrische Schichten elektrisch isoliert. Diese Flankenbe¬ deckung mit einer Dielektrikumschicht 5 erhält man z. B., in¬ dem zunächst das Material dieser Dielektrikumschicht ganzflä- chig isotrop auf die Oberfläche der Struktur der Figur 1 ab¬ geschieden und dann anisotrop rückgeätzt wird. A further improvement of the method according to the invention is achieved by, in an additional method step, filling the silicon of the substrate 1 in the openings 4 by epitaxial deposition up to the height of the thin silicon layer 3. The thin silicon layer 3 of the SOI regions then forms a planar surface together with this epitaxially deposited silicon 6 (see FIG. 2). This epitaxially deposited silicon 6 can be provided with a suitable doping profile for the production of the functional elements to be integrated. In this way, e.g. B. bipolar transistors in these areas of the substrate. In order to completely electrically isolate the bulk Si functional elements from the SOI functional elements, it is advantageous if, before the further silicon 6 is grown epitaxially, the flanks of the thin silicon layer 3 are covered with a dielectric layer 5 (for example SiO 2) become. The thin silicon layer 3 of the SOI regions is then completely electrically insulated from the bulk silicon by dielectric layers. This flank covering with a dielectric layer 5 is obtained, for. B. by first depositing the material of this dielectric layer over the entire surface isotropically onto the surface of the structure in FIG. 1 and then etching it back anisotropically.

Claims

Patentansprüche: Claims:
1. Verfahren zur Herstellung eines Halbleiterbauelementes auf Silizium mit einem Subεtrat (1) auε Silizium und einer an ei- ner Oberεeite dieεeε Substrates (1) unter einer dünnen Sili¬ ziumschicht (3) vergrabenen und nur in Bereichen vorhandenen Isolatorschicht (2), bei dem unter Verwendung einer Fotomaske das Silizium der oberen dünnen Siliziumεchicht (3) eineε SOI-Subεtrateε und die darunterliegende Iεolatorschicht (2) außerhalb dieser Be¬ reiche entfernt werden.1. A method for producing a semiconductor component on silicon with a substrate (1) made of silicon and a substrate (1) buried on an upper side of this substrate under a thin silicon layer (3) and insulator layer (2) present only in regions which, using a photomask, removes the silicon of the upper thin silicon layer (3), an SOI substrate, and the underlying isolator layer (2) outside of these areas.
2. Verfahren nach Anspruch 1, bei dem zusätzlich die entfernten Anteile der Isolatorschicht (2) und der dünnen Siliziumschicht (3) durch epitaktisch ab¬ geschiedenes Silizium (6) ersetzt werden.2. The method according to claim 1, in which the removed portions of the insulator layer (2) and the thin silicon layer (3) are replaced by epitaxially deposited silicon (6).
3. Verfahren nach Anspruch 2, bei dem vor diesem zusätzlichen Verfahrensschritt die Flanken der dünnen Siliziumschicht (3) mit einer Dielektrikumschicht (5) isoliert werden.3. The method according to claim 2, in which the flanks of the thin silicon layer (3) are insulated with a dielectric layer (5) before this additional method step.
4. Verfahren nach Anspruch 2 oder 3, bei dem das epitaktisch abgeschiedene Silizium (6) zur Her- Stellung von Funktionselementen mit einer Dotierung versehen wird. 4. The method according to claim 2 or 3, wherein the epitaxially deposited silicon (6) is provided with a doping for the production of functional elements.
PCT/DE1994/000484 1993-05-06 1994-05-02 Process for producing components on an soi substrate WO1994027317A1 (en)

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DE4315063 1993-05-06
DEP4315063.2 1993-05-06

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Cited By (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0661735B1 (en) * 1993-12-29 2001-03-07 Consorzio per la Ricerca sulla Microelettronica nel Mezzogiorno Process for the manufacturing of integrated circuits, particularly of intelligent power semiconductor devices
WO2004114400A1 (en) * 2003-06-17 2004-12-29 International Business Machines Corporation High-performance cmos soi device on hybrid crystal-oriented substrates
KR100488379B1 (en) * 2001-09-26 2005-05-11 가부시끼가이샤 도시바 Substrate for semiconductor device and method of fabricating the same
US6991998B2 (en) 2004-07-02 2006-01-31 International Business Machines Corporation Ultra-thin, high quality strained silicon-on-insulator formed by elastic strain transfer
US7037794B2 (en) 2004-06-09 2006-05-02 International Business Machines Corporation Raised STI process for multiple gate ox and sidewall protection on strained Si/SGOI structure with elevated source/drain
US7217949B2 (en) 2004-07-01 2007-05-15 International Business Machines Corporation Strained Si MOSFET on tensile-strained SiGe-on-insulator (SGOI)
US7220626B2 (en) 2005-01-28 2007-05-22 International Business Machines Corporation Structure and method for manufacturing planar strained Si/SiGe substrate with multiple orientations and different stress levels
US7274084B2 (en) 2005-01-12 2007-09-25 International Business Machines Corporation Enhanced PFET using shear stress
US7432553B2 (en) 2005-01-19 2008-10-07 International Business Machines Corporation Structure and method to optimize strain in CMOSFETs
US7479688B2 (en) 2003-05-30 2009-01-20 International Business Machines Corporation STI stress modification by nitrogen plasma treatment for improving performance in small width devices
US7550364B2 (en) 2005-09-29 2009-06-23 International Business Machines Corporation Stress engineering using dual pad nitride with selective SOI device architecture
US7564081B2 (en) 2005-11-30 2009-07-21 International Business Machines Corporation finFET structure with multiply stressed gate electrode
US7655511B2 (en) 2005-11-03 2010-02-02 International Business Machines Corporation Gate electrode stress control for finFET performance enhancement
US7863197B2 (en) 2006-01-09 2011-01-04 International Business Machines Corporation Method of forming a cross-section hourglass shaped channel region for charge carrier mobility modification
EP3996132A1 (en) * 2020-11-10 2022-05-11 Commissariat à l'énergie atomique et aux énergies alternatives Process for manufacturing a substratewith a charge trapping structure

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Cited By (21)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0661735B1 (en) * 1993-12-29 2001-03-07 Consorzio per la Ricerca sulla Microelettronica nel Mezzogiorno Process for the manufacturing of integrated circuits, particularly of intelligent power semiconductor devices
KR100488379B1 (en) * 2001-09-26 2005-05-11 가부시끼가이샤 도시바 Substrate for semiconductor device and method of fabricating the same
US7479688B2 (en) 2003-05-30 2009-01-20 International Business Machines Corporation STI stress modification by nitrogen plasma treatment for improving performance in small width devices
US7329923B2 (en) 2003-06-17 2008-02-12 International Business Machines Corporation High-performance CMOS devices on hybrid crystal oriented substrates
WO2004114400A1 (en) * 2003-06-17 2004-12-29 International Business Machines Corporation High-performance cmos soi device on hybrid crystal-oriented substrates
KR100843489B1 (en) * 2003-06-17 2008-07-04 인터내셔널 비지네스 머신즈 코포레이션 High-Performance CMOS SOI Device On Hybrid Crystal-Oriented Substrates
US7713807B2 (en) 2003-06-17 2010-05-11 International Business Machines Corporation High-performance CMOS SOI devices on hybrid crystal-oriented substrates
US7737502B2 (en) 2004-06-09 2010-06-15 International Business Machines Corporation Raised STI process for multiple gate ox and sidewall protection on strained Si/SGOI sructure with elevated source/drain
US7037794B2 (en) 2004-06-09 2006-05-02 International Business Machines Corporation Raised STI process for multiple gate ox and sidewall protection on strained Si/SGOI structure with elevated source/drain
US7217949B2 (en) 2004-07-01 2007-05-15 International Business Machines Corporation Strained Si MOSFET on tensile-strained SiGe-on-insulator (SGOI)
US7442993B2 (en) 2004-07-02 2008-10-28 International Business Machines Corporation Ultra-thin, high quality strained silicon-on-insulator formed by elastic strain transfer
US6991998B2 (en) 2004-07-02 2006-01-31 International Business Machines Corporation Ultra-thin, high quality strained silicon-on-insulator formed by elastic strain transfer
US7274084B2 (en) 2005-01-12 2007-09-25 International Business Machines Corporation Enhanced PFET using shear stress
US7432553B2 (en) 2005-01-19 2008-10-07 International Business Machines Corporation Structure and method to optimize strain in CMOSFETs
US7220626B2 (en) 2005-01-28 2007-05-22 International Business Machines Corporation Structure and method for manufacturing planar strained Si/SiGe substrate with multiple orientations and different stress levels
US7550364B2 (en) 2005-09-29 2009-06-23 International Business Machines Corporation Stress engineering using dual pad nitride with selective SOI device architecture
US7655511B2 (en) 2005-11-03 2010-02-02 International Business Machines Corporation Gate electrode stress control for finFET performance enhancement
US7564081B2 (en) 2005-11-30 2009-07-21 International Business Machines Corporation finFET structure with multiply stressed gate electrode
US7863197B2 (en) 2006-01-09 2011-01-04 International Business Machines Corporation Method of forming a cross-section hourglass shaped channel region for charge carrier mobility modification
EP3996132A1 (en) * 2020-11-10 2022-05-11 Commissariat à l'énergie atomique et aux énergies alternatives Process for manufacturing a substratewith a charge trapping structure
FR3116151A1 (en) * 2020-11-10 2022-05-13 Commissariat A L'energie Atomique Et Aux Energies Alternatives METHOD FOR FORMING A USEFUL SUBSTRATE TRAPPING STRUCTURE

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