WO1991020129A1 - Circuit pour la limitation de la vitesse de montee des signaux de sortie de circuits integres - Google Patents

Circuit pour la limitation de la vitesse de montee des signaux de sortie de circuits integres Download PDF

Info

Publication number
WO1991020129A1
WO1991020129A1 PCT/DE1991/000374 DE9100374W WO9120129A1 WO 1991020129 A1 WO1991020129 A1 WO 1991020129A1 DE 9100374 W DE9100374 W DE 9100374W WO 9120129 A1 WO9120129 A1 WO 9120129A1
Authority
WO
WIPO (PCT)
Prior art keywords
circuit
output
signal
differential amplifier
rate
Prior art date
Application number
PCT/DE1991/000374
Other languages
German (de)
English (en)
Inventor
Oliver Fischer
Hans-Peter Klose
Original Assignee
Robert Bosch Gmbh
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Robert Bosch Gmbh filed Critical Robert Bosch Gmbh
Publication of WO1991020129A1 publication Critical patent/WO1991020129A1/fr

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/003—Modifications for increasing the reliability for protection
    • H03K19/00346—Modifications for eliminating interference or parasitic voltages or currents
    • H03K19/00361—Modifications for eliminating interference or parasitic voltages or currents in field effect transistor circuits

Definitions

  • the invention relates to a circuit for limiting the rate of signal rise of output signals of integrated circuits.
  • Output transistors from integrated circuits are usually designed so that a required, maximum, capacitive load and a required, assigned signal rise time can be used. This means that with a smaller, capacitive load, very steep-edged output signals are generated, that is to say that the signal rise speed is dependent on the capacitive load.
  • One measure for reducing the interference radiation emitted by a device is to limit the rate of increase of signals, in particular digital signals. len, which connect different integrated circuits of a control unit. This measure, known per se, considerably reduces the high-frequency voltage component contained in the output signals.
  • external driver modules which are arranged directly at the output of the integrated circuit and limit the rate of signal rise.
  • driver strength in the circuit by software-controlled parallel connection of driver transistors.
  • the load dependency for the respective driver strength is also retained here.
  • a reference signal is generated and the output signal is correspondingly tracked, and the signal rise rate of the output signal is determined by a differentiating element and a correction signal for tracking the output signal is derived therefrom.
  • the circuit is able to output signals with defi generate slew rate.
  • Circuit can be integrated on an integrated circuit with components of digital signal processing.
  • the load dependency of the signal rate of rise of the output signals is eliminated for a large, capacitive load range without having to use special software or external hardware.
  • the IC output voltage follows an internally generated reference edge that is independent of the external circuitry.
  • the circuit is able to adjust to capacitive loads that change during operation and to maintain a predetermined signal rate of increase.
  • a correction signal is formed which corrects the amplifier output voltage in such a way that a too rapid rise in the output signal, as would occur without this correction measure in the start-up range (output voltage ⁇ -C 1.5 V; 10 to 20 ns) would occur, is prevented.
  • a reduction of the interference radiation can be achieved by using the circuit in integrated circuits. This makes a contribution to the functional reliability of control units. Furthermore, necessary measures for processing input signals on integrated circuits, e.g. by filtering out interference signals, can be eliminated or reduced.
  • FIG. 1 shows a basic circuit diagram of a circuit for limiting the signal slew rate of output signals of integrated circuits
  • FIG. 2 shows a concrete embodiment of a circuit according to the basic circuit diagram according to FIG. 1.
  • Fig. 1 is an essentially mirror-image circuit consisting of an upper part for rising flanks and a lower part (with reversed polarities) for falling flanks.
  • the upper part for rising edges is described:
  • a current source I ⁇ _ which can be connected to the non-inverting input of a differential amplifier V ] _ ' via a switch S_ when the input signal changes from' 0 'to' 1 '.
  • the inverting input of the differential amplifier V ⁇ _ is connected to the circuit output, which is represented by an external, capacitive load CL.
  • the output of the differential amplifier V ⁇ _ is connected to the gate of an output transistor MP.
  • the other two transistor connections are each connected to a voltage source VCC and the output of the circuit CL.
  • a differentiating element DDT1 is also provided between the output of the circuit CL and the differential amplifier V] _.
  • the non-inverting input of the differential amplifier V] has a connection with a capacitance C__.
  • the circuit part shown has the following function: the output and input should initially be at logic '0', corresponding to 0 V. If the input is set to logic '1', the capacitance Ci is connected to the current source I ⁇ via the switches S ⁇ . The voltage across the capacitance changes according to the following equation: •
  • the differentiating element DDT1 contains an RC element and differentiates the voltage across the capacitance L and forms a correction signal which is fed to the differential amplifier V ] _. This corrects the amplifier output voltage in such a way that a too rapid rise in the output signal in the start-up range (output voltage «- 1.5 V) is prevented.
  • an internal reference signal with a certain signal slew rate is thus generated generated via the capacitance C__ and the output signal tracked accordingly.
  • the signal rise speed at the output CL is determined via the differentiating element DDT1 and corresponding difference signals are fed to the differential amplifier V ⁇ _ for a correction .
  • the lower part of the circuit in FIG. 1 consists of the differential amplifier V2, the capacitor Ci, a differentiator DDT2 and an output transistor MN.
  • This circuit part operates in accordance with the previously described first circuit part when the input signal changes from logic '1' to '0'.
  • the circuits Hi and H2 shown further at the outputs of the differential amplifiers V ⁇ _ and V2 ensure that the output transistors MP and MN are never at the same time in the conductive state.
  • the rising edge is generated here with the capacitances C27 and C28 and with the current IREF1.
  • the falling edge is generated with the capacitances C21 and C22 and with the current IREF2.
  • the reference signal and output signal can be divided capacitively. This takes place through the capacitance pairs C21 / C22. 23 / C24, 25 / C26 and ⁇ ⁇ C27 / 28 • The capacitive division also achieves a better control characteristic.

Landscapes

  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Logic Circuits (AREA)

Abstract

La présente invention se rapporte à un circuit pour la limitation de la vitesse de montée des signaux de sortie de circuits intégrés. Selon l'invention, le circuit est inclus dans le circuit intégré, le circuit engendrant un signal de référence et le signal de sortie étant poursuivi en conséquence. En outre, un élément différenciateur (DDT1, DDT2) détermine la vitesse de montée du signal de sortie et en dérive un signal de correction pour la poursuite du signal de sortie.
PCT/DE1991/000374 1990-06-12 1991-05-04 Circuit pour la limitation de la vitesse de montee des signaux de sortie de circuits integres WO1991020129A1 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
DEP4018754.3 1990-06-12
DE19904018754 DE4018754A1 (de) 1990-06-12 1990-06-12 Schaltung zur begrenzung der signalanstiegsgeschwindigkeit von ausgangssignalen integrierter schaltkreise

Publications (1)

Publication Number Publication Date
WO1991020129A1 true WO1991020129A1 (fr) 1991-12-26

Family

ID=6408246

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/DE1991/000374 WO1991020129A1 (fr) 1990-06-12 1991-05-04 Circuit pour la limitation de la vitesse de montee des signaux de sortie de circuits integres

Country Status (2)

Country Link
DE (1) DE4018754A1 (fr)
WO (1) WO1991020129A1 (fr)

Cited By (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0576204A1 (fr) * 1992-06-23 1993-12-29 AT&T Corp. Circuit tampon integré avec contrôle des temps de montée et de descente
EP0577367A2 (fr) * 1992-06-30 1994-01-05 STMicroelectronics, Inc. Circuit à enrichissement à temps pour un dispositif de puissance d'attaque du côté de la tension pour un moteur à courant continu polyphasé
WO1994029962A1 (fr) * 1993-06-08 1994-12-22 National Semiconductor Corporation Bus cmos compatible btl et etage d'attaque pour lignes de transmission
US5463331A (en) * 1993-06-08 1995-10-31 National Semiconductor Corporation Programmable slew rate CMOS buffer and transmission line driver with temperature compensation
US5483184A (en) * 1993-06-08 1996-01-09 National Semiconductor Corporation Programmable CMOS bus and transmission line receiver
US5539341A (en) * 1993-06-08 1996-07-23 National Semiconductor Corporation CMOS bus and transmission line driver having programmable edge rate control
US5543746A (en) * 1993-06-08 1996-08-06 National Semiconductor Corp. Programmable CMOS current source having positive temperature coefficient
US5557223A (en) * 1993-06-08 1996-09-17 National Semiconductor Corporation CMOS bus and transmission line driver having compensated edge rate control
GB2299720A (en) * 1995-04-05 1996-10-09 Hewlett Packard Co CMOS output driver using reference slope signals
US5818260A (en) * 1996-04-24 1998-10-06 National Semiconductor Corporation Transmission line driver having controllable rise and fall times with variable output low and minimal on/off delay
DE19910352C1 (de) * 1999-03-09 2000-06-15 Siemens Ag Kompensationsschaltung für Treiberschaltungen
US6114895A (en) * 1997-10-29 2000-09-05 Agilent Technologies Integrated circuit assembly having output pads with application specific characteristics and method of operation
EP1091492A1 (fr) * 1999-10-08 2001-04-11 STMicroelectronics S.r.l. Tampon de sortie pour signaux numériques

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE50100686D1 (de) * 2000-01-20 2003-10-30 Infineon Technologies Ag Anordnung und verfahren zum einstellen der flankenzeiten eines oder mehrerer treiber sowie treiberschaltung
US6670821B2 (en) * 2002-01-02 2003-12-30 Broadcom Corporation Methods and systems for sensing and compensating for process, voltage, temperature, and load variations

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB2203308A (en) * 1987-04-07 1988-10-12 Western Digital Corp Reducing transient noise in output driver IC
EP0347083A2 (fr) * 1988-06-15 1989-12-20 Advanced Micro Devices, Inc. Configuration de porte d'attaque de sortie TTL
EP0368524A1 (fr) * 1988-11-09 1990-05-16 Ncr International Inc. Circuit de tampon de sortie

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB2203308A (en) * 1987-04-07 1988-10-12 Western Digital Corp Reducing transient noise in output driver IC
EP0347083A2 (fr) * 1988-06-15 1989-12-20 Advanced Micro Devices, Inc. Configuration de porte d'attaque de sortie TTL
EP0368524A1 (fr) * 1988-11-09 1990-05-16 Ncr International Inc. Circuit de tampon de sortie

Cited By (20)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5311084A (en) * 1992-06-23 1994-05-10 At&T Bell Laboratories Integrated circuit buffer with controlled rise/fall time
EP0576204A1 (fr) * 1992-06-23 1993-12-29 AT&T Corp. Circuit tampon integré avec contrôle des temps de montée et de descente
EP0577367A3 (fr) * 1992-06-30 1995-05-17 Sgs Thomson Microelectronics Circuit à enrichissement à temps pour un dispositif de puissance d'attaque du cÔté de la tension pour un moteur à courant continu polyphasé.
EP0577367A2 (fr) * 1992-06-30 1994-01-05 STMicroelectronics, Inc. Circuit à enrichissement à temps pour un dispositif de puissance d'attaque du côté de la tension pour un moteur à courant continu polyphasé
US5557223A (en) * 1993-06-08 1996-09-17 National Semiconductor Corporation CMOS bus and transmission line driver having compensated edge rate control
KR100314893B1 (ko) * 1993-06-08 2002-02-28 클라크 3세 존 엠. Cmos-btl 호환가능버스 및 전송선 드라이버
US5463331A (en) * 1993-06-08 1995-10-31 National Semiconductor Corporation Programmable slew rate CMOS buffer and transmission line driver with temperature compensation
US5483184A (en) * 1993-06-08 1996-01-09 National Semiconductor Corporation Programmable CMOS bus and transmission line receiver
US5539341A (en) * 1993-06-08 1996-07-23 National Semiconductor Corporation CMOS bus and transmission line driver having programmable edge rate control
US5543746A (en) * 1993-06-08 1996-08-06 National Semiconductor Corp. Programmable CMOS current source having positive temperature coefficient
WO1994029962A1 (fr) * 1993-06-08 1994-12-22 National Semiconductor Corporation Bus cmos compatible btl et etage d'attaque pour lignes de transmission
US5438282A (en) * 1993-06-08 1995-08-01 National Semiconductor Corporation CMOS BTL compatible bus and transmission line driver
GB2299720A (en) * 1995-04-05 1996-10-09 Hewlett Packard Co CMOS output driver using reference slope signals
GB2299720B (en) * 1995-04-05 1999-06-02 Hewlett Packard Co Method and apparatus for a load adaptive pad driver
US5598119A (en) * 1995-04-05 1997-01-28 Hewlett-Packard Company Method and apparatus for a load adaptive pad driver
US5818260A (en) * 1996-04-24 1998-10-06 National Semiconductor Corporation Transmission line driver having controllable rise and fall times with variable output low and minimal on/off delay
US6114895A (en) * 1997-10-29 2000-09-05 Agilent Technologies Integrated circuit assembly having output pads with application specific characteristics and method of operation
DE19910352C1 (de) * 1999-03-09 2000-06-15 Siemens Ag Kompensationsschaltung für Treiberschaltungen
EP1091492A1 (fr) * 1999-10-08 2001-04-11 STMicroelectronics S.r.l. Tampon de sortie pour signaux numériques
US6545503B1 (en) 1999-10-08 2003-04-08 Stmicroelectronics S.R.L. Output buffer for digital signals

Also Published As

Publication number Publication date
DE4018754A1 (de) 1991-12-19

Similar Documents

Publication Publication Date Title
DE60024393T2 (de) PLL-Schaltung mit reduziertem Phasenoffset ohne Erhöhung der Betriebsspannung
DE69814250T2 (de) Spannungsregelung mit Lastpolstabilisation
DE60020451T2 (de) Komparatorschaltung
DE3872275T2 (de) Cmos-referenzspannungsgeneratoreinrichtung.
DE3839888C2 (fr)
WO1991020129A1 (fr) Circuit pour la limitation de la vitesse de montee des signaux de sortie de circuits integres
EP0591750B1 (fr) Méthode pour régler le courant d'un circuit d'attaque de sortie intégré monolithique
DE69028324T2 (de) Signalverzögerungsschaltung mit Ladungspumpenschaltung
DE10214304A1 (de) Verfahren und Vorrichtung zur Erzeugung zweier Signale mit einem vorbestimmten Abstand sich entsprechender Signalflanken zueinander
DE102008039195B4 (de) Verfahren und Elektronikvorrichtung zum Erfassen der Frequenz eines Eingangstaktsignals einer integrierten Schaltung und integrierte Schaltung
DE3786778T2 (de) Spannungsvergleichsschaltung.
DE3725339A1 (de) Automatische justierschaltung zum justieren der zeitkonstanten einer filterschaltung
DE10152285A1 (de) Funktionsgenerator mit einstellbarer Schwingungsfrequenz
DE10232346B4 (de) Schaltungsanordnung und Verfahren zur Datensignalreproduktion
DE102005028173B4 (de) Integrierte CMOS-Tastverhältnis-Korrekturschaltung für ein Taktsignal
DE68921136T2 (de) Transistorverstärker für hohe Anstiegsgeschwindigkeiten und kapazitive Belastungen.
DE102005020803A1 (de) Schaltungsanordnung mit einer Verstärkeranordnung und einer Offset-Kompensationsanordnung
DE10130123A1 (de) Verzögerungsregelkreis zur Erzeugung komplementärer Taktsignale
EP0540906B1 (fr) Dispositif redresseur sensible à la phase avec effet intégrateur
EP0780982A1 (fr) Système d'horloge complémentaire
EP0134527A1 (fr) Circuit MOS dynamique
DE3113800A1 (de) Frequenzmodulator
DE69113414T2 (de) Integrierte Konstantstromversorgung.
EP1066679B1 (fr) Procede et circuit pour commander la compensation de tensions de decalage d'un circuit de reception radio integre dans un module de circuit
DE69820925T2 (de) Takteingangsschaltung

Legal Events

Date Code Title Description
AK Designated states

Kind code of ref document: A1

Designated state(s): JP KR US

AL Designated countries for regional patents

Kind code of ref document: A1

Designated state(s): AT BE CH DE DK ES FR GB GR IT LU NL SE