WO1988000751A2 - Appareil d'affichage graphique a balayage recurrent - Google Patents

Appareil d'affichage graphique a balayage recurrent Download PDF

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Publication number
WO1988000751A2
WO1988000751A2 PCT/GB1987/000518 GB8700518W WO8800751A2 WO 1988000751 A2 WO1988000751 A2 WO 1988000751A2 GB 8700518 W GB8700518 W GB 8700518W WO 8800751 A2 WO8800751 A2 WO 8800751A2
Authority
WO
WIPO (PCT)
Prior art keywords
display
array
vram
displays
vrams
Prior art date
Application number
PCT/GB1987/000518
Other languages
English (en)
Other versions
WO1988000751A3 (fr
Inventor
Richard James Jales
Derek John Parkyn
Original Assignee
Sigmex Limited
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from GB868617579A external-priority patent/GB8617579D0/en
Application filed by Sigmex Limited filed Critical Sigmex Limited
Priority to GB8806423A priority Critical patent/GB2205470B/en
Publication of WO1988000751A2 publication Critical patent/WO1988000751A2/fr
Publication of WO1988000751A3 publication Critical patent/WO1988000751A3/fr

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/14—Digital output to display device ; Cooperation and interconnection of the display device with other functional units
    • G06F3/1423—Digital output to display device ; Cooperation and interconnection of the display device with other functional units controlling a plurality of local displays, e.g. CRT and flat panel display
    • G06F3/1431—Digital output to display device ; Cooperation and interconnection of the display device with other functional units controlling a plurality of local displays, e.g. CRT and flat panel display using a single graphics controller
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/14—Digital output to display device ; Cooperation and interconnection of the display device with other functional units
    • G06F3/153—Digital output to display device ; Cooperation and interconnection of the display device with other functional units using cathode-ray tubes
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06T—IMAGE DATA PROCESSING OR GENERATION, IN GENERAL
    • G06T1/00—General purpose image data processing
    • G06T1/20—Processor architectures; Processor configuration, e.g. pipelining
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G5/00—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
    • G09G5/36—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators characterised by the display of a graphic pattern, e.g. using an all-points-addressable [APA] memory
    • G09G5/39—Control of the bit-mapped memory
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G5/00—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
    • G09G5/34—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators for rolling or scrolling
    • G09G5/346—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators for rolling or scrolling for systems having a bit-mapped display memory

Definitions

  • This invention relates to raster-scan graphical display apparatus and in particular is concerned with the organisation of the display store and the associated devices for entering and retrieving data from the data store.
  • VRAM video ram
  • the VRAM is shown as comprising a rectangular array of bit storage positions, a column address decoder, a row address decoder.
  • a recirculating parallel-in/serial-out shift register 4 and a tap select decoder 5 are connected as shown.
  • a row of such storage positions can be selected by means of the row address decoder while the column address decoder 2 enables all columns of the storage array 1 simultaneously.
  • a video ram is shown connected to the input of a digital-to-analogue converter which provides an analogue drive signal for the display.
  • raster scan graphical display apparatus for use with computer terminals and comprising a plurality of VRAM stores organised for operation as a k x m array corresponding to an array of data positions each comprising a pixel of the display to be provided and where k is the number of VRAMs in each row and m is the number of VRAMs in each column, each VRAM store being arranged for the storage of data for a plurality of corresponding data positions for a plurality of display terminals, means being provided for cyclically accessing the rows of the VRAM array so as to correspond with consecutive lines of the respective displays.
  • the array is square and corresponds to a square pixel array of each of the displays.
  • a barrel shifter may be provided to control the cyclic access of the respective display terminals to the rows of the VRAM array.
  • Fig. 1 is a schematic diagram of a conventional VRAM storage arrangment
  • Fig. 2 is a block circuit diagram of the arrangement shown in Fig. 1 providing an output for a display
  • Fig. 3 is a block circuit diagram of raster scan graphical display apparatus embodying this invention.
  • Fig. 4 is a block schematic diagram of the data storage arrangement of the raster scan graphical display apparatus shown in Fig. 3;
  • Fig. 5 is a memory bit map illustrating the operation of the apparatus shown in Fig. 4;
  • Fig. 6 is a schematic diagram and associated graphs illustrating some aspects of the operation of the apparatus shown in Fig. 4;
  • Figs. 7 to 9 are schematic diagrams and tables illustrating the operation of the apparatus shown in Fig. 3.
  • Fig. 10 is a block schematic diagram corresponding to Fig. 4 of a modified form of the data storage arrangement.
  • raster scan graphical display apparatus 10 is arranged for use between a host computer 11 and a plurality (in the present case four) of display terminals 12 to 15.
  • the apparatus 10 comprises, as is shown in Fig. 4, a 4 x 4 array of VRAMs 0,0 to 3,3. Each row of the array is associated with a respective one of recirculating parallel-in/serial-out shift registers 16 to 19 whose serial outputs are connected to respective inputs of a barrel shifter 20 having shift control means 21 whose operation will be described below.
  • the barrel shifter 20 provides serial outputs respectively corresponding to selected ones of its serial inputs to digital-to-analogue converters 22 to 25 in a cyclic sequence determined by the shift control means 21.
  • the analogue signal outputs from the digital-to-analogue converters are respectively connected to the display terminals 12 to 15.
  • the apparatus shown in Fig. 4 is arranged to provide a display data memory whose bit map is as shown in Fig. 5 from which it can be seen that the four different displays occupy respectively different areas of the bit map of the data storage array.
  • each of the display storage areas has associated with it a respective line start address XSAO, YSAO to XSA3, YSA3.
  • the line start address XSAO, YSAO corresponds to the display of the terminal 12, XSA1, YSA1 to the display of the terminal 13, XSA2, YSA2 to the display of the terminal 14 and XSA3, YSA3 to the display of the terminal 15.
  • Fig. 6 there is shown the general arrangement of a single (for the sake of simplicity) display storage area and its relationship to the line start address.
  • the graphs also show the relationship of the various periods of the operational cycle in relation to the normal line blanking and line synchronisation pulses.
  • Fig. 6 during the line blanking period, 1 is a first time interval during which conventional dynamic memory refresh cycles can be provided and 2 is the time interval during which the four respective line start addresses are supplied to the respective rows of VRAMs.
  • each row of VRAMs provides a series of pixels comprising one line of that one of the displays to which the relevant row of VRAMs is presently connected by means of the barrel shifter 20.
  • the preferred arrangement of pixel contributions to each display line by the individual VRAMs in the relevant row is similar to the "modulo 4" arrangement for the y-direction described below where the x-direction runs parallel with the columns.
  • the pixels stored in the x-direction comprise 0 modulo 4 (0,4,8,%), 1 modulo 4 (1,5,9,%), 2 modulo 4 (2,6,10,%) and 3 modulo 4 (3,7,11,7) in the respective VRAMs of the row where the integers in question represent the address in the x-direction of the display line.
  • This optimises the processing of a 4 x 4 (generally k x k, e.g.
  • Fig. 7 how the VRAM rows contribute to the consecutive lines of each display, it being understood that each VRAM row can only contribute to one line of one display during each cycle stage of the storage array corresponding to a single setting of the barrel shifter.
  • m,n,p and q are the current line Y addresses divided by four over the complete Y address range for the respective displays.
  • Fig. 8 illustrates the relationship of the barrel shifter setting for the display terminal 12.
  • the barrel shifter is caused to change position by means of the shift control means 21 so as to connect the VRAM rows and associated shift registers 16 to 19 respectively to digital-to-analogue converters 25,22,23 and 24 (display terminals 15,12,13 and 14).
  • This association is indicated in Fig. 9 by the entries in respect of display line 1 modulo 4, while Fig. 7 indicates the direct association between the VRAM rows and the relevant display line for each of the display terminals.
  • Barrel shifter 20 is then shifted through further changes in position for the transfers corresponding to display lines 2 and 3 modulo 4 as indicated in Figs. 7 to 9.
  • the next change in position of the barrel shifter brings it back to its reset or initial position for the start of a new cycle of display data transfers.
  • FIG. 10 there is shown a modified form of the arrangement shown in Fig. 4 in the sense that the arrangement shown in Fig. 10 comprises an 8 x 8 array of VRAMs capable of driving a maximum of 8 independent displays as compared with 4 independent displays which can be driven by means of the arrangement shown in Fig. 4. Otherwise the two arrangements operate in a similar manner.
  • a plurality of display terminals can be driven via a common data storage array providing pixel array capabilities with regard to image handling and processing and since all four heads have access to all the image information in the storage array whether such image information is stored as predetermined primitive images or working images, there are many advantages to be gained from the common access for all the display terminals.
  • Video RAMS 0,0 to 3,3 whose rows provide respect consecutive lines of the raster in cyclic sequence determined by means of a barrel shifter (20). All four displays can t use common data storage and operate using an appropriately sized pixel array e.g. 4 x 4, 8 x 8, for image handling and p cessing. FOR THE PURPOSES OF INFORMATION ONLY

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Human Computer Interaction (AREA)
  • General Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Computer Graphics (AREA)
  • Controls And Circuits For Display Device (AREA)
  • Control Of Indicators Other Than Cathode Ray Tubes (AREA)

Abstract

Quatre affichages indépendants (12 à 15) sont commandés par une série de mémoires vidéo à accès sélectif (0,0 à 3,3) dont les rangées fournissent des lignes consécutives respectives du canevas selon une séquence cyclique déterminée à l'aide d'un décaleur cylindrique (2). Les quatre affichages peuvent alors utiliser tous une mémoire commune de données et fonctionner avec un agencement d'éléments d'image de la grandeur appropriée, par exemple 4 x 4, 8 x 8, pour saisir et traiter des images.
PCT/GB1987/000518 1986-07-18 1987-07-17 Appareil d'affichage graphique a balayage recurrent WO1988000751A2 (fr)

Priority Applications (1)

Application Number Priority Date Filing Date Title
GB8806423A GB2205470B (en) 1986-07-18 1987-07-17 Raster-scan graphical display apparatus

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
GB868617579A GB8617579D0 (en) 1986-07-18 1986-07-18 Raster graphical display system
GB8617579 1986-07-18
GB8630894 1986-12-24
GB868630894A GB8630894D0 (en) 1986-07-18 1986-12-24 Raster graphical display apparatus

Publications (2)

Publication Number Publication Date
WO1988000751A2 true WO1988000751A2 (fr) 1988-01-28
WO1988000751A3 WO1988000751A3 (fr) 1988-04-07

Family

ID=26291057

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/GB1987/000518 WO1988000751A2 (fr) 1986-07-18 1987-07-17 Appareil d'affichage graphique a balayage recurrent

Country Status (3)

Country Link
EP (1) EP0277962A1 (fr)
GB (1) GB2205470B (fr)
WO (1) WO1988000751A2 (fr)

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0427322A1 (fr) * 1989-11-06 1991-05-15 Océ-Nederland B.V. Méthode et moyens de traitement de données provenant d'images
GB2243062A (en) * 1990-04-11 1991-10-16 Afe Displays Ltd Image creation system
GB2243519A (en) * 1990-04-11 1991-10-30 Afe Displays Ltd Image display system
GB2264616A (en) * 1992-02-25 1993-09-01 Apple Computer Row interleaved frame buffer.
US5361078A (en) * 1990-02-16 1994-11-01 Nadimelia Limited Multiple screen graphics display
WO1999005650A1 (fr) * 1997-07-24 1999-02-04 Electronics For Imaging, Inc. Procede et systeme de conversion de format d'image

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2528604A1 (fr) * 1982-06-09 1983-12-16 Tatsumi Denshi Kogyo Kk Procede et appareil pour afficher une image coordonnee sur les ecrans de plusieurs dispositifs d'affichage

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2528604A1 (fr) * 1982-06-09 1983-12-16 Tatsumi Denshi Kogyo Kk Procede et appareil pour afficher une image coordonnee sur les ecrans de plusieurs dispositifs d'affichage

Cited By (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0427322A1 (fr) * 1989-11-06 1991-05-15 Océ-Nederland B.V. Méthode et moyens de traitement de données provenant d'images
US5070531A (en) * 1989-11-06 1991-12-03 Oce-Nederland B.V. Method of and means for processing image data
US5361078A (en) * 1990-02-16 1994-11-01 Nadimelia Limited Multiple screen graphics display
GB2243062A (en) * 1990-04-11 1991-10-16 Afe Displays Ltd Image creation system
GB2243519A (en) * 1990-04-11 1991-10-30 Afe Displays Ltd Image display system
GB2243519B (en) * 1990-04-11 1994-03-23 Afe Displays Ltd Image display system
GB2243062B (en) * 1990-04-11 1994-06-01 Afe Displays Ltd Image creation system
GB2264616A (en) * 1992-02-25 1993-09-01 Apple Computer Row interleaved frame buffer.
US5357606A (en) * 1992-02-25 1994-10-18 Apple Computer, Inc. Row interleaved frame buffer
WO1999005650A1 (fr) * 1997-07-24 1999-02-04 Electronics For Imaging, Inc. Procede et systeme de conversion de format d'image
US6348978B1 (en) 1997-07-24 2002-02-19 Electronics For Imaging, Inc. Method and system for image format conversion

Also Published As

Publication number Publication date
GB2205470A (en) 1988-12-07
WO1988000751A3 (fr) 1988-04-07
GB2205470B (en) 1990-08-29
EP0277962A1 (fr) 1988-08-17
GB8806423D0 (en) 1988-04-20

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