WO1987001858A3 - Systeme de memoire fonctionnant suivant un mode par page - Google Patents

Systeme de memoire fonctionnant suivant un mode par page Download PDF

Info

Publication number
WO1987001858A3
WO1987001858A3 PCT/US1986/001826 US8601826W WO8701858A3 WO 1987001858 A3 WO1987001858 A3 WO 1987001858A3 US 8601826 W US8601826 W US 8601826W WO 8701858 A3 WO8701858 A3 WO 8701858A3
Authority
WO
WIPO (PCT)
Prior art keywords
memory
page mode
mode operation
select
memory system
Prior art date
Application number
PCT/US1986/001826
Other languages
English (en)
Other versions
WO1987001858A2 (fr
Inventor
Billy Kenneth Taylor
Larry Clifford James
Original Assignee
Ncr Co
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Ncr Co filed Critical Ncr Co
Priority to AT86905621T priority Critical patent/ATE59728T1/de
Priority to DE8686905621T priority patent/DE3676488D1/de
Priority to DE1986905621 priority patent/DE238550T1/de
Publication of WO1987001858A2 publication Critical patent/WO1987001858A2/fr
Priority to DK264287A priority patent/DK170584B1/da
Publication of WO1987001858A3 publication Critical patent/WO1987001858A3/fr

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1015—Read-write modes for single port memories, i.e. having either a random port or a serial port
    • G11C7/1018—Serial bit line access mode, e.g. using bit line address shift registers, bit line address counters, bit line burst counters
    • G11C7/1021—Page serial bit line access mode, i.e. using an enabled row address stroke pulse with its associated word line address and a sequence of enabled column address stroke pulses each with its associated bit line address
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/12—Group selection circuits, e.g. for memory block selection, chip selection, array selection
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/18—Address timing or clocking circuits; Address control signal generation or management, e.g. for row address strobe [RAS] or column address strobe [CAS] signals

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Dram (AREA)
  • Debugging And Monitoring (AREA)
  • Memory System (AREA)

Abstract

Un système de mémoire comprend une pluralité de cartes de mémoire (10A-10C) portant chacune une pluralité de blocs de mémoire. Chaque bloc de mémoire comprend une pluralité d'éléments de mémoire (20A). Dans un fonctionnement de mode par page du système de mémoire, tous les éléments de mémoire reçoivent un signal actif d'échantillonage d'adresse de rangée, lequel est maintenu actif tant que dure le fonctionnement en mode par page. Des informations d'adresse de mémoire sont décodées par des décodeurs (22) de cartes pour sélectionner une carte de mémoire ainsi que par des décodeurs (24A) de bloc pour sélectionner un bloc de mémoire, permettant ainsi aux éléments de mémoire sélectionnés d'effectuer des opérations de lecture ou d'écriture dans un mode par page.
PCT/US1986/001826 1985-09-23 1986-09-08 Systeme de memoire fonctionnant suivant un mode par page WO1987001858A2 (fr)

Priority Applications (4)

Application Number Priority Date Filing Date Title
AT86905621T ATE59728T1 (de) 1985-09-23 1986-09-08 Speichersystem mit seitenbetriebsart.
DE8686905621T DE3676488D1 (de) 1985-09-23 1986-09-08 Speichersystem mit seitenbetriebsart.
DE1986905621 DE238550T1 (de) 1985-09-23 1986-09-08 Speichersystem mit seitenbetriebsart.
DK264287A DK170584B1 (da) 1985-09-23 1987-05-25 Pagineret lager til en databehandlingsenhed og fremgangsmåde til drift af denne

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US778,815 1985-09-23
US06/778,815 US4823324A (en) 1985-09-23 1985-09-23 Page mode operation of main system memory in a medium scale computer

Publications (2)

Publication Number Publication Date
WO1987001858A2 WO1987001858A2 (fr) 1987-03-26
WO1987001858A3 true WO1987001858A3 (fr) 1987-07-02

Family

ID=25114468

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US1986/001826 WO1987001858A2 (fr) 1985-09-23 1986-09-08 Systeme de memoire fonctionnant suivant un mode par page

Country Status (9)

Country Link
US (1) US4823324A (fr)
EP (1) EP0238550B1 (fr)
JP (1) JP2595220B2 (fr)
AU (1) AU583950B2 (fr)
CA (1) CA1258910A (fr)
DE (1) DE3676488D1 (fr)
DK (1) DK170584B1 (fr)
WO (1) WO1987001858A2 (fr)
ZA (1) ZA866857B (fr)

Families Citing this family (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02500697A (ja) * 1987-06-02 1990-03-08 ヒューズ・エアクラフト・カンパニー パイプラインメモリ構造
GB2215498A (en) * 1988-02-01 1989-09-20 Tsb International Inc Expandable reconfigurable memory circuit
US5335336A (en) * 1988-03-28 1994-08-02 Hitachi, Ltd. Memory device having refresh mode returning previous page address for resumed page mode
US5724540A (en) * 1988-03-28 1998-03-03 Hitachi, Ltd. Memory system having a column address counter and a page address counter
US5239638A (en) * 1988-12-30 1993-08-24 Intel Corporation Two strobed memory access
GB8907933D0 (en) * 1989-04-08 1989-05-24 Macdonald Neal H Control system for an array of circuit modules
US4967397A (en) * 1989-05-15 1990-10-30 Unisys Corporation Dynamic RAM controller
US5113511A (en) * 1989-06-02 1992-05-12 Atari Corporation System for dynamically providing predicted high/slow speed accessing memory to a processing unit based on instructions
JPH0682339B2 (ja) * 1990-08-31 1994-10-19 インターナショナル・ビジネス・マシーンズ・コーポレイション メモリ・アクセス・システムおよび方法
US5479640A (en) * 1990-08-31 1995-12-26 International Business Machines Corporation Memory access system including a memory controller with memory redrive circuitry
US5278967A (en) * 1990-08-31 1994-01-11 International Business Machines Corporation System for providing gapless data transfer from page-mode dynamic random access memories
JPH07281948A (ja) * 1994-04-06 1995-10-27 Mitsubishi Electric Corp メモリ制御装置
JPH07334416A (ja) * 1994-06-06 1995-12-22 Internatl Business Mach Corp <Ibm> コンピュータ・システムにおけるページ・モード・メモリの初期設定の方法および手段
US6209071B1 (en) 1996-05-07 2001-03-27 Rambus Inc. Asynchronous request/synchronous data dynamic random access memory
US6263448B1 (en) 1997-10-10 2001-07-17 Rambus Inc. Power control system for synchronous memory device
US6009019A (en) * 1998-02-05 1999-12-28 S3 Incorporated Real time DRAM eliminating a performance penalty for crossing a page boundary
DE102013012259B3 (de) 2013-07-24 2014-10-09 Airbus Defence and Space GmbH Aluminium-Werkstoff mit verbesserter Ausscheidungshärtung, Verfahren zu dessen Herstellung und Verwendung des Aluminium-Werkstoffes

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1980000632A1 (fr) * 1978-09-01 1980-04-03 Ncr Co Systeme de memoire a haute densite
GB2093236A (en) * 1981-02-09 1982-08-25 Sony Corp Semiconductor random access memory arrangements

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4541090A (en) * 1981-06-09 1985-09-10 Matsushita Electric Industrial Co., Ltd. Semiconductor memory device
JPS57208686A (en) * 1981-06-16 1982-12-21 Fujitsu Ltd Semiconductor storage device
JPH0632217B2 (ja) * 1981-06-29 1994-04-27 富士通株式会社 半導体記憶装置
JPS59135695A (ja) * 1983-01-24 1984-08-03 Mitsubishi Electric Corp 半導体記憶装置
JPS59144966A (ja) * 1983-02-08 1984-08-20 Nec Corp デ−タ処理装置
JPS6134793A (ja) * 1984-07-27 1986-02-19 Hitachi Ltd ダイナミツクメモリ装置における診断及びエラ−訂正装置

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1980000632A1 (fr) * 1978-09-01 1980-04-03 Ncr Co Systeme de memoire a haute densite
GB2093236A (en) * 1981-02-09 1982-08-25 Sony Corp Semiconductor random access memory arrangements

Also Published As

Publication number Publication date
EP0238550B1 (fr) 1991-01-02
WO1987001858A2 (fr) 1987-03-26
DK264287A (da) 1987-05-25
DE3676488D1 (de) 1991-02-07
JP2595220B2 (ja) 1997-04-02
EP0238550A1 (fr) 1987-09-30
AU583950B2 (en) 1989-05-11
ZA866857B (en) 1987-04-29
US4823324A (en) 1989-04-18
CA1258910A (fr) 1989-08-29
JPS63501045A (ja) 1988-04-14
AU6336686A (en) 1987-04-07
DK264287D0 (da) 1987-05-25
DK170584B1 (da) 1995-10-30

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