WO1986006538A3 - Circuit de commande de memoire permettant a un systeme de micro-ordinateur d'utiliser des memoires a acces selectif statiques et dynamiques - Google Patents

Circuit de commande de memoire permettant a un systeme de micro-ordinateur d'utiliser des memoires a acces selectif statiques et dynamiques Download PDF

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Publication number
WO1986006538A3
WO1986006538A3 PCT/US1986/000726 US8600726W WO8606538A3 WO 1986006538 A3 WO1986006538 A3 WO 1986006538A3 US 8600726 W US8600726 W US 8600726W WO 8606538 A3 WO8606538 A3 WO 8606538A3
Authority
WO
WIPO (PCT)
Prior art keywords
microcomputer system
control circuit
memory control
dynamic rams
utilize static
Prior art date
Application number
PCT/US1986/000726
Other languages
English (en)
Other versions
WO1986006538A2 (fr
Inventor
Jeffrey Gerald Miner
Original Assignee
American Telephone & Telegraph
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by American Telephone & Telegraph filed Critical American Telephone & Telegraph
Priority to JP61502316A priority Critical patent/JPH0731630B2/ja
Priority to DE8686902688T priority patent/DE3667874D1/de
Publication of WO1986006538A2 publication Critical patent/WO1986006538A2/fr
Publication of WO1986006538A3 publication Critical patent/WO1986006538A3/fr

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/18—Address timing or clocking circuits; Address control signal generation or management, e.g. for row address strobe [RAS] or column address strobe [CAS] signals
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/12—Group selection circuits, e.g. for memory block selection, chip selection, array selection

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Read Only Memory (AREA)
  • Microcomputers (AREA)
  • Semiconductor Memories (AREA)
  • Static Random-Access Memory (AREA)

Abstract

Commande de l'accès à la mémoire d'un système de micro-ordinateur, compatible aussi bien avec des mémoires du type dynamique que statique. Un circuit de déclenchement (12) est sensible aux signaux de commande de validation de lecture/écriture et de verrouillage d'adresse d'un micro-processeur (10), et délivre un signal de validation utilisé (en 13) pour produire un signal de validation de puce compatible avec la synchronisation et la commande requises par les mémoires aussi bien dynamiques que statiques.
PCT/US1986/000726 1985-04-19 1986-04-09 Circuit de commande de memoire permettant a un systeme de micro-ordinateur d'utiliser des memoires a acces selectif statiques et dynamiques WO1986006538A2 (fr)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP61502316A JPH0731630B2 (ja) 1985-04-19 1986-04-09 マイクロプロセッサシステム
DE8686902688T DE3667874D1 (de) 1985-04-19 1986-04-09 Speichersteuerungsschaltung die einem mikrorechnersystem ermoeglicht statische und dynamische rams zu verwenden.

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US725,019 1985-04-19
US06/725,019 US4755964A (en) 1985-04-19 1985-04-19 Memory control circuit permitting microcomputer system to utilize static and dynamic rams

Publications (2)

Publication Number Publication Date
WO1986006538A2 WO1986006538A2 (fr) 1986-11-06
WO1986006538A3 true WO1986006538A3 (fr) 1987-01-15

Family

ID=24912804

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US1986/000726 WO1986006538A2 (fr) 1985-04-19 1986-04-09 Circuit de commande de memoire permettant a un systeme de micro-ordinateur d'utiliser des memoires a acces selectif statiques et dynamiques

Country Status (6)

Country Link
US (1) US4755964A (fr)
EP (1) EP0217937B1 (fr)
JP (1) JPH0731630B2 (fr)
CA (1) CA1253977A (fr)
DE (1) DE3667874D1 (fr)
WO (1) WO1986006538A2 (fr)

Families Citing this family (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0642263B2 (ja) * 1984-11-26 1994-06-01 株式会社日立製作所 デ−タ処理装置
JPS63229691A (ja) * 1987-03-18 1988-09-26 Nec Ic Microcomput Syst Ltd メモリ周辺回路
JP2569554B2 (ja) * 1987-05-13 1997-01-08 三菱電機株式会社 ダイナミツクｒａｍ
JPH02177194A (ja) * 1988-12-28 1990-07-10 Mitsubishi Electric Corp ダイナミックランダムアクセスメモリ装置
CA2011518C (fr) * 1989-04-25 1993-04-20 Ronald N. Fortino Puces de memoire vive dynamique avec antememoire repartie et methode de controle connexe
EP0475588B1 (fr) * 1990-08-17 1996-06-26 STMicroelectronics, Inc. Mémoire à semi-conducteur avec entrée de mode test empêchée pendant couple de démarrage
US5276843A (en) * 1991-04-12 1994-01-04 Micron Technology, Inc. Dynamic RAM array for emulating a static RAM array
US5418924A (en) * 1992-08-31 1995-05-23 Hewlett-Packard Company Memory controller with programmable timing
US5809340A (en) * 1993-04-30 1998-09-15 Packard Bell Nec Adaptively generating timing signals for access to various memory devices based on stored profiles
US6185629B1 (en) * 1994-03-08 2001-02-06 Texas Instruments Incorporated Data transfer controller employing differing memory interface protocols dependent upon external input at predetermined time
JP3540844B2 (ja) * 1994-11-02 2004-07-07 日本テキサス・インスツルメンツ株式会社 半導体集積回路
US5764582A (en) * 1996-11-26 1998-06-09 Powerchip Semiconductor Corp. Apparatus and method of refreshing a dynamic random access memory
US6035371A (en) * 1997-05-28 2000-03-07 3Com Corporation Method and apparatus for addressing a static random access memory device based on signals for addressing a dynamic memory access device
EP1122733A1 (fr) * 2000-01-31 2001-08-08 STMicroelectronics S.r.l. Régénération interne d'un signal d'activation d'adressage (ALE) d'un protocole de gestion pour une mémoire entrelacée avec accès en rafale et circuit correspondant

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4087704A (en) * 1974-11-04 1978-05-02 Intel Corporation Sequential timing circuitry for a semiconductor memory
DE2834818B1 (de) * 1978-08-09 1980-02-07 Standard Elek K Lorenz Ag Schaltungsanordnung zur wahlweisen Erzeugung eines Lesesignals oder eines Schreibsignals

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5740793A (en) * 1980-07-22 1982-03-06 Nec Corp Memory circuit

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4087704A (en) * 1974-11-04 1978-05-02 Intel Corporation Sequential timing circuitry for a semiconductor memory
DE2834818B1 (de) * 1978-08-09 1980-02-07 Standard Elek K Lorenz Ag Schaltungsanordnung zur wahlweisen Erzeugung eines Lesesignals oder eines Schreibsignals

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
PATENTS ABSTRACTS OF JAPAN, Volume 6, No. 112, (P-124) (990), 23 June 1982, & JP, A, 5740793 (Nippon Denki) (6 March 1982) *

Also Published As

Publication number Publication date
EP0217937B1 (fr) 1989-12-27
WO1986006538A2 (fr) 1986-11-06
EP0217937A1 (fr) 1987-04-15
JPH0731630B2 (ja) 1995-04-10
CA1253977A (fr) 1989-05-09
JPS62502574A (ja) 1987-10-01
US4755964A (en) 1988-07-05
DE3667874D1 (de) 1990-02-01

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