CA2011632A1 - Circuit de commande a stockage partiel utilise dans une memoire - Google Patents

Circuit de commande a stockage partiel utilise dans une memoire

Info

Publication number
CA2011632A1
CA2011632A1 CA2011632A CA2011632A CA2011632A1 CA 2011632 A1 CA2011632 A1 CA 2011632A1 CA 2011632 A CA2011632 A CA 2011632A CA 2011632 A CA2011632 A CA 2011632A CA 2011632 A1 CA2011632 A1 CA 2011632A1
Authority
CA
Canada
Prior art keywords
data
memory banks
partially storing
storing data
registering
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
CA2011632A
Other languages
English (en)
Other versions
CA2011632C (fr
Inventor
Takashi Ibi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Publication of CA2011632A1 publication Critical patent/CA2011632A1/fr
Application granted granted Critical
Publication of CA2011632C publication Critical patent/CA2011632C/fr
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/04—Addressing variable-length words or parts of words

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Dram (AREA)
  • Memory System (AREA)
  • Static Random-Access Memory (AREA)
  • Techniques For Improving Reliability Of Storages (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
  • Complex Calculations (AREA)
CA002011632A 1989-03-08 1990-03-07 Circuit de commande a stockage partiel utilise dans une memoire Expired - Fee Related CA2011632C (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP1-055407 1989-03-08
JP01055407A JP3081614B2 (ja) 1989-03-08 1989-03-08 部分書込み制御装置

Publications (2)

Publication Number Publication Date
CA2011632A1 true CA2011632A1 (fr) 1990-09-08
CA2011632C CA2011632C (fr) 1996-07-09

Family

ID=12997694

Family Applications (1)

Application Number Title Priority Date Filing Date
CA002011632A Expired - Fee Related CA2011632C (fr) 1989-03-08 1990-03-07 Circuit de commande a stockage partiel utilise dans une memoire

Country Status (7)

Country Link
US (1) US5206942A (fr)
EP (1) EP0386719B1 (fr)
JP (1) JP3081614B2 (fr)
KR (1) KR920005739B1 (fr)
AU (1) AU619088B2 (fr)
CA (1) CA2011632C (fr)
DE (1) DE69032776T2 (fr)

Families Citing this family (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0454652A (ja) * 1990-06-25 1992-02-21 Nec Corp マイクロコンピュータ
JPH04242433A (ja) * 1991-01-17 1992-08-31 Nec Corp マイクロプロセッサ
US5734927A (en) * 1995-06-08 1998-03-31 Texas Instruments Incorporated System having registers for receiving data, registers for transmitting data, both at a different clock rate, and control circuitry for shifting the different clock rates
US5982676A (en) * 1998-05-26 1999-11-09 Stmicroelectronics, Inc. Low voltage generator for bitlines
US6272609B1 (en) * 1998-07-31 2001-08-07 Micron Electronics, Inc. Pipelined memory controller
US6215708B1 (en) * 1998-09-30 2001-04-10 Integrated Device Technology, Inc. Charge pump for improving memory cell low VCC performance without increasing gate oxide thickness
JP3742250B2 (ja) * 1999-06-04 2006-02-01 富士通株式会社 パケットデータ処理装置及びそれを用いたパケット中継装置
US7577640B1 (en) * 2004-03-31 2009-08-18 Avaya Inc. Highly available, highly scalable multi-source logical database with low latency
US20070150697A1 (en) * 2005-05-10 2007-06-28 Telairity Semiconductor, Inc. Vector processor with multi-pipe vector block matching
US20060259737A1 (en) * 2005-05-10 2006-11-16 Telairity Semiconductor, Inc. Vector processor with special purpose registers and high speed memory access
US8139399B2 (en) * 2009-10-13 2012-03-20 Mosys, Inc. Multiple cycle memory write completion
JP2015108972A (ja) * 2013-12-04 2015-06-11 富士通株式会社 演算装置、演算装置の決定方法及びプログラム
AU2014380279B2 (en) 2014-01-31 2017-05-04 Hewlett-Packard Development Company, L.P. Three-dimensional addressing for erasable programmable read only memory

Family Cites Families (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3883854A (en) * 1973-11-30 1975-05-13 Ibm Interleaved memory control signal and data handling apparatus using pipelining techniques
JPS57105879A (en) * 1980-12-23 1982-07-01 Hitachi Ltd Control system for storage device
US4675808A (en) * 1983-08-08 1987-06-23 American Telephone And Telegraph Company At&T Bell Laboratories Multiplexed-address interface for addressing memories of various sizes
JPS60157646A (ja) * 1984-01-27 1985-08-17 Mitsubishi Electric Corp メモリバンク切換装置
JPH0670773B2 (ja) * 1984-11-01 1994-09-07 富士通株式会社 先行制御方式
US4601018A (en) * 1985-01-29 1986-07-15 Allen Baum Banked memory circuit
JPH0746323B2 (ja) * 1985-08-14 1995-05-17 富士通株式会社 部分書込みアクセスを圧縮する主記憶装置
JPS62194561A (ja) * 1986-02-21 1987-08-27 Toshiba Corp 半導体記憶装置
US4797850A (en) * 1986-05-12 1989-01-10 Advanced Micro Devices, Inc. Dynamic random access memory controller with multiple independent control channels
US4937781A (en) * 1988-05-13 1990-06-26 Dallas Semiconductor Corporation Dual port ram with arbitration status register
US5060145A (en) * 1989-09-06 1991-10-22 Unisys Corporation Memory access system for pipelined data paths to and from storage

Also Published As

Publication number Publication date
US5206942A (en) 1993-04-27
CA2011632C (fr) 1996-07-09
KR900014989A (ko) 1990-10-25
AU619088B2 (en) 1992-01-16
EP0386719A2 (fr) 1990-09-12
AU5113490A (en) 1990-09-20
JPH02234242A (ja) 1990-09-17
DE69032776D1 (de) 1999-01-07
EP0386719A3 (fr) 1992-01-22
DE69032776T2 (de) 1999-04-22
KR920005739B1 (ko) 1992-07-16
EP0386719B1 (fr) 1998-11-25
JP3081614B2 (ja) 2000-08-28

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Legal Events

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