Classifications

• • G—PHYSICS
  • G06—COMPUTING OR CALCULATING; COUNTING
  • G06F—ELECTRIC DIGITAL DATA PROCESSING
  • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
  • G06F13/38—Information transfer, e.g. on bus
  • G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
  • G06F13/4204—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus
  • G06F13/4234—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being a memory bus
  • G06F13/4243—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being a memory bus with synchronous protocol
• • G—PHYSICS
  • G05—CONTROLLING; REGULATING
  • G05B—CONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS
  • G05B19/00—Programme-control systems
  • G05B19/02—Programme-control systems electric
  • G05B19/18—Numerical control [NC], i.e. automatically operating machines, in particular machine tools, e.g. in a manufacturing environment, so as to execute positioning, movement or co-ordinated operations by means of programme data in numerical form
  • G05B19/414—Structure of the control system, e.g. common controller or multiprocessor systems, interface to servo, programmable interface controller
• • G—PHYSICS
  • G06—COMPUTING OR CALCULATING; COUNTING
  • G06F—ELECTRIC DIGITAL DATA PROCESSING
  • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
  • G06F13/38—Information transfer, e.g. on bus
  • G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
  • G06F13/4204—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus
  • G06F13/4234—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being a memory bus
  • G06F13/4239—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being a memory bus with asynchronous protocol
• • G—PHYSICS
  • G05—CONTROLLING; REGULATING
  • G05B—CONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS
  • G05B2219/00—Program-control systems
  • G05B2219/30—Nc systems
  • G05B2219/33—Director till display
  • G05B2219/33182—Uart, serial datatransmission, modem

Definitions

• serial data transmitted from a first device such as a numerical control device is stored in a RAM provided in a second device such as a high-power control circuit of a machine tool for each bit in a predetermined manner.
• O pertains to a data transfer device that transfers data to a specified bit
• a serial transfer method is used for data transfer between distant devices in order to reduce transmission lines.
• the receiving device processes the received data with a microphone computer, it is necessary to convert the received serial data into parallel data and temporarily store it in RAM or the like. is there.
• RAM random access memory
• serial-parallel conversion is performed and stored in the RAM. Therefore, it is necessary to assign a specific meaning to each bit of the serial data.
• the receiving side will experience a delay in recognizing only the transmission time of the maximum parallel data bits. It will be a mistake.
• the present invention has improved the above-mentioned disadvantages of the prior art.] 3
• the purpose of the present invention is to achieve a serial transmitted from the first device.
• An object of the present invention is to provide a data transfer device capable of transferring data to a predetermined bit at a predetermined address of the HAM of the second device for each bit.
• the present invention achieves the above object by synchronizing each bit data of the serial data transmitted from the first device with each bit data from the first device.
• a data transfer device for transferring a packet to be transmitted to a predetermined bit of a predetermined address of a RAM provided in a second device for each packet to be transmitted, wherein the packet is counted by said packet.
• a counter to be loaded, an address generation circuit for generating an address of the RAM corresponding to the output of the counter, and an output corresponding to the output of the counter.
• a bit address generation circuit for generating a bit address for designating a bit position in one address of the RAM, and a counter output to the counter.
• the read cycle and the timing signal for the subsequent light cycle are sent to the above address.
• a timing control circuit that is generated during one address generation cycle of the generation circuit, and read from the RAM during a read cycle specified by the timing control circuit.
• the timing control circuit specifies the timing of the parallel data corresponding to the address of the address generator.
• the data at the bit position thus replaced is replaced with the bit data corresponding to the serial data sent from the first device, and the replaced parallel data is replaced with the time data.
• Light size specified by the lighting control circuit A read-modify-light circuit for transferring the data to the original address of the RAM during the clock.
• FIG. 1 is a block diagram of a main part of an embodiment of the present invention
• FIG. 2 is an explanatory diagram of a serial timing clock and transmission information transmitted from the first device
• FIG. FIGS. 4 and 5 are explanatory diagrams of the operation of the address generator 210, the bit address generator 211, and the timing control circuit 209.
• FIG. 5 is a diagram illustrating the operation of the first device.
• 6 is a timing chart for transferring the serial transmission data of the RAM 300 to the RAM 300.
• Fig. 6 is a timing chart for transferring the reception information of the RAM 300 to the first device. It is a chat.
• FIG. 1 is a block diagram of a main part of an embodiment of the present invention.
• 10 is a numerical control device specifically as shown in FIG. 1, 20 is a data transfer device according to the embodiment of the present invention, and 30 is a second device, specifically a high-power control device of a machine tool.
• 20 is a data transfer device according to the embodiment of the present invention
• 30 is a second device, specifically a high-power control device of a machine tool.
• a total of 100 types of transmission information is transferred from the first device to the transmission area of the RAM 300 of the second device 30 via the data transfer device 20.
• a total of 100 types of received information are transferred from the reception area of the RAM 300 to the first device 10 via the data transfer device 20.
• Each transmission information and reception information is on / off control information expressed by 1 bit.
• the first device 10 is a serial timing device. Send It has a terminal 100 for sending out, a terminal 101 for sending transmission information serially, and a terminal 102 for receiving serial / reception information.
• the first device 10 repeats the operation as shown in the timing chart of FIG. 2, for example, with the total number of pits of the transmission information and the reception information as one unit. Immediate Chi, terminal 100 or et single click ⁇ click C k in synchronization with the click ⁇ click each time delivering feed one terminal 101 or et. All the operations that leave send a signal information transmission information si After executing for ⁇ s 100, after sending 100 clocks for the received information, only the clock is sent from terminal 101 without sending the transmission information from terminal 101. The serial transmission of the transmission information synchronized with the clock C k is performed again. ⁇
• the data transfer device 20 has a clock input terminal 200, a data input terminal 201, and a data transmission terminal 202 connected to the first device 10 by transmission lines 103 to 105.
• Terminals 200 and 201 are connected to receivers 203 and 204, and terminal 202 is connected to driver 205.
• Output Les shea one server 203 is connected to the input of the bit Ryo Drain scan mosquito c te 20 6-and scan collected by filtration over strobe signal generation circuit 207.
• the bit address counter 206 is counted up at the output of the receiver 203, and the total number of bits of transmission information-and reception information ( 200 in the above example) ), The counter is set to the initial value, and the counter starts counting again.
• the strobe signal generation circuit 207 receives the output of the receiver 203 and receives one output of the RAM 300. During the cycle, two strobe signals are generated and output to the end circuit 208.
• the output of the bit address counter 206 is input to a timing control circuit 209, an address generation circuit 210, and a bit address generation circuit 211.
• the address generation circuit 210 generates an address of the RAM 300 in response to the output of the counter 206, and outputs the address of the RAM 300 and the address 213 * buffer 301.
• To the address input terminal of the RAM 300 via the The bit address generation circuit 211 is a bit position in the address specified by the address generation circuit 210 of the RAM 300 corresponding to the output of the counter 206.
• a bit address is generated to specify the address, and is output to the read-modify-light circuit 214 and the 8: 1 multiplexer 215.
• timing control circuit 209 may provide only a read cycle or a read cycle and a subsequent write cycle in response to the output of the counter 206.
• a timing signal for cycling is generated during one address generation cycle of the address generation circuit 210 described above, and the lead Z light control signal is supplied to the drive.
• a strobe signal is transmitted through driver 218, strobe line 219, and resistor 303 to R
• RAM 300 is a dual port type RAM,
• the buffer 301, the receiver * 302 ′ are accessed from the data transfer device 20 via the driver 303, the address bus 304, the read / write line 305.
• a strobe line 306, a micro computer power of a high-voltage control device (not shown) is also accessed via a data bus 309, and the RAM 300 is connected via the RAM 300.
• ON / OFF information is exchanged between the numerical controller and the machine-side high-current controller.
• the 8-bit data (transmission information or reception information) read from the RAM 300 is transmitted through the buffer 307, the data path 220, and the buffer 221.
• the signal is input to the circuit 215 and the latch circuit 222, and is input to the output carry-modify light circuit 214 of the latch circuit 222.
• the read-modify write circuit 214 is provided with the address generation circuit 21 read from the RAM 300 during the read cycle specified by the timing control circuit 209.
• the bit address generation the bit specified by the bit address of the circuit 211
• the position data is replaced with bit data from the receiver 204, and the replaced parallel data is replaced with a light cycle defined by the timing control circuit 209.
• the data is transferred to the original address of the RAM 300 via the buffer 223, the data bus 220, and the REF-T 308.
• the multiplexer 215 selects the bit specified by the bit end dress generation circuit 211 from among the 8-bit output of the buffer 221 and outputs the data. Liver 205 Send to.
• the transmission information si to slOO is transferred to each bit position of address 0 to 12 of the RAM 300 (transmission area), and the addresses 20 to 32 of the RAM 300 are transmitted.
• the reception information stored at each bit position in the reception area is transferred to the first device 10 as serial reception information ⁇ ⁇ 1 to ⁇ 00
• the transmission information and reception information correspond to the reception information.
• an address generation circuit 210, a bit end dress generation circuit 211, and a timing control circuit 209 are used in FIG. As shown, address, bit address, and lead Z light control signals are configured to be generated.
• the address generation circuit 210, the bit address generation circuit 211, and the timing control circuit 209 are connected to the bit address power counter 206.
• the output of the address is an address, and a ROM for outputting the above address, bit address, and read / write control signal is used.]? You can.
• FIG. 4 shows a case where an address generation circuit 210, a bit address generation circuit 211, and a timing control circuit 209 are configured by using two 8-bit ROMa and ROMb.
• An example of the setting of the stored information is shown below.
• ROMa, ⁇ de Re scan RAD0 ⁇ RAD7 of RAM 300 is taken into the serial 'in the lower 4 bits of ROMb (a () ⁇ a 3 ), bit to bit a 4 ⁇ a 6 of R OMa
• the address * DIPB0 to * DIPB2 is stored.
• the switching control signal A down de circuit 208 is stored in the bit a 4 in ROMB, re the bit a 5 — Stores the flash / light control signal.
• bi Tsu bets a 5 La wells control signal for example, "0" is stored, re-one de in the first half of the period in which one ⁇ Drain scan is generated in ⁇ Drain scan generator 21 0
• a few additional circuits are provided so that the control signal is sent to the driver 216 and the light control signal is sent out in the latter half.
• the bit a 5 Li one de control signal is stored, one ⁇ de-less that have been generated during the period Li one de control signal
• a de Re scan generator 210 is generated.
• ROMa bit a 7 of b Ru the Paris tee bit der.
• FIG. 5 is a timing chart when serial transmission data from the first device is transferred to RAM 300, and j ?, serial timing.
• a predetermined address is generated in the address generation circuit 210 for each clock, and the stall during the generation of the lead control signal generated by the timing control circuit 209 is generated.
• 8 bits of data corresponding to ⁇ de re scan to be stored in RAM 300 or et al me by the signal is read out and Shi Li a Le sent in Li one Domo de-off ⁇ Lee La I bet circuit 21 4
• the data replaced with the data is transferred to the original address of the RAM 300 by a strobe signal during the generation of the light control signal.
• Fig. 6 is a timing chart when transferring the received information of the RAM 300 to the first device.) And the generation of the read control signal generated by the timing control circuit. J9 according to the strobe signal in the RAM 300 specified by the address generator 210 Information of ⁇ Drain scan is read, the following c the predetermined bit between Le Chi flop Selector Selector support 215 is transferred to the first device 10 is selected, the operation of the second illustrated device .
• the transmission information should be stored in the RAM 300 according to the signal, and the information of the address of the RAM 300 should be stored in the buffer 307, data, ' ⁇ 220, and the buffer 221. Then, it is sent to the latch circuit 222 and the multiplexer 215.
• the read modify write circuit 214 replaces the bit corresponding to the bit address at the output of the latch circuit 222 with the transmission information of the receiver 204. Then, it is sent to the RAM 300 via the buffer 223, the data node 220, and the buffer 308.
• the data added to the RAM 300 is transmitted from the timing control circuit 209 to the light control signal RAM 300 and is generated by the strobe signal generation circuit 207. It is set to RAM 300 when the strobe signal is input to RAM 300.
• the serial timing is synchronized with the transmission information.
• the bit address counter 206 starts This transmission information is written to the next .bit position of the RAM 300 because it has been advanced.
• Data transfer station from the second device 20 to the first device 10 The transfer of constant transmission information has been completed, and the next serial timing is completed.
• the address generation circuit 210 When input to the counter 206, the address generation circuit 210 generates the first address of the reception area of the RAM 300, and the bit address generation circuit 211 generates the first bit. An address is generated, and the timing control circuit 209 generates a read control signal.
• the information of the first address of the reception area of the RAM 300 is stored in the buffer 307 and the data node. Is input to the multiplexer 215 via the bus 220 and the bus 221, and the multiplexer 215 selects 1-bit reception information corresponding to the bit address. Sent to driver 205. When the next serial timing clock is input, the bit address counter 206 is incremented, so that the next address of the first address of the RAM 300 is next. The second-bit reception information is transmitted to the first device 10 via the driver 205. When the transmission of the last received information is completed, the operation of 1 is performed again.
• the transmission information is sequentially stored from the head address of the RAM 300, and the reception information is sequentially read from the subsequent reception area.
• the address generation circuit 21 and this to be changed by rewriting the bit ⁇ de Re be generated circuit 21 1, Timing of control circuit 2 09-bit a de Re scan mosquito window down ROM an output corresponding to the data value This makes it possible to use any address bit of RAM as the transmission area and the reception area.], And the information arrangement of the RAM 300 differs. It can be easily applied to real data transfer.
• the operation of transmitting serial data from the first device to the RAM 300 ⁇ for each bit and the data in the reception area of the RAM 300 are performed. Is transferred to the first device 10 one bit at a time as serial data, but the latter can be omitted S if necessary.
• the present invention synchronizes each bit data of the serial data transmitted from the first device with each bit data and synchronizes the first data with the first bit data.
• a data transfer device for transferring, to a predetermined bit of a predetermined address in a RAM provided in a second device for each clock transmitted from the device, wherein the clock is used for the data transfer.
• a counter to be counted up, an address generation circuit for generating an address of the RAM in response to an output of the counter, and a counter for the counter.
• a bit address generation circuit that generates a reset end address, and a read cycle corresponding to the output of the counter and a write cycle following the bit cycle
• a timing control circuit for generating the timing signal of the address generation circuit during one address generation cycle of the address generation circuit; and a reset circuit defined by the timing control circuit.
• the transmitted serial data can be transferred for each bit to a predetermined bit of a predetermined address of the RAM of the second device. Therefore, since the contents of the RAM are updated every bit of the serial transmission data, the second device that identifies the contents of the transmission information by reading the RAM contents promptly transmits the transmission information. It is possible to identify In particular, by using ROM for the address generation circuit, bit address generation circuit, and timing control circuit, the circuit can be simplified, and reading and writing can be performed. The advantage is that the address and bit of RAM can be easily changed. is there.

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• Engineering & Computer Science (AREA)
• Theoretical Computer Science (AREA)
• Physics & Mathematics (AREA)
• General Physics & Mathematics (AREA)
• General Engineering & Computer Science (AREA)
• Human Computer Interaction (AREA)
• Manufacturing & Machinery (AREA)
• Automation & Control Theory (AREA)
• Communication Control (AREA)
• Memory System (AREA)

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Citations (5)

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• 1984
  • 1984-05-16 JP JP59098093A patent/JPS60241150A/ja active Pending
• 1985
  • 1985-05-15 WO PCT/JP1985/000267 patent/WO1985005471A1/ja active IP Right Grant
  • 1985-05-15 EP EP85902632A patent/EP0185093B1/en not_active Expired - Lifetime
  • 1985-05-15 DE DE8585902632T patent/DE3581901D1/de not_active Expired - Lifetime
  • 1985-05-15 US US06/822,422 patent/US4682167A/en not_active Expired - Fee Related

Patent Citations (5)

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