JPS5771004A - Input and output control system - Google Patents

Input and output control system

Info

Publication number
JPS5771004A
JPS5771004A JP14790980A JP14790980A JPS5771004A JP S5771004 A JPS5771004 A JP S5771004A JP 14790980 A JP14790980 A JP 14790980A JP 14790980 A JP14790980 A JP 14790980A JP S5771004 A JPS5771004 A JP S5771004A
Authority
JP
Japan
Prior art keywords
data
input
reception
transmission
output
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP14790980A
Other languages
Japanese (ja)
Other versions
JPS6058482B2 (en
Inventor
Masashi Tominaga
Munehiro Minami
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Tokyo Shibaura Electric Co Ltd filed Critical Toshiba Corp
Priority to JP14790980A priority Critical patent/JPS6058482B2/en
Publication of JPS5771004A publication Critical patent/JPS5771004A/en
Publication of JPS6058482B2 publication Critical patent/JPS6058482B2/en
Expired legal-status Critical Current

Links

Classifications

    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38Information transfer, e.g. on bus
    • G06F13/42Bus transfer protocol, e.g. handshake; Synchronisation
    • G06F13/4204Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus
    • G06F13/4208Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being a system bus, e.g. VME bus, Futurebus, Multibus

Abstract

PURPOSE:To transmit and receive accurate series data by providing a buffer register BR between a shift register SR and a bus and controlling the transmission and reception of the SR according to the presence of data in the BR. CONSTITUTION:A series data input and output equipment S-I/O consists of an SR11 transmitting and receiving input and output data to and from an external equipment, a BR12 wherein those data are held temporarily, and a bus 13 connecting the input and output data to a CPU. Then, shift pulses phis to the SR11 are controlled by a reception mode FF21 inindicating the transmission and reception modes of the S-I/O and an FF22 controlling the transfer of data on the basis of the presence of data in the BR12, thereby preventing necessary data from being erased. When the final data is transferred to the BR12 of SR11, an enable series data input and output FF14 operating the S-I/O is reset through the operation of an auxiliary FF15 to prevent the transmission and reception of unnecessary data, performing the transmission and reception of accurate series data.
JP14790980A 1980-10-22 1980-10-22 Input/output control method Expired JPS6058482B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP14790980A JPS6058482B2 (en) 1980-10-22 1980-10-22 Input/output control method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP14790980A JPS6058482B2 (en) 1980-10-22 1980-10-22 Input/output control method

Publications (2)

Publication Number Publication Date
JPS5771004A true JPS5771004A (en) 1982-05-01
JPS6058482B2 JPS6058482B2 (en) 1985-12-20

Family

ID=15440853

Family Applications (1)

Application Number Title Priority Date Filing Date
JP14790980A Expired JPS6058482B2 (en) 1980-10-22 1980-10-22 Input/output control method

Country Status (1)

Country Link
JP (1) JPS6058482B2 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1985005471A1 (en) * 1984-05-16 1985-12-05 Fanuc Ltd Data transfer equipment

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1985005471A1 (en) * 1984-05-16 1985-12-05 Fanuc Ltd Data transfer equipment
US4682167A (en) * 1984-05-16 1987-07-21 Fanuc Ltd Data transfer system for numerically controlled equipment

Also Published As

Publication number Publication date
JPS6058482B2 (en) 1985-12-20

Similar Documents

Publication Publication Date Title
JPS5771004A (en) Input and output control system
JPS5499886A (en) Sequence controller
JPS578828A (en) Communication system between computer systems
JPS5583917A (en) Two-way data transfer system between plural units
JPS56105504A (en) Control device
JPS57141741A (en) Input and output control system
JPS55147851A (en) Communication controlling system
JPS573126A (en) Input and output controlling system
JPS57199357A (en) Data transmission controller
JPS5619251A (en) Data transmission/reception control system
JPS57212519A (en) Programmable controller
JPS57153328A (en) Terminal device with keying data pushup storage function
JPS5765041A (en) Data transmssion control system
JPS5654509A (en) Sequence controller
JPS575141A (en) Bus control system
JPS56763A (en) Line connector
JPS57174726A (en) Data transfer controlling system
JPS57178533A (en) Data transmission controlling interface with memory
JPS5785125A (en) Information processor
JPS5643850A (en) Intermultiplexer communication control system
JPS6468156A (en) Data transfer system
EP0108413A3 (en) Method for the control of data transfer between a data transmitter and a data receiver on a bus, using a control unit which is connected to the bus
JPS57150017A (en) Direct memory access system
JPS62239741A (en) Addition system for device control code
JPS57157326A (en) Input and output system