JPS5771004A - Input and output control system - Google Patents
Input and output control systemInfo
- Publication number
- JPS5771004A JPS5771004A JP14790980A JP14790980A JPS5771004A JP S5771004 A JPS5771004 A JP S5771004A JP 14790980 A JP14790980 A JP 14790980A JP 14790980 A JP14790980 A JP 14790980A JP S5771004 A JPS5771004 A JP S5771004A
- Authority
- JP
- Japan
- Prior art keywords
- data
- input
- reception
- transmission
- output
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
- G06F13/4204—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus
- G06F13/4208—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being a system bus, e.g. VME bus, Futurebus, Multibus
Abstract
PURPOSE:To transmit and receive accurate series data by providing a buffer register BR between a shift register SR and a bus and controlling the transmission and reception of the SR according to the presence of data in the BR. CONSTITUTION:A series data input and output equipment S-I/O consists of an SR11 transmitting and receiving input and output data to and from an external equipment, a BR12 wherein those data are held temporarily, and a bus 13 connecting the input and output data to a CPU. Then, shift pulses phis to the SR11 are controlled by a reception mode FF21 inindicating the transmission and reception modes of the S-I/O and an FF22 controlling the transfer of data on the basis of the presence of data in the BR12, thereby preventing necessary data from being erased. When the final data is transferred to the BR12 of SR11, an enable series data input and output FF14 operating the S-I/O is reset through the operation of an auxiliary FF15 to prevent the transmission and reception of unnecessary data, performing the transmission and reception of accurate series data.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP14790980A JPS6058482B2 (en) | 1980-10-22 | 1980-10-22 | Input/output control method |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP14790980A JPS6058482B2 (en) | 1980-10-22 | 1980-10-22 | Input/output control method |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS5771004A true JPS5771004A (en) | 1982-05-01 |
JPS6058482B2 JPS6058482B2 (en) | 1985-12-20 |
Family
ID=15440853
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP14790980A Expired JPS6058482B2 (en) | 1980-10-22 | 1980-10-22 | Input/output control method |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS6058482B2 (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO1985005471A1 (en) * | 1984-05-16 | 1985-12-05 | Fanuc Ltd | Data transfer equipment |
-
1980
- 1980-10-22 JP JP14790980A patent/JPS6058482B2/en not_active Expired
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO1985005471A1 (en) * | 1984-05-16 | 1985-12-05 | Fanuc Ltd | Data transfer equipment |
US4682167A (en) * | 1984-05-16 | 1987-07-21 | Fanuc Ltd | Data transfer system for numerically controlled equipment |
Also Published As
Publication number | Publication date |
---|---|
JPS6058482B2 (en) | 1985-12-20 |
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