WO1985000460A1 - Circuit de memoire par quartets ayant un circuit de redondance de colonnes - Google Patents

Circuit de memoire par quartets ayant un circuit de redondance de colonnes Download PDF

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Publication number
WO1985000460A1
WO1985000460A1 PCT/US1984/000757 US8400757W WO8500460A1 WO 1985000460 A1 WO1985000460 A1 WO 1985000460A1 US 8400757 W US8400757 W US 8400757W WO 8500460 A1 WO8500460 A1 WO 8500460A1
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WO
WIPO (PCT)
Prior art keywords
data
data line
column
gate
bit segment
Prior art date
Application number
PCT/US1984/000757
Other languages
English (en)
Inventor
Elvan S. Young
Steven J. Schumann
Original Assignee
Advanced Micro Devices, Inc.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Advanced Micro Devices, Inc. filed Critical Advanced Micro Devices, Inc.
Publication of WO1985000460A1 publication Critical patent/WO1985000460A1/fr

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Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/70—Masking faults in memories by using spares or by reconfiguring
    • G11C29/78—Masking faults in memories by using spares or by reconfiguring using programmable devices
    • G11C29/84—Masking faults in memories by using spares or by reconfiguring using programmable devices with improved access time or stability
    • G11C29/846—Masking faults in memories by using spares or by reconfiguring using programmable devices with improved access time or stability by choosing redundant lines at an output stage

Definitions

  • the present invention relates generally to apparatus for accessing data and, more particularly, to a byte wide memory circuit having a column redundancy circuit or scheme.
  • the memory circuit includes a main memory array for storing the data and circuitry for accessing the stored data.
  • the main memory array for example, a static random access memory (SRAM), generally includes a number of bit segments, each having a plurality of addressable columns for storing the data.
  • SRAM static random access memory
  • OMPI in the main memory array includes, for each bit segment, a column address decoder which receives and decodes column addresses to activate the corresponding columns.
  • the memory circuit can be manufactured, for example, as an integrated circuit (IC) on a semiconductor chip.
  • one or more defects can occur which cause one or more columns in the bit segments to be unusable for storing the data.
  • one defect can constitute two columns in a bit segment being shorted together, thereby making both columns defective. Consequently, the memory circuit typically is manufactured with redundant columns which can be used to replace defective columns, together with programmable redundant column address decoders which are programmed to decode addresses to the defective columns.
  • the redundant column address decoder programmed with that address responds by activating the corresponding redundant column to replace the defective column.
  • One particular byte wide memory circuit having a column redundancy scheme is known as a four-bit byte wide memory circuit.
  • the architecture of this memory circuit includes four bit segments, four input/output (I/O) ports and four data lines which couple the bit segments to the I/O ports, respectively.
  • This memory circuit has symmetrical left and right half planes, with each half plane including two bit segments, two data lines and two I/O ports. Each half plane also has four redundant columns arranged in two pairs of
  • OMPI redundant columns to replace defective columns in the two bit segments, thereby providing a ratio of four redundant columns per two I/O ports.
  • Two redundant columns of one pair are coupled, respectively, to the two data lines and two redundant columns of the other pair are also coupled, respectively, to the two data lines.
  • the two redundant columns of a pair are activated as a pair when addressing a defective column in a bit segment.
  • the two pairs of redundant columns are used to replace different combinations of defective columns in the bit segments. For example, if two columns in one bit segment coupled to one data line are shorted together, then one pair of redundant columns is activated when one of these defective columns is addressed and the other pair of redundant columns is activated when the other defective column is addressed. That is, the one redundant column of one pair connected to the one data line and the one redundant column of the other pair connected to the one data line are used to replace, respectively, the shorted columns in the one bit segment.
  • Another disadvantage or inefficiency is that if, for example, and as another manufacturing defect, only one column in the two bit segments of a given half plane is distinctly defective, then still two pairs or four redundant columns are provided, with only one redundant column actually being used for the replacement of the one defective column.
  • Other disadvantages include the increased manufacturing costs and complexity that are associated with requiring these numbers of redundant columns relative to the numbers of I/O ports, and the additional space that is needed on the semiconductor chip to provide these redundant columns.
  • OMPI invention to provide a byte wide memory circuit having a more efficient column redundancy scheme.
  • Yet another object of the present invention is to simplify, and reduce the costs of, manufacturing a byte wide memory circuit having a column redundancy scheme.
  • the apparatus of the invention can comprise a plurality of memory means for storing data, a plurality of data lines corresponding, respectively, to the plurality of memory means, a plurality of port means coupled, respectively, to the plurality of data lines, a plurality of redundant means for storing data and corresponding, respectively, to the plurality of port means, and means for coupling, respectively, the plurality of redundant means to one or another of the plurality of data lines while decoupling one or another of the plurality of memory means from one or another of the plurality of data lines.
  • each of the redundant means is a redundant column and the means for coupling and decoupling is programmable to couple or switch a given redundant column to one or the other data line.
  • a given redundant column can be coupled or switched to the one or another data line by programming the programmable coupling and decoupling means.
  • the programmable coupling and decoupling means includes, for a given redundant column, a programmable address decoder that is programmed to decode an address to a defective column, a pair of pass gates for coupling the given redundant column to one and the other data lines, respectively, and a programmable multiplexer which is programmed to select and switch a gate enabling signal produced by the programmed address decoder to one of these two pass gates, thereby, for example, gating data stored in the redundant column onto one of the data lines. Simultaneously, the programmed coupling and decoupling means effectively decouples the bit segment having the defective column replaced by the given redundant column from the corresponding data line.
  • the present invention in which a given redundant column can be coupled or switched to one of two data lines, only one redundant column per I/O port is needed for replacing the same defective columns as with prior column redundancy schemes. Furthermore, as a result of this flexibility in the coupling of a given redundant column to one or the other data line, the present invention also provides only two redundant columns, with only one of these redundant columns being necessary to replace a distinctly defective column. Also, by being able to couple two redundant columns of the present invention to the same one of two data lines and, hence, a corresponding I/O port, the column redundancy scheme of the present invention advantageously effectuates a two redundant column per I/O data transfer for byte wide memory circuits. Consequently, more efficient redundant column usage and reduced costs and simplicity of manufacturing are achieved with the present invention, while providing the ability to replace the same defective columns as prior column redundancy schemes.
  • FIG. 1 is a simplified block diagram of the present invention
  • Fig. 2 is a more detailed block diagram of the present invention.
  • Fig. 3 is a partial schematic illustration of the present invention.
  • Fig. 1 illustrates an apparatus 10 for accessing data and, in particular, a byte wide memory circuit 12.
  • the byte wide memory circuit 12 can be a 4-bit byte wide memory circuit, although the principles of the present invention can be applied to other types of byte wide memory circuits.
  • the memory circuit 12 can constitute other types of circuit implementation..
  • the memory circuit 12 has a left-hand portion or plane 12A, shown in detail, and a symmetrical or similar right-hand portion or plane 12B shown only generally in one block.
  • the discussion of left-hand plane 12A will be sufficient for an understanding of the right-hand plane 12B and the overall principles of the present invention.
  • the memory circuit plane 12A has a main memory array 14A divided into a plurality of memory means shown generally at 16A for storing data.
  • memory means I ⁇ A includes a bit segment BS, having a plurality of addressable data storage columns shown generally at 18 and an address decoder AD, for decoding column addresses to access the respective columns 18.
  • Memory means 16A includes another bit segment BS 2 which has a plurality of addressable data storage columns shown generally at 20 and an address decoder AD_ for decoding column addresses to access the respective columns 20.
  • Address decoder AD' and address decoder AD_ receive the addresses to the columns 18 and columns 20 over control lines shown generally at 22.
  • bit segment BS can have 32 columns 18 and bit segment BS r, can have 32 columns 20 , whereby address decoder AD, and address decoder AD- will decode 5-bit addresses on lines 22.
  • a plurality of data lines of memory circuit plane 12A, shown generally at DL, is coupled to the plurality of memory means 16A, respectively, to conduct or transfer the data that can be stored in memory means 16A.
  • the data lines DL include a data line DL, that is coupled to the bit segment BS, and a data line DL 2 that is coupled to the bit segment BS formulate.
  • the memory circuit plane 12A also includes a plurality of port means shown generally at PM, which is coupled to the plurality of data lines DL, respectively.
  • the port means PM includes a port means PM, that is coupled to the data line DL, and a port means PM linen that is coupled to the data line DL 2 .
  • a given column address is supplied on lines 22 and received by address decoder AD, and address decoder AD 2 .
  • This column address is then decoded by address decoder AD, and address decoder AD-, wnereby one of the columns 18 and one of the columns 20, respectively, is accessed.
  • a data transfer can be made between the port means PM, and the one addressed column 18 over the data line DL, , and between the port means PM 2 and the one addressed column 20 over the data line DL-.
  • a number of defects can occur during the course of manufacturing the bit segment BS, and the bit segment BS remedy that can cause one or more of the columns 18 and columns 20 to be unusable for data storage purposes.
  • a column 18, and a column 13- -in bit segment BS can be shorted, thereby making both of these columns defective for storing data, or a column 20, and a column 20_ in bit segment BS- can be shorted, thereby making these two columns defective for storing data.
  • Another manufacturing defect can have two separate columns being unusable, such as a column 18.. in bit segment BS, and a column 20-. in bit segment BS_ being distinctly defective.
  • Memory circuit plane 12A has a plurality of redundant means shown generally at 26A for replacing one or more defective columns 18 in bit segment BS, and/or one or more defective columns 20 in bit segment BS 2 «
  • redundant means 26A has a plurality of redundant columns shown generally at RC corresponding in number, respectively, to the plurality of port means PM.
  • the plurality of redundant columns RC includes a redundant column RC, for replacing a defective column 18 in bit segment BS. or a defective column 20 in bit segment BS- and a redundant column RC 2 for replacing a defective column 18 in bit segment BS, or a defective column 20 in bit segment BS 2 »
  • These two redundant columns RC, and RC 2 correspond in number to the number of port means PM, i.e., to the port means PM, and port means PM-.
  • the architecture of the memory circuit plane 12A is such that there is a like number, of bit segments BS, and BS-, data lines DL, and DL 2 , port mmee,ans PM, and PM- and redundant columns RC, and
  • Memory circuit plane 12A also includes means 28 for coupling, respectively, the plurality of redundant columns RC to one or another of the plurality of data lines DL while simultaneously effectively decoupling one of the plurality of memory means 16A from one or the other of the data lines DL.
  • means 28 includes a control circuit 29 which, as will be further described, is programmable to respond to column addresses on lines 22 to defective columns.
  • Means 28 also includes a switch means 30, controlled by control circuit 29, for connecting redundant column RC, to the data line DL, over a line 32 or to the data line DL- over a line 34.
  • Means 28 further includes a switch means 36 for simultaneously effectively decoupling bit segment BS, from the data line DL, if redundant column RC, is coupled to data line DL, , and a switch means 38 for simultaneously effectively decoupling bit segment BS 2 from the data line DL 2 if redundant column RC,
  • OMPI IO is coupled to data line DL 2 - Switch means 36 and switch means 38 are also controlled by control circuit 29.
  • means 28 includes a switch means 40, controlled by control circuit 29, for connecting redundant column RC- to the data line DL, over a line 42 or to the data line DL 2 over a line 44. Simultaneously, means 28 will effectively decouple, via the switch means 36, bit segment BS, from the data line DL, if redundant column RC- is coupled to data line DL, .or, via the switch means 38, bit segment BS- from the data line DL 2 if redundant column RC- is coupled to data line DL 2 .
  • redundant column RC can be switched to data line DL, or data line DL_, while bit segment BS, is effectively decoupled from data line DL, or bit segment BS- is effectively decoupled from data line DL 2 , respectively.
  • redundant column RC- can be sv/itched to data line DL, or data line DL 2 , while bit segment BS, is effectively decoupled from data line DL, or bit segment BS 2 is effectively decoupled from data line DL 2 , respectively.
  • redundant column RC, and redundant column RC 2 are used to store the same data that otherwise would be stored by defective column 18, and defective column 18.,. Since bit segment BS, and, therefore, defective column 18, and defective column 18-, communicate with port means PM, only by the data line DL, , the means 28 will be programmed to couple redundant column RC, to the data line DL, via the line 32 and redundant column RC- to the data line DL, via the line 42 whenever column addresses on lines 22 are received to access defective column 18, and defective column 18-. Simultaneously, means 28 will respond to the column addresses on lines 22 to defective column 18, and defective column 18- by effectively decoupling bit segment BS, from the data line DL,.
  • means 28 when the column address on lines 22 to defective column 18, is received, means 28 responds by coupling redundant column RC, to data line DL, via line 32. Simultaneously, means 28 will respond by effectively decoupling the bit segment BS, from the data line DL, via switch means 36. Therefore, though address decoder AD, will also decode the address on lines 22 to access defective column 18,, the means 28 will enable a data transfer between redundant column RC, and port means PM, over data line DL, while disabling a data transfer between bit segment BS, and port means PM, over data line DL,.
  • means 28 when the column address is received on lines 22 to access defective column 18-, means 28 responds by coupling redundant column RC- to data line DL, via line 42. Simultaneously, means 28 effectively decouples the bit segment BS, from the data line DL, via switch means 36. Thus, though address decoder AD, will also decode the address on lines 22 to access defective column 18-, the means 28 will enable a data transfer between redundant column RC container and port means PM, over data line DL, while disabling a data transfer between bit segment BS, and port means PM, over data line DL 1 .
  • means 28 decouples redundant column RC, and redundant column RC- from data line DL, via line 32 and line 42, respectively, and enables the coupling of the bit segment BS, to data line DL,- via switch means 36.
  • a data transfer can occur between the non-defective columns 18 of bit segment BS, and port means PM, via data line DL,.
  • RC- are now used to replace defective column 20, and defective column 20-. Since bit segment BS- and, hence, defective column 20, and defective column 20-, communicate with port means PM- via data line DL 2 , the means 28 will couple redundant column RC, and redundant column RC- to data line DL 2 via respective line 34 and line 44 in response to the column addresses on lines 22 to defective column 20, and defective column 20-, respectively. Simultaneously, means 28 will respond to these column addresses on lines 22 to defective column 20, and defective column 20 2 by effectively decoupling bit segment BS- from data line DL_ via switch means 38.
  • means 28 in response to the column address to defective column 20, on lines 22, means 28 will couple redundant column RC, to data line DL 2 via line 34 and effectively decouple, via switch means 38, the bit segment BS- from data line DL 2 . Therefore, though address decoder AD- will also decode the address on lines 22 to access defective column 20,, the means 28 will enable a data transfer between redundant column RC, and port means PM 2 over data line DL 2 while disabling a data transfer between bit segment BS 2 and port means PM- over data line DL 2 .
  • means 28 will respond by coupling redundant column RC- to data line DL_ via line 44. Simultaneously, means 28 will effectively decouple bit segment BS 2 from data line DL- via switch means 38. Thus, though address decoder AD- will also decode the address on lines 22 to- access defective column 20 2 , the means
  • 28- will enable a data transfer between redundant column RC- and port means PM 2 over data line DL 2 while disabling a data transfer between bit segment BS- and port means PM- over data line DL-.
  • means 28 decouples redundant column RC, and redundant column RC 2 from data line DL-, respectively, and enables the coupling of bit segment BS 2 to data line DL 2 via switch means 38. Therefore, the non-defective columns 20 can communicate with the port means PM via data line DL 2 for data transfer purposes.
  • Defective Column Condition No. 3 Assume now that, as manufactured, only column 18- in bit segment BS, and column 20 ⁇ in bit segment BS- are defective. Consequently, redundant column RC, can be used to replace defective column 18- and redundant column RC- can be used to replace defective column 20.,. Since bit segment BS, and, hence, defective column 18-, communicate with port means PM, via data line DL,, redundant column RC, will be coupled by means 28 to data line DL, in the manner previously described whenever the column address to defective column 18- is on lines 22.
  • redundant column RC 2 will be coupled by means 28 to data line DL_ in the manner previously described whenever the column address to defective column 20-, is on lines 22.
  • means 28 effectively decouples bit segment BS, from data line DL, as previously described.
  • means 28 effectively decouples bit segment BS 2 from data line DL 2 as described above.
  • data transfers can occur between port means PM, and redundant column RC, via data line DL, whenever the column address to defective column 18- is produced on lines 22, or data transfers can occur between port means PM_ and redundant column RC 2 via data line DL 2 whenever the column address to defective column 20_ is produced on lines 22.
  • means 28 decouples redundant column RC, from data line DL, and enables the coupling of bit segment BS, to data line DL,, so that the non-defective column 18 can communicate with port means PM, via data line DL, .
  • means 28 decouples redundant column RC- from data line DL 2 and enables the coupling of bit segment BS- to data line DL_ , so that the non- defective column 20 can communicate with port means PM_ via data line DL 2 .
  • Defective Column Condition No. 4 Assume now that, as manufactured, only column 18. is defective. Under this condition, one of the redundant columns, e.g., redundant column RC, , can be used to replace the defective column
  • the means 28 responds by coupling redundant column RC, to data line DL, while effectively decoupling the bit segment BS, from data line DL, , as mentioned above.
  • the means 28 responds by decoupling redundant column RC, from data line DL, and coupling bit segment BS, to data line DL, as mentioned above.
  • redundant column RC only one redundant column, e.g., redundant column RC, is utilized and only coupled to data line DL,. Redundant column RC- is not used at all and always is decoupled from data line DL, and data line DL 2 . However, in the manner previously described, redundant column RC- is available for use should another column 18 or a column 20 be defective.
  • the memory circuit plane 12B is similar to memory circuit plane 12A and need not be disclosed in the same detail. Circuit plane 12B will have a comparable plurality of means 16A and a comparable redundant column circuit 26A.
  • Circuit plane 12B also will have two additional data lines DL (not shown) similar to data lines DL, and data lines DL-, as well as two additional port means PM (not shown) similar to port means PM, and port means PM-, respectively.
  • the manner in which the circuit plane 12B operates is identical- to the above-described operation of circuit plane 12A.
  • the present invention can provide one redundant column RC per one port means PM.
  • the two redundant columns RC, and RC 2 can be switched to the same data line, e.g. , data line DL, , thereby effecting a two redundant column per port means data transfer.
  • This architecture has the advantages previously mentioned, such as the efficient usage of redundant columns.
  • Fig. 2 shows in more detail the memory circuit plane 12A of Fig. 1, and, in particular, the port means PM and the means 28.
  • Fig. 2 shows in a similar manner as Fig. 1 the memory storing means 16A having the bit segment BS, , the address decoder AD, and the data line DL, , and the bit segment BS 2 , the address decoder AD 2 , and the data line DL 2 , together with the lines 22 carrying the column addresses.
  • Fig. 2 also shows the redundant column RC, and the redundant column RC-.
  • the port means PM includes a sense amplifier SA, which is coupled to data line DL, and an input/output port I/O, coupled to the sense
  • the port means PM- includes a sense amplifier SA- which is coupled to the data line DL 2 and an input/output port I/O., coupled to the sense amplifier SA_.
  • the sense amplifier SA, and sense amplifier SA- will amplify and output data on data line DL and data line DL 2 to port I/O, and port I/O-, respectively. While not shown, two data input buffers would be used to buffer and output data received from port I/O, and port I/O- onto data line DL, and data line DL-, respectively.
  • the means 28 includes programmable means shown generally at 46, responsive to defective column addresses on lines 22, for enabling a data transfer between the redundant column RC, and data line DL, via line 32 or between redundant column
  • overall programmable means 46 is a part - of control circuit 29,and also includes the switch means 30.
  • a programmable address decoder means 48 of programmable means 46 when programmed, as will be described below, is responsive to a column address on lines 22 for producing a gate enabling signal on a line 52 or a gate enabling signal on a line 54.
  • a pass gate 56 of switch means 30 is enabled by the gate enabling signal on line 52 to couple data between the redundant column RC, and the data line DL, via line 32.
  • a pass gate 58 of switch means 30 is responsive to the gate enabling signal on line 54 to couple data between the redundant column RC, and the data line DL- via line 34.
  • the programmable address decoder means 48 includes a programmable redundant address decoder 60 that can be programmed to decode any one address to any column in bit segment BS, or bit segment BS-.
  • the programmable redundant address decoder means 48 also includes a programmable multiplexer 62 having a programmable circuit 64 with one input coupled to the output of the decoder 60 over a line 66 and an output coupled to the line 52, as well as another programmable circuit 68 having one input coupled to the output of decoder 60 over the line 66 and an output coupled to the line 54.
  • redundant address decoder 60 will be programmed to decode one column address to a defective column in bit segment BS, or bit segment BS 2 .
  • either circuit 64 or circuit 68 will be programmed to select and switch the output of decoder 60 on line 66 to line 52 or line 54, respectively.
  • the programming of either circuit 64 or circuit 68 will depend on the data line DL, or data line DL- to which the redundant column RC, should be coupled.
  • redundant address decoder 60 has been programmed to decode an address to a defective column in bit segment BS, which, as- previously described, communicates with the data line DL,. Consequently, only circuit 64 will be programmed to select and switch the output of decoder 60 on line 66 to line 52 to provide the gate enabling signal.
  • decoder 60 will decode this address and produce an output signal, e.g., logic 1, on line 66.
  • Multiplexer circuit 62 then. will couple this signal onto line 52 to enable the gate 56, whereby, for example, the data stored in redundant column RC, will be coupled through gate 56 and line 32 onto data line DL,.
  • redundant address decoder 60 has been programmed to decode a column address to a defective column in bit segment BS 2 .
  • bit segment BS- communicates with data line DL-. Consequently, only circuit 68 will be programmed to couple line 66 to line 54. Therefore, when the address to this defective column is received on lines 22, redundant address decoder 60.produces a signal, e.g., logic 1, on line 66 that is selected and switched by circuit 68 onto line 54.
  • pass gate 58 is enabled to, for example, gate the data stored in redundant column RC, onto line 34 and, hence, data line DL-.
  • Programmable means 46 also includes a NOR gate 70 having one input coupled to the line 52 carrying the gate enabling signal and an output coupled over a line 72 to a pass gate 74 of switch means 36.
  • pass gate 74 couples data on data line DL, between the bit segment BS, and sense amplifier SA,.
  • pass gate 74 effectively decouples or inhibits data flow between the bit segment BS, and the sense amplifier SA, .
  • programmable means 46 includes a NOR gate 75 having one input coupled to the line 54 and an output coupled over a line 76 to a pass gate 78 of switch means 38.
  • pass gate 78 gates data on data line DL 2 between the bit segment BS- and the sense amplifier SA_.
  • pass gate 78 effectively decouples or inhibits data ffllooww bbeettwweeeenn tthe bit segment BS- and the sense amplifier SA 2 .
  • NOR gate 70 responds by producing a logic 0 on line 72 to disable pass gate 74.
  • NOR gate 70 may produce a logic 1 on line 72 to enable pass gate 74, depending on the other input to gate 70, as will be further described.
  • NOR gate 75 will produce a logic 0 on line 76 to disable pass gate 78.
  • the NOR gate 75 may produce a logic 1 on line 76 to disable pass gate 78, depending on the other input to gate 75, as will be further described.
  • redundant address decoder means 48 has been programmed to decode a defective column in bit segment BS,. Accordingly, when the address on lines 22 to this defective column is received by address decoder means 48, the logic 1 gate enabling signal on line 52 will be produced to enable gate 56, whereby redundant column RC, will, for example, output its data onto data line DL, via pass gate 56 and line 32. Simultaneously, the logic 1 gate enabling signal on line 52 will be inverted by NOR gate 70, which will produce a logic 0 on line 72 to disable pass gate 74. Consequently, the bit segment BS, , and in particular the defective column that is currently being addressed by address decoder AD, , is effectively decoupled from the data line DL,. -23-
  • address decoder means 48 has been programmed to decode a defective column in bit segment BS-. Consequently, when the address to that defective column is produced on lines 22, address decoder means 48 will produce the logic 1 gate enabling signal on line 54, whereby gate 58 will be enabled, for example, to couple data from the redundant column RC, onto the data line DL-. Simultaneously, NOR gate 75 will respond to the logic 1 on line 54 by outputting a logic 0 on line 76 to disable the pass gate 78. Accordingly, bit segment BS 2 and, in particular, the defective column currently being addressed by address decoder AD- , is effectively decoupled from the data line DL 2 .
  • Means 28 also has a programmable means shown generally at 80 for enabling a data transfer between the redundant column RC 2 and the data line DL, via line 42 or between the redundant column RC- and the data line DL 2 via line 44, respectively.
  • overall programmable means 80 is a part of control circuit 29 and also includes switch means 40.
  • a programmable redundant address decoder means 82 of programmable means 80 when programmed, produces a gate enabling signal on an output line 84 or a gate enabling signal on an output line 86 in response to a column address on lines 22.
  • a pass gate 88 of switch means 40 in response to the gate enabling signal on line 84, couples or gates data between the redundant column RC 2 and the data line DL, via line 42.
  • a pass gate 90 of switch means 40 in response to the gate enabling signal on line 86, couples or gates data between the redundant column RC 2 and the data line
  • the programmable redundant address decoder means 82 includes a programmable decoder 92 that can be programmed to respond to an address to any one of the columns in bit segment BS, or bit segment BS-.
  • a programmable multiplexer 94 includes a programmable circuit 96 having an input coupled to the output of decoder 92 over a line 98 and an output coupled to the line 84.
  • a programmable circuit 100 of multiplexer 94 has an input coupled to the line 98 and an output coupled to the line 86.
  • redundant column RC 2 is to replace a defective column in bit segment BS, which, as previously mentioned, communicates only with the data line DL, .
  • address decoder 92 is programmed to decode the column address on lines 22 to the defective column in bit segment.BS,.
  • programmable circuit 96 is programmed to couple line 98 to line 84. Therefore, whenever, the column address to this defective column is produced on lines 22, address decoder 92 responds by producing an output signal on line 98, e.g., logic 1, that is selected and switched by circuit 96 onto line 84 as the gate enabling signal.
  • pass gate 88 is enabled to couple the redundant column RC- to data line DL, via line 42.
  • the logic 1 gate enabling signal on line 84 is provided as the other input to NOR gate 70, whose output then goes to a logic 0 on line 72 to disable pass gate 74. Consequently, bit segment BS, and, in particular the defective
  • OMPI colu n is effectively decoupled from data line DL ⁇ .
  • address decoder 92 is programmed to decode the column • address on lines 22 to the defective column in bit segment BS-. And, therefore, programmable circuit 100 is programmed to couple line 98 to line 86.
  • address decoder 92 responds by producing a logic 1 output signal on line 98 that is selected and switched by circuit 100 onto line 86 as the gate enabling signal.
  • the pass gate 90 then is enabled to couple the redundant column RC- to data line DL- via line 44.
  • address decoder 60 and address decoder 92 output a logic 0 on line 66 and line 98, respectively.
  • line 52, line 54, line 84 and line 86 are at logic 0 to disable pass gate 56, pass gate 58, pass gate 88 and pass gate 90, respectively, whereby redundant column RC, and redundant column RC_ are decoupled from data line DL, and data line DL 2 ⁇
  • NOR gate 70 and NOR gate 75 will respond by producing a logic 1 on line 72 and on line 76, respectively, whereby pass gate 74 and pass gate 78 are enabled. Accordingly, bit segment BS, and bit segment BS 2 , and in particular, the non-defective columns, are effectively coupled to the data line DL, and data line DL-, respectively.
  • Fig. 3 shows a partial schematic of several of the components described in connection with Fig. 2.
  • Fig. 3 illustrates schematically the programmable circuit 64 of programmable multiplexer 62 having the input line 66 and the output line 52.
  • a transistor 101 has one electrode coupled to a node 102 and another electrode coupled to a line 104, while a programmable device 106 is coupled between line 104 via a node 108 and digital ground.
  • the programmable device 106 can be, for example, a laser-blown type fuse or an electrically-blown type fuse.
  • a circuit path shown generally at 110 is coupled between V and digital ground, and includes a series-connected transistor 112 and transistor 114.
  • the transistor 114 has its gate electrode coupled to line 104 and, therefore, is turned on or off in response to a gating signal on line 104,
  • the output of circuit path 110 is taken via a node 116 on a line 118 to control the gating on or off of a transistor 120.
  • OMPI ⁇ - 122 is coupled between +V and digital ground and has, in series-connection, a transistor 124, a transistor 126 and a programmable device 128.
  • the output of circuit path 122 is taken via a node 130 over a line 132 to control the gating on or off of a transistor 134 which is in series circuit with the transistor 120.
  • the programmable device 128 can be, for example, a laser-blown fuse or an electrically-blown fuse.
  • a capacitor 136 is charged via V , transistor 124, transistor 126, node 130 and a node 138.
  • the node 130 and the node 138 are electrically indistinguishable.
  • Charged capacitor 136 is then used to hold on, via node 138, the transistor 101 and, via node 130, the transistor 134.
  • a line 140 couples one electrode of transistor 134 to node 102, while output line 52 is coupled to a node 142 between electrodes of transistor 120 and transistor 134.
  • Line 52 can be coupled to line 66 by programming both programmable device 106 and programmable device 128, i.e., by opening device 106 and device 128.
  • Line 52 can be permanently decoupled from line 66 by not programming programmable device 106 and programmable device 128, i.e., by maintaining these programmable devices closed.
  • the programming of device 106 and device 128 can occur using conventional programming techniques and depending on whether these devices are laser-blown or electrically-blown fuses.
  • the path from node 108 to digital ground through opened device 106 is open. Therefore, when the signal on line 66 is at logic 1, transistor 101, which is gated on via source 136 and node 138, couples this logic 1 signal to line 104 and, thereby, gates on transistor 114. Therefore, the circuit path 110 is closed between +V - and digital ground, whereby node 116 and line 118 are at logic 0 to gate off transistor 120. Also, therefore, with transistor 134 being gated on, and with line 140 being at logic 1 via node 102, transistor 134 couples this logic 1 via node 142 to output line 52 as the previously mentioned logic 1 gate enabling signal.
  • line 104 is coupled to digital ground through node 108 and closed device 106, so that line 104 is permanently at logic 0 to gate off transistor 114 and, thereby, gate on transistor 120.
  • line 132 is coupled to digital ground via node 130 and device 128, so that line 132 is permanently at logic 0 to gate off transistor 134. Consequently, line 52 is always at logic 0, whereby line 52 is decoupled from line 66.
  • circuit 68 of programmable multiplexer 62 is similar to circuit 64 and can be programmed or not programmed, with similar results as described above.
  • circuit 96 and circuit 100 of programmable multiplexer 94 are similar to circuit 64 and can be programmed or not programmed, with similar results as described above. Also shown schematically is the pass gate
  • Pass gate 58 is illustrated schematically and includes a transistor 146 having a gate electrode coupled to line 54, one electrode coupled to redundant column RC, and another electrode coupled to data line DL-. Transistor 146 is gated on or off in a similar manner as transistor 144 to couple or decouple redundant column RC, with respect to data line DL-.
  • Pass gate 74 includes a transistor 148 which is in circuit with data line DL, .
  • Transistor 148 has a gate electrode coupled to the output of NOR gate 70 over line 72, one electrode coupled to bit segment BS, and another electrode coupled to sense amplifier SA,.
  • Pass gate 78 includes a transistor 150 which is in circuit with data line
  • Transistor 150 includes a gate electrode coupled to the output of NOR gate 74 over line 76, one electrode coupled to bit segment BS 2 and another electrode coupled to sense- ⁇ amplifier SA 2 .
  • transistor 148 is, respectively, gated on or off to enable or disable data flow between bit segment BS, and sense amplifier SA,.
  • Transistor 150 operates in a similar manner for controlling data flow between bit segment BS- and sense amplifier SA 2 .
  • address decoder 60 will be programmed in a conventional manner to decode the column address
  • OMPI to defective column 18- and circuit 64 will be programmed as described above to couple line 66 to line 52, with circuit 68 not being programmed.
  • address decoder 92 will be programmed in a conventional manner to decode the column address to defective column 20, and circuit 100 will be programmed, as described above, to couple line 98 to line 86, with circuit 96 not being programmed. Accordingly, the coupling and decoupling of redundant column RC, and the corresponding decoupling and coupling of bit segment .BS, with respect to data line DL, will occur as previously described, depending on whether defective column 18- is addressed or the other non-defective columns 18 are addressed.
  • the architecture of the byte wide memory circuit 12, particularly the 4-bit byte wide architecture specifically described requires only one, relatively low power sense amplifier SA per data line DL.
  • the one sense amplifier SA such as sense amplifier SA, receives all data on data line DL, , whether from bit segment BS, or redundant column RC, or redundant column RC- for amplifying this data.
  • This advantageously reduces the number of components' required for the present invention and the power requirement of the sense amplifier SA,.
  • the redundant columns RC are coupled to the respective data lines DL at points along the data lines DL near the port means PM.

Landscapes

  • For Increasing The Reliability Of Semiconductor Memories (AREA)
  • Logic Circuits (AREA)
  • Error Detection And Correction (AREA)
  • Detection And Correction Of Errors (AREA)

Abstract

Un circuit de mémoire par quartets (12) possède un schéma de redondance de colonnes comprenant une pluralité de segments binaires (BS) ayant chacun des colonnes (18, 20), pour le stockage de données, une pluralité de lignes de données (DL) correspondant respectivement à la pluralité de segments binaires (BS) une pluralité de ports entrée/sortie (PM) couplés, respectivement, à la pluralité de lignes de données (DL), une pluralité de colonnes redondantes (RC) pour le stockage de données et de manière correspondante, respectivement à la pluralité de ports entrée/sortie (PM), et un circuit programmable (28) pour coupler entre elles, respectivement, la pluralité de colonnes redondantes (RC) des lignes de données (DL) tout en désaccouplant les segments binaires (BS) des lignes de données (DL).
PCT/US1984/000757 1983-07-14 1984-05-17 Circuit de memoire par quartets ayant un circuit de redondance de colonnes WO1985000460A1 (fr)

Applications Claiming Priority (2)

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US51420383A 1983-07-14 1983-07-14
US514,203 1983-07-14

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EP (1) EP0150194A4 (fr)
JP (1) JPS60501878A (fr)
WO (1) WO1985000460A1 (fr)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0243859A2 (fr) * 1986-05-02 1987-11-04 International Business Machines Corporation Mémoire à accès aléatoire à deux portes avec redondance de colonne
FR2644924A1 (fr) * 1989-03-23 1990-09-28 Sgs Thomson Microelectronics Circuit de selection d'une colonne redondante dans une memoire integree avec redondance de colonnes de donnees
DE4029247A1 (de) * 1990-09-14 1992-03-19 Samsung Electronics Co Ltd Doppel-port-speichereinrichtung
US6041422A (en) * 1993-03-19 2000-03-21 Memory Corporation Technology Limited Fault tolerant memory system

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US4051354A (en) * 1975-07-03 1977-09-27 Texas Instruments Incorporated Fault-tolerant cell addressable array
US4233674A (en) * 1978-08-07 1980-11-11 Signetics Corporation Method of configuring an integrated circuit
US4389715A (en) * 1980-10-06 1983-06-21 Inmos Corporation Redundancy scheme for a dynamic RAM
WO1983002847A1 (fr) * 1982-02-05 1983-08-18 Advanced Micro Devices Inc Memoire a semiconducteurs utilisant des circuit redondants

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US4281398A (en) * 1980-02-12 1981-07-28 Mostek Corporation Block redundancy for memory array
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US4051354A (en) * 1975-07-03 1977-09-27 Texas Instruments Incorporated Fault-tolerant cell addressable array
US4233674A (en) * 1978-08-07 1980-11-11 Signetics Corporation Method of configuring an integrated circuit
US4389715A (en) * 1980-10-06 1983-06-21 Inmos Corporation Redundancy scheme for a dynamic RAM
WO1983002847A1 (fr) * 1982-02-05 1983-08-18 Advanced Micro Devices Inc Memoire a semiconducteurs utilisant des circuit redondants

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Title
IBM Journal of Research Development, Vol. 24, No. 3, issued May 1980, (Armonk, N.Y.), FITZGERALD et al, "Circuit Implementation of Fusible Redundant Addresses on Rams for Productivity Enhancement:, see pages 291-292, 295-297 and figure 8. *
IBM Technical Disclosure Bulletin, Vol. 24, No. 11B, issued April 1982 (Armonk, N.Y.), BOSCH et al, "Static/Dynamic Fault Relocation for a Fault Tolerant Memory", see pages 6046-7. *
See also references of EP0150194A4 *

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0243859A2 (fr) * 1986-05-02 1987-11-04 International Business Machines Corporation Mémoire à accès aléatoire à deux portes avec redondance de colonne
EP0243859A3 (fr) * 1986-05-02 1990-03-21 International Business Machines Corporation Mémoire à accès aléatoire à deux portes avec redondance de colonne
FR2644924A1 (fr) * 1989-03-23 1990-09-28 Sgs Thomson Microelectronics Circuit de selection d'une colonne redondante dans une memoire integree avec redondance de colonnes de donnees
DE4029247A1 (de) * 1990-09-14 1992-03-19 Samsung Electronics Co Ltd Doppel-port-speichereinrichtung
US6041422A (en) * 1993-03-19 2000-03-21 Memory Corporation Technology Limited Fault tolerant memory system

Also Published As

Publication number Publication date
JPS60501878A (ja) 1985-10-31
EP0150194A4 (fr) 1988-04-26
EP0150194A1 (fr) 1985-08-07

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