CA2202692C - Redondance de colonne dans des memoires semi-conductrices - Google Patents

Redondance de colonne dans des memoires semi-conductrices Download PDF

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Publication number
CA2202692C
CA2202692C CA002202692A CA2202692A CA2202692C CA 2202692 C CA2202692 C CA 2202692C CA 002202692 A CA002202692 A CA 002202692A CA 2202692 A CA2202692 A CA 2202692A CA 2202692 C CA2202692 C CA 2202692C
Authority
CA
Canada
Prior art keywords
column
redundant
normal
memory device
columns
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
CA002202692A
Other languages
English (en)
Other versions
CA2202692A1 (fr
Inventor
Arun Achyuthen
Lidong Chen
John Wu
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mosaid Technologies Inc
Original Assignee
Mosaid Technologies Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mosaid Technologies Inc filed Critical Mosaid Technologies Inc
Priority to CA002202692A priority Critical patent/CA2202692C/fr
Priority to US08/904,153 priority patent/US5959903A/en
Publication of CA2202692A1 publication Critical patent/CA2202692A1/fr
Priority to US09/348,314 priority patent/US6141268A/en
Application granted granted Critical
Publication of CA2202692C publication Critical patent/CA2202692C/fr
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/70—Masking faults in memories by using spares or by reconfiguring
    • G11C29/78—Masking faults in memories by using spares or by reconfiguring using programmable devices
    • G11C29/84—Masking faults in memories by using spares or by reconfiguring using programmable devices with improved access time or stability
    • G11C29/846—Masking faults in memories by using spares or by reconfiguring using programmable devices with improved access time or stability by choosing redundant lines at an output stage
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/408—Address circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/408—Address circuits
    • G11C11/4087—Address decoders, e.g. bit - or word line decoders; Multiple line decoders

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • For Increasing The Reliability Of Semiconductor Memories (AREA)
  • Dram (AREA)
  • Techniques For Improving Reliability Of Storages (AREA)
CA002202692A 1997-04-14 1997-04-14 Redondance de colonne dans des memoires semi-conductrices Expired - Fee Related CA2202692C (fr)

Priority Applications (3)

Application Number Priority Date Filing Date Title
CA002202692A CA2202692C (fr) 1997-04-14 1997-04-14 Redondance de colonne dans des memoires semi-conductrices
US08/904,153 US5959903A (en) 1997-04-14 1997-07-31 Column redundancy in semiconductor memories
US09/348,314 US6141268A (en) 1997-04-14 1999-07-07 Column redundancy in semiconductor memories

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CA002202692A CA2202692C (fr) 1997-04-14 1997-04-14 Redondance de colonne dans des memoires semi-conductrices

Publications (2)

Publication Number Publication Date
CA2202692A1 CA2202692A1 (fr) 1998-10-14
CA2202692C true CA2202692C (fr) 2006-06-13

Family

ID=4160422

Family Applications (1)

Application Number Title Priority Date Filing Date
CA002202692A Expired - Fee Related CA2202692C (fr) 1997-04-14 1997-04-14 Redondance de colonne dans des memoires semi-conductrices

Country Status (2)

Country Link
US (2) US5959903A (fr)
CA (1) CA2202692C (fr)

Families Citing this family (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW436806B (en) * 1998-07-23 2001-05-28 Fujitsu Ltd Semiconductor memory device and method for executing shift redundancy operation
US6137735A (en) * 1998-10-30 2000-10-24 Mosaid Technologies Incorporated Column redundancy circuit with reduced signal path delay
US6097645A (en) * 1999-03-04 2000-08-01 Texas Instruments Incorporated High speed column redundancy scheme
US6400619B1 (en) 2001-04-25 2002-06-04 International Business Machines Corporation Micro-cell redundancy scheme for high performance eDRAM
KR100408714B1 (ko) * 2001-06-28 2003-12-11 주식회사 하이닉스반도체 반도체 메모리 장치의 컬럼 리페어회로 및 방법
US6674673B1 (en) 2002-08-26 2004-01-06 International Business Machines Corporation Column redundancy system and method for a micro-cell embedded DRAM (e-DRAM) architecture
US6807114B2 (en) * 2003-01-17 2004-10-19 Micron Technology, Inc. Method and system for selecting redundant rows and columns of memory cells
US8976604B2 (en) 2012-02-13 2015-03-10 Macronix International Co., Lt. Method and apparatus for copying data with a memory array having redundant memory
US9165680B2 (en) 2013-03-11 2015-10-20 Macronix International Co., Ltd. Memory integrated circuit with a page register/status memory capable of storing only a subset of row blocks of main column blocks
US9773571B2 (en) 2014-12-16 2017-09-26 Macronix International Co., Ltd. Memory repair redundancy with array cache redundancy
US20160218286A1 (en) 2015-01-23 2016-07-28 Macronix International Co., Ltd. Capped contact structure with variable adhesion layer thickness
US9514815B1 (en) 2015-05-13 2016-12-06 Macronix International Co., Ltd. Verify scheme for ReRAM
US9881697B2 (en) 2016-03-04 2018-01-30 Sandisk Technologies Llc Dynamic-shifting redundancy mapping for non-volatile data storage
US9691478B1 (en) 2016-04-22 2017-06-27 Macronix International Co., Ltd. ReRAM array configuration for bipolar operation
US9583211B1 (en) 2016-06-01 2017-02-28 International Business Machines Coproration Incorporating bit write capability with column interleave write enable and column redundancy steering
US9959928B1 (en) 2016-12-13 2018-05-01 Macronix International Co., Ltd. Iterative method and apparatus to program a programmable resistance memory element using stabilizing pulses

Family Cites Families (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4598388A (en) * 1985-01-22 1986-07-01 Texas Instruments Incorporated Semiconductor memory with redundant column circuitry
JP2600435B2 (ja) * 1990-05-08 1997-04-16 松下電器産業株式会社 冗長救済回路
EP1227504B1 (fr) * 1991-08-28 2004-08-04 Oki Electric Industry Co., Ltd. Dispositif de mémoire à semiconducteurs
KR950000275B1 (ko) * 1992-05-06 1995-01-12 삼성전자 주식회사 반도체 메모리 장치의 컬럼 리던던시
US5469401A (en) * 1992-07-14 1995-11-21 Mosaid Technologies Incorporated Column redundancy scheme for DRAM using normal and redundant column decoders programmed with defective array address and defective column address
EP0646866A3 (fr) * 1993-09-30 1998-05-27 STMicroelectronics, Inc. Validation-maítre pour décodeur de rangée redondante
JPH07105697A (ja) * 1993-10-07 1995-04-21 Mitsubishi Electric Corp 半導体記憶装置
EP0697659B1 (fr) * 1994-08-12 1999-12-15 Siemens Aktiengesellschaft Circuit de redondance pour une mémoire à circuit intégré à semi-conducteur
KR0130030B1 (ko) * 1994-08-25 1998-10-01 김광호 반도체 메모리 장치의 컬럼 리던던시 회로 및 그 방법
JPH08153399A (ja) * 1994-11-29 1996-06-11 Nec Corp 半導体記憶装置
JPH0955080A (ja) * 1995-08-08 1997-02-25 Fujitsu Ltd 半導体記憶装置及び半導体記憶装置のセル情報の書き込み及び読み出し方法
EP0758112B1 (fr) * 1995-08-09 2002-07-03 Infineon Technologies AG Dispositif de mémoire à semiconducteur intégrée avec arrangement de circuits redondants
US5646896A (en) * 1995-10-31 1997-07-08 Hyundai Electronics America Memory device with reduced number of fuses
US5732030A (en) * 1996-06-25 1998-03-24 Texas Instruments Incorporated Method and system for reduced column redundancy using a dual column select

Also Published As

Publication number Publication date
US5959903A (en) 1999-09-28
CA2202692A1 (fr) 1998-10-14
US6141268A (en) 2000-10-31

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Effective date: 20170418