WO1983001709A1 - Structure de transistor plane - Google Patents

Structure de transistor plane Download PDF

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Publication number
WO1983001709A1
WO1983001709A1 PCT/DE1982/000174 DE8200174W WO8301709A1 WO 1983001709 A1 WO1983001709 A1 WO 1983001709A1 DE 8200174 W DE8200174 W DE 8200174W WO 8301709 A1 WO8301709 A1 WO 8301709A1
Authority
WO
WIPO (PCT)
Prior art keywords
zone
area
potential
base
ring
Prior art date
Application number
PCT/DE1982/000174
Other languages
German (de)
English (en)
Inventor
Bosch Gmbh Robert
Original Assignee
Michel, Hartmut
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Michel, Hartmut filed Critical Michel, Hartmut
Publication of WO1983001709A1 publication Critical patent/WO1983001709A1/fr

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/402—Field plates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
    • H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
    • H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
    • H01L29/0619—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE] with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction

Definitions

  • the invention is based on a planar transistor structure according to the preamble of the main claim.
  • the transistor structures are already known. However, they have the disadvantage that external electric fields, such as those caused by polarization of masking lacquers when operated at high voltage and temperature, can lead to degradation of the blocking characteristics.
  • planar transistor structure according to the invention with the characterizing features of the main claim has the advantage over the fact that the space charge zone that forms during operation around the base zone is limited within the second annular zone and is shielded below the metal layer serving as the cover electrode from external electrical fields.
  • FIG. 1 shows a schematic partial section through the planar transistor structure according to the invention
  • FIG. 2 shows a non-schematic top view of the arrangement according to FIG. 1
  • FIG. 3 shows a top view of one of the Z paths designed as an emitter-base paths according to the invention.
  • 10 denotes a semiconductor wafer with n conductivity.
  • the semiconductor plate 10 has a collector connection C on its underside.
  • a p-conductive base zone 11 is diffused into the semiconductor plate 10 from above.
  • the base zone 11 carries a metallization, not specified, which leads to a base connection B.
  • An emitter zone which is not shown in FIG. 1 and has n + conductivity, is diffused into the base zone 11 from the same main surface of the semiconductor die 10 in the usual way.
  • a passivation layer 13 extends over the top of the semiconductor die 10, but is interrupted at various points to form contact windows.
  • a first annular zone 14 with p-conductivity is diffused around the base zone 11 into the upper side of the semiconductor die 10.
  • a second annular zone 15 with n + conductivity which serves as a stop ring, is further diffused into the upper side of the semiconductor die 10.
  • a metal layer D serving as a cover electrode is applied, which surrounds the base zone 11 in a ring shape, overlaps the edge of the base zone 11 which occurs at the top of the semiconductor die, extends into the region above the second annular zone 15 and with which first annular zone 1 4 is contacted in the region of the contact window 16.
  • the potential of the first annular zone 1 4 and thus the potential of the cover electrode D is selected according to the invention so that it lies between the potential of the base zone 11 and the potential of the semiconductor wafer 10 forming the collector zone.
  • FIG. 2 which shows a scale top view of the arrangement schematically drawn in FIG. 1, the three Z sections at 17, 18 and 19, indicated only schematically in FIG. 1, can be seen in the top view.
  • the passivation layer 13 is omitted from the drawing or assumed to be transparent so that the Z sections 17, 18, 19 and zones 11, 14 and 15 with their borders on the semiconductor surface become visible.
  • the cover electrode D extends in FIG. 2 over the entire strip-shaped area between the two dashed lines d1 and d2 with the exception of a recess A, which is also surrounded by dashed lines.
  • the recess A is necessary to accommodate the contact windows of the Z sections 17, 18 19 and the metallization bridges between these sections and their connection points.
  • the triangular contact window 16 shown in plan view in FIG. 2 serves to contact the top electrode D with the first annular zone 14.
  • each Z segment consists of a p-type zone 20 diffused into the n-type collector base material 10 and of an n + type zone 21 diffused into this zone.
  • Each of the two zones 20, 21 has a contact window (not shown in FIG. 3) and a metallization accommodated therein.
  • This metallization is indicated in FIG. 2 by dots, while the metallization bridges between the individual Z sections 17, 18, 19 are indicated in FIG. 2 by solid lines.
  • the dashed line drawn in the upper part of the recess A between two contact windows soll, on the other hand, is intended to indicate that further Z sections can also be accommodated in this space.

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Electrodes Of Semiconductors (AREA)

Abstract

La structure comprend une zone collectrice dans une plaquette (10) semiconductrice avec une conductivité n- et une zone de base (11) diffusée sur la surface principale de la plaquette (10) et ayant une conductivité de type p. Elle comprend une zone émettrice diffusée dans la zone de base (11) de conductivité du type n+ et une couche de passivation (13). Cette dernière recouvre la partie de la surface princiale de la plaquette (10) qui n'est pas utilisée comme fenêtre de contact. Une première zone en forme d'anneau (14) est diffusée autour de la zone de base (11) dans la surface principale de la plaquette. Elle a une conductivité du type p. Une deuxième zone de type de conductivité n+ est diffusée autour de la zone en anneau (14) dans la surface principale de la plaquette (10). Elle joue le rôle d'anneau d'arrêt (15). Sur la couche de passivation (13) on dépose une couche métallique (D) qui fonctionne comme électrode de couverture, entoure la zone de base (11) en formant un anneau, chevauche le bord de la zone de base (11), s'étend jusqu'au dessus de la deuxième zone annulaire (15) et entre en contact dans la première zone (14) avec cette zone (14). Le potentiel de la première zone en anneau (14) et par conséquent le potentiel de l'électrode de couverture (D) est ainsi fixé de manière à être situé entre le potentiel de la zone de base (11) et le potentiel de la plaquette semiconductrice (10) constituant la zone collectrice.
PCT/DE1982/000174 1981-10-28 1982-09-03 Structure de transistor plane WO1983001709A1 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
DEP3142616.6811028 1981-10-28
DE19813142616 DE3142616A1 (de) 1981-10-28 1981-10-28 "planare transistorstruktur"

Publications (1)

Publication Number Publication Date
WO1983001709A1 true WO1983001709A1 (fr) 1983-05-11

Family

ID=6144948

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/DE1982/000174 WO1983001709A1 (fr) 1981-10-28 1982-09-03 Structure de transistor plane

Country Status (4)

Country Link
EP (1) EP0092550A1 (fr)
DE (1) DE3142616A1 (fr)
IT (1) IT1153589B (fr)
WO (1) WO1983001709A1 (fr)

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0098834B1 (fr) * 1982-01-20 1987-01-07 Robert Bosch Gmbh Dispositif semi-conducteur planaire
WO1992000606A1 (fr) * 1990-06-28 1992-01-09 Robert Bosch Gmbh Dispositif semi-conducteur monolithique integre avec une electrode de couverture
WO1994016462A1 (fr) * 1993-01-07 1994-07-21 Harris Corporation Structure de passivation marginale helicoidale pour des dispositifs a semi-conducteurs
US5479046A (en) * 1990-06-28 1995-12-26 Robert Bosch Gmbh Monolithically integrated semiconductor arrangement with a cover electrode
EP0703627A1 (fr) * 1994-09-20 1996-03-27 Hitachi, Ltd. Dispositif semi-conducteur avec plaque de champ et convertisseur de puissance utilisant ce dispositif

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3710204A (en) * 1967-05-20 1973-01-09 Telefunken Patent A semiconductor device having a screen electrode of intrinsic semiconductor material
US3763406A (en) * 1969-03-25 1973-10-02 Philips Corp Guard junction for semiconductor devices
US3836998A (en) * 1969-01-16 1974-09-17 Signetics Corp High voltage bipolar semiconductor device and integrated circuit using the same and method
FR2282723A1 (fr) * 1974-08-19 1976-03-19 Sony Corp Composant semi-conducteur a jonction recouverte d'une couche de passivation
US4009483A (en) * 1974-04-04 1977-02-22 Motorola, Inc. Implementation of surface sensitive semiconductor devices

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3710204A (en) * 1967-05-20 1973-01-09 Telefunken Patent A semiconductor device having a screen electrode of intrinsic semiconductor material
US3836998A (en) * 1969-01-16 1974-09-17 Signetics Corp High voltage bipolar semiconductor device and integrated circuit using the same and method
US3763406A (en) * 1969-03-25 1973-10-02 Philips Corp Guard junction for semiconductor devices
US4009483A (en) * 1974-04-04 1977-02-22 Motorola, Inc. Implementation of surface sensitive semiconductor devices
FR2282723A1 (fr) * 1974-08-19 1976-03-19 Sony Corp Composant semi-conducteur a jonction recouverte d'une couche de passivation

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0098834B1 (fr) * 1982-01-20 1987-01-07 Robert Bosch Gmbh Dispositif semi-conducteur planaire
WO1992000606A1 (fr) * 1990-06-28 1992-01-09 Robert Bosch Gmbh Dispositif semi-conducteur monolithique integre avec une electrode de couverture
US5479046A (en) * 1990-06-28 1995-12-26 Robert Bosch Gmbh Monolithically integrated semiconductor arrangement with a cover electrode
WO1994016462A1 (fr) * 1993-01-07 1994-07-21 Harris Corporation Structure de passivation marginale helicoidale pour des dispositifs a semi-conducteurs
US5382825A (en) * 1993-01-07 1995-01-17 Harris Corporation Spiral edge passivation structure for semiconductor devices
EP0703627A1 (fr) * 1994-09-20 1996-03-27 Hitachi, Ltd. Dispositif semi-conducteur avec plaque de champ et convertisseur de puissance utilisant ce dispositif

Also Published As

Publication number Publication date
IT1153589B (it) 1987-01-14
IT8223923A0 (it) 1982-10-26
DE3142616A1 (de) 1983-05-05
EP0092550A1 (fr) 1983-11-02

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