Classifications

• • H—ELECTRICITY
  • H03—ELECTRONIC CIRCUITRY
  • H03G—CONTROL OF AMPLIFICATION
  • H03G3/00—Gain control in amplifiers or frequency changers
  • H03G3/20—Automatic control
  • H03G3/30—Automatic control in amplifiers having semiconductor devices
  • H03G3/3005—Automatic control in amplifiers having semiconductor devices in amplifiers suitable for low-frequencies, e.g. audio amplifiers
• • H—ELECTRICITY
  • H03—ELECTRONIC CIRCUITRY
  • H03G—CONTROL OF AMPLIFICATION
  • H03G3/00—Gain control in amplifiers or frequency changers
  • H03G3/20—Automatic control
  • H03G3/30—Automatic control in amplifiers having semiconductor devices
  • H03G3/3005—Automatic control in amplifiers having semiconductor devices in amplifiers suitable for low-frequencies, e.g. audio amplifiers
  • H03G3/301—Automatic control in amplifiers having semiconductor devices in amplifiers suitable for low-frequencies, e.g. audio amplifiers the gain being continuously variable
• • H—ELECTRICITY
  • H03—ELECTRONIC CIRCUITRY
  • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
  • H03L5/00—Automatic control of voltage, current, or power

Definitions

• the present invention applies an amplitude control circuit for stabilizing the output signal amplitude of a positive wave signal oscillator.
• a sinusoidal oscillator particularly a wing-bridge type or a sulzer type, is used as an oscillator used in a frequency band of several Hz to several 100 KHz.
• a device such as a glass-tube-enclosed type of thermistor or a tundant lamp that uses a device whose resistance value changes depending on the heat of the coil.
• the amplitude stabilizing means of the former (a) is often used because of its simple construction. However, when this method is used, it is difficult to obtain a sinusoidal signal with a low distortion in the low frequency region below a few 10 Hz. This is because the internal resistance of the amplitude stabilization element is not modulated by the effective value of the oscillation output signal amplitude, but by the amplitude change itself. Amplitude stabilization is a solution to this problem.
• the heat capacity of the element must be extremely large. However, the larger the heat capacity of the amplitude-stabilized potato, the worse the followability to the average fluctuation of the oscillation output amplitude. '' This deterioration of followability is commonly referred to as hunting.
• the latter (b) means for stabilizing amplitude is slightly more complicated than the former (a) in terms of its structure.
• the amplitude stabilizing means of (b) is also different. It is widely used.
• the internal resistance of the amplitude stabilizing element is controlled by the control voltage or the control current.
• the source-drain resistance of FET is used for the amplitude stabilizing element.
• the internal resistance of FET is controlled by the voltage between the dirt and the source.
• the average value or peak value of the rectified oscillation output signal is used as the control voltage. This rectified oscillation output signal is output to the resonator by an eliminator or filter circuit.
• the time constant of the filter circuit must be set large. Absent. If this time constant is small, the amplitude of the ripple contained in the control signal becomes large as the oscillation frequency becomes low. 'This ripple modulates the internal resistance of the amplitude control element and deteriorates the distortion factor of the oscillation output signal. On the other hand, if the time constant of the filter circuit is increased in order to reduce the distortion rate of the oscillation output signal, the above-mentioned hunting phenomenon becomes noticeable. As described above, also in the amplitude stabilizing means of (b), lowering the distortion factor and lowering the hunching are mutually contradictory matters.
• the amplitude control circuit according to the present invention has the following configuration.
• An amplification means for outputting an IS oscillation output signal; an amplification degree control means provided in the first feedback loop of the amplification means for controlling the amplification degree of the amplification means; and a frequency of the oscillation output signal. And an oscillation frequency setting means provided in the second feedback loop of the amplifying means.
• the first phase-shifted signal having a phase difference with respect to the oscillation output signal and derived from the oscillation frequency setting means and the oscillation output signal.
• Vector synthesizing means for synthesizing a second phase-shifted signal that is phase-shifted by a predetermined magnitude with respect to the oscillation output signal;
• control signal corresponding to the amplitude of the oscillation output signal is increased based on the second phase shift signal and the transmission output signal. 'Control signal provided to the width control means ⁇ generation means.
• the amplitude control circuit having the above configuration, it is possible to obtain the control signal corresponding to the amplitude without substantially relating to the frequency of the oscillation output signal.
• Figure 1 is a block diagram showing the basic configuration of a sine wave oscillator including the amplitude control circuit according to the present invention.
• Figure 2 is a circuit diagram that embodies the configuration shown in Figure 1.
• Figures 3A and 3B are vector diagrams showing how the vector synthesis circuit J S in Figure 1 performs vector synthesis. '
• FIGS. 4A to 40 are waveform diagrams showing the sine wave signal eJa, the cosine wave signal e3a, and the control signal in the circuit shown in FIG.
• Fig. 5 is a graph showing an example of the gut voltage-drain electric characteristics of the P channel F ET 2 8-34 shown in Fig. 2.
• FIG. 6 is a circuit diagram showing a modification of the oscillator circuit i 6 shown in FIG.
• FIG. 11 is a block diagram showing a modified example of the square function combining circuit in 20.
• FIG. 8 is a circuit diagram embodying the square function circuits 7 2 and 6 shown in FIG.
• 9 to 11 are circuit diagrams showing modified examples of the oscillation circuit J 6 shown in FIG.
• FIG. 12 is a block diagram showing a modified configuration example of the vector synthesizing circuit J S and the control signal generating circuit 2 shown in FIG. '
• Fig. 13 is a vector diagram showing the state of signals formed in each block shown in Fig. 12.
• Figure 15 is a circuit diagram that embodies the configuration shown in Figure 12.
• Figure 16 is a block diagram showing the configuration when the amplitude control circuit of the configuration shown in Figure 1 is applied to an automatic level control circuit.
• FIG. 1 shows a basic configuration of a sine wave oscillator including an amplitude control circuit according to the present invention.
• the 'output signal e J of the amplifier circuit (?) Is input to the amplification control circuit ⁇ 2.
• the signal ej is fed back to the first input terminal of the amplification circuit 0 via the control circuit J 2.
• the signal e J is also fed back to the amplifier circuit via the oscillation frequency setting circuit J 4.
• Negative feedback (or positive feedback) is applied to the second input terminal of 2 ⁇ ?.
• Circuits J 0, I 2 and R 4 form a normal oscillator circuit.
• the signals applied to the first and second input terminals of the amplifier circuit JT 0 were the positive feedback signal and the negative feedback signal, respectively.
• the oscillating circuit I 6 in this case is formed by, for example, a Salza-type (conclusion T-type) oscillating circuit.
• the oscillator circuit _ is, for example, a winde bridge type. It is formed by an oscillator circuit.
• the signal e ⁇ is applied to the first input of the vector combiner Jf *.
• the phase shift signal e 2 derived from the setting circuit j 4 is applied to the second input terminal of the combining circuit J i s. If the setting circuit 2 4 is of the sulzer type or the Wien type, the phase shift amount of the signal e 2 with respect to the signal e J is
• Signals e i and e 2 are output from signals e j to 90 by the combining circuit. Converted to out-of-phase signal e 3.
• the signal e J is a sine
• the signal e 3 becomes a cosine wave.
• the signal ei is further applied to the first input terminal of the control signal generator circuit 2.
• the signal e 3 force s is applied to the second input terminal of the control signal generating circuit 2.
• Control signal ⁇ circuit. 2 Fei is a circuit for combining the control signal e 4 comprising a DC component proportional to the square sum of, respectively Re its signal ej Contact and e 3. That is, the direct flow component of the signal e 4 is represented by a function having ej 2 + e 3 l as a variable. Now, let's express the signals e J and e 3 respectively as follows.
• E is the amplitude (corresponding to the peak value) of signals e J and e 3, is its angular frequency, and t is time.
• the signal e 4 is expressed as follows.
• k is a proportional coefficient peculiar to the control signal generating circuit 2 ⁇ ?.
• the signal e 4 is independent of the angular frequency of the oscillation output signal e 1.
• the signal e 4 contains only information proportional to the square of the amplitude E of the signal e J.
• Figure 2 is a more detailed version of the basic configuration shown in Figure 1.
• OMPI It is a schematic circuit diagram. This circuit configuration is what the inventor believes to be the optimum mode at the time when this cocoon is made.
• the output terminal of the amplifier J 0 is connected to the positive phase input terminal of the amplifier J ⁇ 7 via a resistor. This positive-phase input terminal is grounded via the resistance element R J 2, of the impedance controlled element J 2.
• R J 2 the resistance element for this controlled element 2 2 t, a combination of a L E D and a C d S cell is suitable as a photo-voltage generator. In-band dance controlled element J 2! And resistance
• R 2 2 2 has formed the amplification degree control circuit.
• the resistor has a capacitor
• a bridge T-shaped oscillator station wave number setting circuit J 4 is formed.
• Amplifier J 0, impedance controlled element J, and resistance RJ 2 2 , RI 4, f R 1 4 t , and capacitor
• the output end is connected to the output end of the amplifier J 0 through a series circuit of resistors RJS s and RJS 4 .
• the amplifier 2 2 and the resistor RJ Si to R i S 4 form a vector combining circuit 18.
• the negative-phase input terminal of amplifier 2 2 is connected as an external ground '. That is, the'connection point between the resistors RJ 4 2 and R 1 8 ⁇ is equivalently grounded.
• the phase shift signal e appears at the connection point of the capacitors C i 4 , and C i .of the oscillation frequency setting circuit J 4.
• the phase shift signal e is a sine wave voltage signal whose phase is shifted by ⁇ with respect to the sine wave oscillation output signal e J of the oscillator circuit _ £.
• the phase shift signal e 2 becomes a current signal i 2 having a magnitude corresponding to e 2 Z n J and is input to the vector synthesizing circuit _.
• the current signal ⁇ 2 is converted into a phase shift signal by the amplifier 2.
• the phase shift signals e 2 and e 2 a have opposite phases.
• the amplitude of the phase shift signal e 2 a is
• FIG. 3A This figure shows how the combination of the phase shift signal ⁇ 3 by the vector combiner circuit ⁇ _ ⁇ is performed.
• the phase of the phase shift signal e 2 is delayed by ⁇ with respect to the oscillation output signal ⁇ i. Let's do it.
• the phase shift signal 6 2 a is obtained.
• the phase-shifted signal ⁇ 3 is obtained by vector-adding the phase-shifted signal 6 2 a and the oscillation output signal e 1. Due to the size of the amplitude multiplication factors A and _, the phase difference of the'phase-shifted signal e 3 with respect to the oscillation output signal ej is 90. Can be set to.
• the vector synthesis circuit _ can synthesize a cosine wave signal from a sine wave signal.
• the 90 ° phase shift signal A 2 e 3 with the same amplitude as the oscillation output signal e J can be obtained.
• the output terminal of the amplifier J 0 is connected to the negative phase input terminal of the amplifier 2 4 via the resistor and the series circuit of R 2 0 2 .
• the negative phase input terminal and output terminal of the amplifier 24 are connected through the resistor 112.
• the positive phase input terminal of amplifier 2 4 is connected to the offset phase resistance.
• R2 0 4 and through the are grounded.
• the connection point of the resistors RJS S and RZS 4 is connected to the negative phase input terminal of the amplifier 26 through the series circuit of the resistors H 20 s and R 20 e .
• Reverse phase input terminal Contact good beauty the output of the amplifier 2 5 is connected via a resistor R2 0 7.
• Positive phase input terminal of the amplifier 2 is grounded via the off cell Tsu preparative balun scan resistor R2 0 8.
• the temple. 2 and the signal appearing at the output of amplifier 24 is one e if a.
• the signal generated at the connection point of resistor 0 and R 20 e is e 3 a
• the signal generated at the output of amplifier 6 is 1.
• ⁇ 3 a The signal'e 1 a is in phase with the oscillation output signal e 1
• the signal 3 a is in phase with the phase shift signal ⁇ 3. Therefore, the signals ⁇ ⁇ ? A and e 3 a have a phase difference of 90 ° from each other.
• the amplitudes of signals e 1 a and e 3 a can be adjusted by resistors R 20 i and R 2 ⁇ ? 3 , respectively.
• Figures 4A and 4B show the phase relationships between signal a, i e a and signal e 3 a, i e 3 a.
• connection point of resistors R 2 and R 2 ⁇ 72 is connected to the gate of P channel MOS ⁇ F ⁇ T 2 S.
• the output of amplifier 2 4 is: P channel ⁇ 03 ⁇
• connection point of R and R 2 0 ⁇ and the output terminal of amplifier 2 are connected to the P channel M 0 S * FET 3 2 and 3 4 1 respectively.
• the enhanced type is used.
• the FET used here has a drain current ID that is substantially The gate-source voltage
• a depletion type may be used as 3 4.
• the main reason for using the enhanced-type ⁇ FET in Fig. 2 is that it is easy to simplify the circuit configuration.
• ' Figure 5 shows an example of the e ID — V characteristics of a P-channel FET.
• the curve A is the envelope type, and 1 V TH is the threshold voltage.
• Curve B is the depletion type and + V p is the pint voltage.
• the curves A and B can usually be represented by a quadratic function with good accuracy ⁇ j
• the drains of FET 2 S and 3 ⁇ are connected to one negative power supply via a resistor R 20 e .
• the drains of PET 3 2 and 3 4 are connected to the negative power supply VE ⁇ through a resistor R2 0 10 .
• Resistance R 2 0 9 your good beauty R 2 0 ie is provided for excessive current limit.
• Each source and substrate is connected to the NPN Transistor 3 emulator.
• the transistor 4 (7 collector is connected to the positive power source + Vc through the resistor R 2 0 1 3 ⁇ 4 .
• the diode-connected transistor 40 is-
• the gate bias voltage V8 (i) of T 2 8-3 4 can be adjusted by a resistor.
• FET2, '30 and 34 be dual FETs with the same characteristics. -.
• the collectors of the transistors 3 and 3 S are connected to the light-emitting element of the impedance-controlled element J 2, the source of the LED, via a resistor R 2. ..
• the anode of this LED is connected to the positive power supply + V C.
• the collectors of the transistors 3 and 3 S are grounded via the "e" 02 0.
• the capacitor 02 0, is the control voltage for the gain control circuit J. e 4 or control 'current 1 4 are kicked set the residual ripple included in order to Ikisukuna the FET 2 8 -.
• the control current I 4 does not include ripples.However, when the above ID—Vas characteristics deviate from the squared characteristics, the control current I 4 includes some ripples.
• the frequency component of the ripple is a higher harmonic component that is more than twice the frequency distortion of the oscillation output signal e I.
• the amplitude of the ripple component is smaller than the direct current component of the control current ⁇ 4 . It is extremely small, so it is possible to set the capacity of the carriage 02 0 t and that of the transistors 3 6 and 3 S.
• the time constant of the collector circuit and the impedance of the collector circuit may be small.
• the capacitor 02 may be omitted if the squared characteristic 'is accurate or if extremely low distortion is not required for the oscillation output signal e J.
• composition of I 4 can be considered as follows.
• a current i s proportional to ⁇ 3 a 2 and an electric current i "proportional to (one e 3 a ) 2 flow through £ 3 2 and 3 4, respectively, and the trans ′ ′.
• the co Lek capacitor circuit hex data 3 S,. all. current i M '+ i M flows.
• control current I 4 which is proportional to 6 3 a * over the phase section of the thy SL current i
• the collector voltage e a of transistors 35 and 33 corresponding to control current 1 4 is given by the sum of i and a 4 as shown in Fig. 4C.
• the DC signal contains some ripple. This residual ripple occurs when the above-mentioned squared characteristic is not realized accurately.
• the level of this DC signal is the amplitude of the oscillation output signal e J.
• the control current ⁇ 4 also has a signal waveform as shown in Fig. 40. By using the current I 4 , it is possible to provide a CR oscillator that simultaneously realizes low distortion and low resonance.
• a stable oscillation signal can be provided regardless of the oscillation frequency.
• an extremely low frequency sine wave signal which had been practically used only by conventional function generators, was converted into a normal Sulzer-shaped or double-branched signal. It can be embodied by a check-type oscillator circuit.
• a function generator is used as an extremely low frequency sine wave generator.
• the sine wave obtained by this function conversion has many odd harmonic distortions.
• Fig. 2 it is possible to obtain an extremely low frequency sine wave signal e J with low distortion.
• FIG. 6 shows a modification of the oscillator circuit in which the present invention can be used.
• a bootstrap type positive feedback circuit is used for the oscillation frequency setting circuit J 4.
• This positive feedback circuit is an application of the contents disclosed in another Japanese application No. 1 “band-wave circuit” by the same inventor as this application.
• the above-mentioned application is Japanese Patent Application No. 5 1-145981 filed on February 4, 1976.
• the positive feedback circuit for amplifier J is the same as in Fig. 2.
• the negative feedback circuit is constructed as follows.
• the output terminal of the amplifier J! 0 is connected to the positive phase input terminal of the amplifier 14 J through the series circuit of the resistors R 2 and 4.
• the connection point of the resistor II J ⁇ and the connecting point is amplified by the capacitor.
• the output terminal and negative-phase input terminal of amplifier 2 are connected via resistor I ⁇ 4.
• the negative-phase input terminal of amplifier J is grounded via resistor R.
• the positive-phase input terminal of amplifier is connected to the positive-phase input and output terminal of'amplification S a via capacitor GJ 4 3 ⁇ 4. ..
• the positive phase input terminal of the amplifier 0 is grounded via a resistor.
• the RZ 4 is that you use to change the oscillation frequency, not rather than the desired. Changing the resistance RJ ⁇ t or RJ 4 2, depending on this change amount, intends want also changes the amount of negative feedback amplifier J 0 at the oscillation frequency. Then, the amplitude of the oscillation output signal e J changes. If the output is harsh, the oscillation output signal ei will clip, or the oscillation will stop. There is no problem when the resistance, RI 4 and R 4 3 are changed so that (11 2 41 + 11 2 4,) 112 43 force — becomes constant.
• the oscillator circuit shown in Fig. 6 has the advantage that a single device (resistor or capacitor) for changing the ⁇ oscillation frequency is sufficient. This is especially beneficial when constructing a voltage-controlled oscillator (V G O).
• V G O voltage-controlled oscillator
• a Wien-brich ': type oscillating circuit as a device for changing the oscillation frequency, at least two variable resistances or variable casings are used. (Parisable capacitor) is required. If there is an error in interlocking these interlocking devices, the amplitude of the oscillation output e j changes as the oscillation frequency changes.
• Fig. 7 shows a modification of the square function combining circuit in the control signal generating circuit 2.
• the square-law characteristic between the gate-source voltage V os of the PET 28 to 34 and its drain current .ID is used.
• the FETs 2 s to 3 4 are cut off at the signal earth ej and the positive half cycle of tes, so that the FETs 2 8 to 3 4 are turned on by themselves. Signal. Gives full-wave rectification of e J and e 3.
• the full-wave rectification 'action and the square function combination action of the FETs 2 S to 34 as described above are possible even by the general configuration shown in FIG.
• the signal is converted by the full-wave rectifier circuit 70 into, for example, only positive sinusoidal pulsating current signal e 1 a.
• This signal eia is converted into a squared signal ej by a square function circuit.
• the signal e 3 is converted into the square signal es a 2 by the full-wave rectifier circuit 7 4 and the square function circuit 7 6.
• the squared signals e a ⁇ and es a 2 are added and combined in the adder 7 S.
• the square signal e J a 2 + ⁇ 3 a 2 -e 4 a is obtained by the adder 7 8.
• the adder 7 S can be constructed by a known circuit.
• a rectifier diode or a linear rectifier circuit with a rectifier transistor inserted in the negative feedback loop of the operational amplifier is suitable. Also,
• the square function circuit 7 2 , 7 ff has the following.
• OMPI It is a combination of roads.
• the input signal e is converted into ⁇ e by the logarithmic compression circuit.
• This ej is converted to 2 tosr ej-! Off ej 2 by the .2x amplifier.
• This toe ei is converted to "C exp (log ej 2 )-sei * according to the exponential function circuit Q.
• FET 7 2 2 of the source is connected to the inverting input of the amplifier 7.
• the negative-phase input terminal of the amplifier 7 2 is grounded via the resistor R 72.
• FIG. 9 to 12 show modified examples of the oscillation circuit ⁇ shown in Fig. 2.
• the impedance controlled element J 2, "included in the gain control circuit J 2 is shown.
• the resistor RJ 2 3 ⁇ 4 of is inserted between the positive-phase input terminal of the amplifier J and its output terminal.
• the electric power I 4 ⁇ that is supplied to the ramp of the impedance control device 2 ⁇ decreases.
• the ⁇ of this current 1 4. Represents Te cowpea one 1 4 the negative value.
• the resistance value of the oscillation output signal increases, and the grip width of the oscillation output signal 1 is reduced. Further, in the oscillation frequency setting circuit J 4, the capacitor 0 J is used as a bridge end element, and the oscillation circuit electric power i 2 is supplied through the capacitor.
• a window type oscillator circuit is used as the oscillator circuit 16.
• the output terminal of the amplifier J 0 through resistor RJ 2 2 is connected to its inverting input terminal.
• the negative-phase input terminal of the amplifier J 0 is grounded through the resistor RJ 2 3 and the drain-source of the N-channel FETI 2 1.
• the FETI 2 used here is assumed to be a depletion type. When an enhanced messenger type or P-channel FET is used, the way the bias is given or the polarity of the control signal e 4 a changes.
• a resistor R i 2 is connected between the drain and gate of FETJ 2 i. This resistance RJ 2 4 is,
• the current characteristic is a non-smooth curve commonly known as the three-tube characteristic.
• the control signal e 4 a is applied to the gate of the resistor via the resistor RJ 2 S ⁇ . In FIG. 10, this control signal e 4 a is marked with a minus sign. This minus sign is for the oscillation output signal e J.
• phase shift signal is connected to the positive phase input end of it width unit J 4 2.
• the negative-phase input terminal of amplifier J 4 is connected to its output cage. Phase shift signal
• phase shift direction of the phase shift signal e 2 is opposite to that of Fig. 2.
• FIG. 11 shows a modification of the oscillator circuit _ ⁇ _ shown in FIG.
• the output terminal of the amplifier J 0 is connected to the positive-phase input terminal of the ⁇ -width amplifier J 0 via the series circuit of the resistor RJ and the capacitor 02.
• the positive phase ⁇ end of is connected to the ground via the resistor RJ and the parallel circuit of the capacitor 0 J ⁇ .
• the output of the amplifier J 0 is connected to the inverting input terminal of amplifier 2 0 through the resistor I 2 2.
• Inverting input terminal of amplifier i 0 through a resistor R 2 2 3, Ru is grounded.
• the output terminal of the amplifier if 0 is connected to the negative phase input terminal of the amplifier J 4 3 via the resistor RJ 2 ⁇ .
• the negative-phase input terminal of the amplifier J 4 t is connected to the output terminal of the amplifier J 4 a via the resistor 1 ⁇ 2 ⁇ .
• the negative-phase input terminal of amplifier J ⁇ ? And the output terminal of amplifier 4 3 are connected via the drain 'source of the antenna type ⁇ channel MO SF ET I 2. To be done. Substrate of FET .1 2, is grounded. Goo door of FETJS t is, and through the resistance RJ 2 4, de Tray down of FET 2 2 i (a stomach source) is connected to.
• the gate is to through the resistor RJ 2 8,; is connected to the source over the scan (or de Tray down).
• the control signal ⁇ 4 a is given to the gut of FETJ Si through the resistor RJ 2 S.
• the gate of PE 1 2 X is connected to the negative terminal-YE via the resistor RJ ⁇ .
• the transfer signal e 2 is taken out from the contact point between the resistor R ⁇ ⁇ 4 X and the capacitor 0 J.
• the magnitude of the resistance ratio RJ 2 7 ZR 2 2 ⁇ is set so that the amplitude of the signal e 1 0 at the negative phase input terminal of 10 and the amplitude of the signal e 1 4 at the output terminal of the amplifiers 1 4 and 4 become equal. It is assumed that the height is adjusted. Then, the drain and the source of FETJ 2 i are given signals e I and e I 4 with the same amplitude in anti-phase with each other around the potential of the substrate. .. That is, 2 X is so-called push-pull driven. Such a configuration is suitable for amplitude control of large signals.
• the resistances R 2 4 and R i 2 ⁇ are provided to supplement the non-linearity of the internal resistance of F ⁇ 1 2 T.
• FIG. 12 shows a modification of the basic configuration of FIG.
• the n phase-combining circuits J .S n allow ⁇ kinds of phase-shifted signals ⁇ 3 ⁇ .
• the control signal e 4 is obtained by calculating the sum of the peaks of the absolute values of these phase shift signals e 3 II. That is, Fig. 12 shows the structure that embodies the following equation.
• Support output signal e 1 is absolute peak detector 2 J.
• the phase-shifted signal ⁇ 2 derived from the G source-wave frequency setting circuit 4 applied to the first input terminal of the vector synthesis circuit 25 and ⁇ iS n is the vector synthesis circuit JS. It is given to the second input terminal of i ⁇ 18.
• the combiner circuits J to JS n use the signals e 1 and e 2 as the basis for the phase shift signal e 3! -synthesize ⁇ 3 n.
• the composition circuit JS i is constructed in the same way as the composition circuit shown in Fig. 2.
• Combined circuit JS, "18 The combined signal es, ⁇ ⁇ 3 ⁇ Are the absolute values Beak detector 2 I! -2 1 ⁇ is input. .
• Signals e J and 'e 3,- ⁇ 3 n are respectively detected by detector 2 J. ⁇ 2 Depending on J II, absolute value signal
• the peak values of the signals e j, e 3, e 3 s, and e sa given to the adder 2 J have small peak values. Therefore, the time constant of the charging / discharging circuit of detector J 9 0 to 19 3 need only be relatively small.
• Figure 15 shows a sine wave oscillator embodied on the block configuration shown in Figures 1 and 12. With the circuit configuration in Fig. 15 the signals e 1, e 3 1 , es 2 and es 3 shown by the vector in Fig. 13 can be obtained.
• the output terminal of amplifier J 0 is connected through resistors and to its positive-phase input terminal and negative-phase input terminal. Be done.
• the positive-phase input terminal of the amplifier 0 is grounded via the resistor RJ 2 3 and the diode * type N-channel FET 1 2, between the train and source.
• the gate * drain of FETJ 2 i is connected via resistor J 2 4 .
• the gate of FET 1 2 is connected to the negative power supply 1 via the ⁇ anti-R i 2 to bias the FET J 2.
• Resistor RJ has a cash register 0 and C! Are connected in parallel.
• the catcher sheet data 0 J 4, and the connection point of the CJ via a resistor RJ 4 2 is connected to the negative-phase input terminal of the amplifier 2.
• the positive-phase input terminal of amplifier 2 is grounded, and its negative-phase input terminal and output terminal are connected via a resistor.
• the output terminal of the amplifier 2 2 is connected to the output terminal of the amplifier J 0 via the series circuit of the resistors RJS S and RI 8 4 .
• the oscillator circuit constructed in this way is substantially the same as the oscillator circuit _ ⁇ shown in Fig. 2. The only difference between them is whether the impedance controlled element 2, is the force F ⁇ ⁇ which is a photo coupler.
• connection points of resistors RJS 3 and RJS 4 are connected to the positive-phase input terminal of amplifier JS3 ⁇ 40 .
• the output terminal of the amplifier 20 is connected to the negative phase input terminal thereof via the resistor H 2 S 21 .
• the negative phase input terminal of the amplifier is grounded through the resistor RJS 20 .
• phase-shifted signal e 3 with advanced phase is given.
• This signal e 3 is amplified A 2 times by the amplifier i S M and converted into a signal e 3 2 having the same amplitude as the signal ⁇ 2.
• the signal ⁇ 3 t is 90 more than the signal e J.
• the phase is advanced. Amplification degree
• the output of amplifier 2 ⁇ ? .. and the output of amplifier JS 20 are connected to the positive phase input of amplifier J s 10 via resistor RJS 10 and resistor RJS ", respectively.
• the positive-phase input of the amplifier j 8 1 ⁇ is grounded through the resistor s lt .
• the negative-phase input of the amplifier 2 S lfl is connected to its output ..
• Resistors RJS, ⁇ and R Jf At the connection point of S, the signal and the signal e 3 s are combined. Amplitude of the combined signal e + e 3 2 is, Ru can I adjust by the resistance.
• the voltage division ratio due to the resistance R> TS ie , 18 n and RJS i Let us consider RJS 10 -R i S hinder. In this case, the signal e 3 i generated at the output end of the amplifier J s le , has a 45 ° phase advance from the signal ei, and its The amplitude is equal to the signal e I.
• the output terminal of the amplifier J is connected to the negative phase input terminal of the amplifier JS 00 via the resistor R i S e .
• the negative-phase input and output of the amplifier i S eo are connected via the resistor R 2 S T.
• the positive phase input terminal of the amplifier zs oe is grounded.
• the output of the amplifier is connected via a resistor R i S s
• the output of the amplifier JS 10 is connected via resistors R i S i S to the paces of the NPN and PNP transistors 2 14 .
• the output terminal of the amplifier JS lo is connected to the pace of the NPN transistor 2 J i e and the PNP transistor 2 J ie via the resistor R'J S, S.
• the output terminal of the amplifier 2S 30 is connected to the pace of the NPN transistor 2 1 ⁇ and the space of the PNP transistor 2 ⁇ ⁇ ⁇ via the resistor S 2 S S ,.
• Preparative run-Soo data 2 2 u, 2 In, of 2 J 15 Contact good beauty 2 2 1T co Lek data is connected to the positive supply + V C. Toran, Custa 2 Jfi ⁇ , 2 1
• the 2 jf i 8 collector is connected to the negative power supply, VE.
• the emitters of the transistors 2 J leverage, 2 l xi , 2 I, ⁇ and 2 J 1T are grounded via the parallel circuit of the capacitor 02 2 and the resistor RS J t. .
• the transistor pace-emitter when used for signal rectification, the response speed of the oscillation control of the oscillation output signal ei is fast, and the transistor Due to the current amplification effect of
• the capacitors C 2 have time constants 02 1, R e and G 2 J z R e, respectively. Be charged.
• the discharge time constants of this OR circuit are 02 B.2 l x and 02 J 2 R 2 l t , respectively.
• This CR charge / discharge circuit can achieve both a fast response speed and a large discharge time constant.
• the output end of this CR charge / discharge circuit that is,-
• e 3 2 and ⁇ 3 s peak potential + ⁇ and ⁇ are generated 0 "-transistor 2 2" emitter, connected to the positive phase input terminal of amplifier 2 3, amplifier 2 The output terminal of 3, is connected to its negative phase input terminal. The emitter of the transistor is connected to the positive phase input terminal of amplifier 2 3 t . The output terminal of amplifier 2 3 2 . is connected to its inverting input terminal. amplifier 2 3 2 output end, via a resistor, is connected to the inverting input terminal of the amplifier 2 3 3. positive Kashiwa input of the amplifier 2 3 s ground The output end of the amplifier 2 3 is connected to its anti-phase input end via a resistor ⁇ 23.
• the amplifier 2 3 3 With R2 3, ⁇ R 2 3 t , the amplifier 2 3 3 becomes an inverter with transfer function 1 1.
• the output terminal of the amplifier 2 3 and the output terminal of the amplifier 2 3 are connected via the series circuit of the resistors R23 a and R2 3 4 .
• connection point of R23 4 is connected to the gate of FETJ 2i via the resistor HJ 2 S.
• the control signal e 4 is obtained from the connection point of the resistors R 2 3 s and R 23 4 .
• WiPO WiPO It is possible to find the W pull minimum of e 4.
• oscillator circuit] _ a phase-shift oscillator circuit in which three or more stages of CR integrator circuits or CJ H differentiator circuits are connected in cascade in addition to the above-mentioned Salza type and Wien bridge type Also applies.
• Figure 16 shows the basic configuration when the amplitude control circuit according to the present invention is applied to an ALC (automatic repelling ⁇ ]) circuit or a ⁇ expander circuit.
• the phase shifter I 40 is constructed according to the prior art.
• the phase shifter 2 4 (? Is selected to have a phase shift amount of 90 °. Fig. '15
• the phase shifter J 40 has a phase shift amount of 45.
• the configuration in Fig. 16 is used as an ALC circuit, the transfer function of the amplification control circuit is used.
• the amplitude control circuit according to the present invention is suitable for use in a CR (or L R, L O) type oscillator having an oscillation frequency of about 1 MH2 or less.
• a CR (or L R, L O) type oscillator having an oscillation frequency of about 1 MH2 or less.
• the configuration as shown in Fig. 2 can be applied to the generator of low distortion sine wave at extremely low frequency below: i H t.
• the circuit +2 that controls the output fluctuation of the oscillator used in this invention can also be applied to an ALC (automatic level adjustment) circuit or an AG0 (automatic gain adjustment) circuit. That is, if the phase-shifted signal with respect to the input signal is synthesized by a well-known phase shifter, the vector synthesis circuit 2 S and the control signal generation circuit 2 S shown in FIG. (The circuit configuration corresponding to? Can be used as it is for ALC or AGO circuit. In this case, the configuration corresponding to the amplification control circuit 2 corresponds to the automatic level controlled attenuator. Becomes o

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• Engineering & Computer Science (AREA)
• Multimedia (AREA)
• Inductance-Capacitance Distribution Constants And Capacitance-Resistance Oscillators (AREA)
• Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
• Amplifiers (AREA)
• Oscillators With Electromechanical Resonators (AREA)

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• 1978
  • 1978-12-05 JP JP79500285A patent/JPS6317242B1/ja active Pending
  • 1978-12-05 WO PCT/JP1978/000040 patent/WO1980001224A1/ja not_active Ceased
  • 1978-12-05 US US06/212,086 patent/US4430627A/en not_active Expired - Lifetime
  • 1978-12-05 DE DE7979900105T patent/DE2862467D1/de not_active Expired
• 1980
  • 1980-06-17 EP EP79900105A patent/EP0022866B1/en not_active Expired

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