US9766274B2 - Current sampling circuit and method - Google Patents

Current sampling circuit and method Download PDF

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US9766274B2
US9766274B2 US14/773,758 US201414773758A US9766274B2 US 9766274 B2 US9766274 B2 US 9766274B2 US 201414773758 A US201414773758 A US 201414773758A US 9766274 B2 US9766274 B2 US 9766274B2
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current
proportional
source
sampling
ldnmos
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US20160109487A1 (en
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Xiaozhen Song
Jie Hu
Yongbo Zhang
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Sanechips Technology Co Ltd
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    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R19/00—Arrangements for measuring currents or voltages or for indicating presence or sign thereof
    • G01R19/0038—Circuits for comparing several input signals and for indicating the result of this comparison, e.g. equal, different, greater, smaller (comparing pulses or pulse trains according to amplitude)
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R19/00—Arrangements for measuring currents or voltages or for indicating presence or sign thereof
    • G01R19/0092—Arrangements for measuring currents or voltages or for indicating presence or sign thereof measuring current only
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/51—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used
    • H03K17/56—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices
    • H03K17/687—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices the devices being field-effect transistors

Definitions

  • the present disclosure relates to current sampling techniques in the field of circuit design, and in particular to a current sampling circuit and method.
  • the current in the power transistor M 1 is firstly mirrored into the sampling transistors M 2 and M 3 , after passing through the close loop negative feedback circuit consisting of the operational amplifier, the transistor M 4 and the resistors R 1 and R 2 , the mirrored current is output as a sampling current.
  • the clamping effect of the operational amplifier is used to ensure that a first input voltage V n is equal to a second input voltage V p so that the output sampling current I out is the same as the current flowing through the sampling transistors M 2 and M 3 , thereby the current in the power transistor M 1 can be sampled stably and accurately; if the current in the power transistor M 1 changes direction, the output sampling current also changes direction, thereby implementing accurate sampling of current in both directions.
  • the current sampling scheme in the related arts has the following disadvantages: 1) it is disadvantageous for applications in large-scale circuits having a high integration density; 2) the current sampling circuit is not energy-saving due to its high power consumption.
  • Embodiments of the disclosure are intended to provide a current sampling circuit that has an integrated circuit structure, a low power consumption and a low cost and can output a stable and accurate sampling current, and a corresponding current sampling method.
  • An embodiment of the disclosure provides a current sampling circuit including a proportional current output circuit and a full differential common mode negative feedback circuit,
  • the proportional current output circuit is configured to calculate a current output from a power device according to a preset proportion to obtain a first proportional current and a second proportional current, and to output the first proportional current and the second proportional current to the full differential common mode negative feedback circuit;
  • the full differential common mode negative feedback circuit is configured to shunt respectively the first proportional current and the second proportional current using a full differential common mode negative feedback network with a bias current in microamps to obtain a first sampling current and a second sampling current, and to output constantly the first sampling current and the second sampling current.
  • the power device may be implemented by a first Lateral Diffusion N-channel Metal-Oxide-Semiconductor (LDNMOS);
  • LDNMOS Lateral Diffusion N-channel Metal-Oxide-Semiconductor
  • the proportional current output circuit may include a second LDNMOS, a third LDNMOS, a fourth LDNMOS and a fifth LDNMOS;
  • the full differential common mode negative feedback circuit may include a first P-channel Metal-Oxide-Semiconductor (PMOS), a second PMOS, a third PMOS, a fourth PMOS, a first resistor, a second resistor, a second reference current source, a third reference current source, a fourth reference current source, and a fifth reference current source.
  • PMOS Metal-Oxide-Semiconductor
  • the drain of the second LDNMOS is connected with the drain of the fourth LDNMOS and a power supply
  • the gate of the second LDNMOS is connected with the gate of the first LDNMOS, the gate of the third LDNMOS and a gate driving voltage (hdrv_in from a gate driving circuit)
  • the source of the second LDNMOS is connected respectively with the drain of the third LDNMOS and the drain of the fifth LDNMOS
  • the source of the third LDNMOS is connected respectively with the source of the first LDNMOS and a first end of the first reference current source
  • the gate of the fourth LDNMOS is connected with the gate of the fifth LDNMOS
  • the source of the fourth LDNMOS is connected respectively with the source of the first PMOS and the source of the third PMOS in the full differential common mode negative feedback circuit
  • the source of the fifth LDNMOS is connected respectively with the source of the second PMOS and the source of the fourth PMOS in the full differential common mode negative feedback circuit
  • the gate of the first PMOS is connected with the gate of the second PMOS, the drain of the first PMOS is connected respectively with a first end of the first resistor, the gate of the fourth PMOS and a first end of the third reference current source;
  • the drain of the second PMOS is connected respectively with a first end of the second resistor, the gate of the third PMOS and a first end of the fourth reference current source;
  • the drain of the third PMOS is connected with a first end of the second reference current source;
  • the drain of the fourth PMOS is connected with the fifth reference current source;
  • a second end of the first resistor is connected respectively with a second end of the second resistor, the gate of the first PMOS and the gate of the second PMOS; second ends of the first reference current source, the second reference current source, the third reference current source, the fourth reference current source and the fifth reference current source are all connected to a ground point;
  • the drain of the first LDNMOS is connected to the power supply.
  • an embodiment of the disclosure further provides a current sampling method, and the method includes:
  • a current output from a power device is calculated according to a preset proportion to obtain a first proportional current and a second proportional current
  • the first proportional current and the second proportional current are shunted respectively using a full differential common mode negative feedback network and a bias current in microamps to obtain a first sampling current and a second sampling current, and the first sampling current and the second sampling current are output constantly.
  • the step that a current output from a power device is calculated according to a preset proportion to obtain a first proportional current and a second proportional current may include:
  • the first proportional current and the second proportional current are determined according to the current value of the proportional branch.
  • the step that the first proportional current and the second proportional current are shunted respectively using a full differential common mode negative feedback network and a bias current in microamps to obtain a first sampling current and a second sampling current may include:
  • I J1 is the first proportional current
  • I J2 is the second proportional current
  • I b is the bias current in microamps provided by the full differential common mode negative feedback network.
  • the current sampling circuit and method provided by the embodiments of the disclosure have the following advantages:
  • a full differential common mode negative feedback circuit including four PMOSs and two resistors is used to replace a close loop negative feedback circuit including transistors and an operational amplifiers, in this way, it can be ensured that the full differential common mode negative feedback network has a gain larger than 60 dB, generally between 70 to 88 dB, and the higher the gain is, the more a stable sampling current output can be ensured, thereby implementing a stable sampling current out;
  • the structure of the full differential common mode negative feedback circuit according to the embodiments of the disclosure is simpler when compared to that of the close loop negative feedback circuit in th related arts; and a sampling current output from the full differential common mode negative feedback circuit is only related to dimensions of a transistor and not affected by process variations, thus an accurate sampling current can be output;
  • the full differential common mode negative feedback circuit according to the embodiments of the disclosure has a higher integration density, occupies smaller pattern area and has lower cost;
  • the full differential common mode negative feedback circuit requires a smaller bias current that is in microamps and generally of 10-20 ⁇ A, thus its power consumption is reduced greatly.
  • FIG. 1 is a schematic structural diagram of a current sampling circuit in related arts of an embodiment of the disclosure
  • FIG. 2 is a schematic structural diagram of a current sampling circuit according to an embodiment of the disclosure
  • FIG. 3 is a schematic structural diagram of a current sampling circuit during practical application of an embodiment of the disclosure
  • FIG. 4 is an equivalent structural diagram of a full differential common mode negative feedback network according to an embodiment of the disclosure.
  • FIG. 5 is a schematic structural diagram of a folding current sampling circuit according to an embodiment of the disclosure.
  • FIG. 6 is a flow chart of a current sampling method according to an embodiment of the disclosure.
  • the above current sampling circuit in order to provide a main gain of the close loop negative feedback circuit, it is required to add an error amplifier or a adjustment transistor to the clamp of the operational amplifier, thus a close loop negative feedback circuit including the operational amplifier and the error amplifier or the adjustment transistor is intended to occupy too much pattern area, and required overheads of pattern area is higher, therefore, the above current sampling circuit is disadvantageous for applications in large-scale circuits having a high integration density;
  • the close loop negative feedback circuit requires large bias currents I 1 and I 2 in amps or milliamps, thus the above current sampling circuit consumes more power and is disadvantageous for the energy-saving development trend.
  • a current output from a power device is calculated according to a preset proportion to obtain a first proportional current and a second proportional current; and the first proportional current and the second proportional current are shunted respectively using a full differential common mode negative feedback network and a bias current in microamps to obtain a first sampling current and a second sampling current, and the first sampling current and the second sampling current are output constantly.
  • An embodiment of the disclosure provides a current sampling circuit for sampling current of a power device, as shown in FIG. 2 , the current sampling circuit includes a proportional current output circuit 201 and a full differential common mode negative feedback circuit 202 ,
  • the proportional current output circuit 201 is configured to calculate a current output from a power device according to a preset proportion to obtain a proportional current, and to output the proportional current to the full differential common mode negative feedback circuit 202 ;
  • the full differential common mode negative feedback circuit 202 is configured to shunt respectively the first proportional current and the second proportional current using a full differential common mode negative feedback network with a bias current in microamps to obtain a first sampling current and a second sampling current, and to output constantly the first sampling current and the second sampling current.
  • the power device may be implemented by a Negative channel Metal Oxide Semiconductor (NMOS), a Positive channel Metal Oxide Semiconductor (PMOS), a Lateral Diffusion NMOS (LDNMOS), a Lateral Diffusion PMOS (LDPMOS), and a PNP transistor or an NPN transistor that has power output function; preferably, the embodiment of the disclosure is implemented by an LDNMOS, and a first LDNMOS M 1 shown in FIG. 3 is namely a power device.
  • NMOS Negative channel Metal Oxide Semiconductor
  • PMOS Positive channel Metal Oxide Semiconductor
  • LDNMOS Lateral Diffusion NMOS
  • LDPMOS Lateral Diffusion PMOS
  • PNP transistor or an NPN transistor that has power output function preferably, the embodiment of the disclosure is implemented by an LDNMOS, and a first LDNMOS M 1 shown in FIG. 3 is namely a power device.
  • the proportional current output circuit 201 includes a second LDNMOS M 2 , a third LDNMOS M 3 , a fourth LDNMOS M 4 and a fifth LDNMOS M 5 ;
  • the full differential common mode negative feedback circuit 202 includes a first
  • PMOS M 6 a second PMOS M 7 , a third PMOS M 8 , a fourth PMOS M 9 , a first resistor R 1 , a second resistor R 2 , a second reference current source I 2 , a third reference current source I 3 , a fourth reference current source I 4 , and a fifth reference current source I 5 .
  • transistors M 2 , M 3 , M 4 , M 5 in the proportional current output circuit 201 are implemented by an LDMOS transistor of the same type as that of power transistor M 1 , with a gate voltage being a gate driving voltage (hdrv_in output from a gate driving circuit), thus respective transistors operate in the linear region and are equivalent to resistors, and the maximum withstanding voltage of each of the transistors M 1 , M 2 , M 3 , M 4 , M 5 is 18V.
  • transistors M 6 , M 7 , M 8 , M 9 in the full differential common mode negative feedback circuit 202 are implemented by a PMOS transistor with a maximum withstanding voltage of 20V.
  • transistors in the full differential common mode negative feedback circuit 203 can also be implemented, as required, by NMOS, NPN or PNP transistors.
  • connection relation of respective devices in the current sampling circuit according to the embodiment of the disclosure is elaborated with reference to FIG. 2 .
  • the drain of the second LDNMOS M 2 is connected with the drain of the fourth LDNMOS M 4 and a power supply V in
  • the gate of the second LDNMOS M 2 is connected with the gate of the first LDNMOS M 1
  • the gate of the third LDNMOS and an output hdrv_in of a gate driving circuit namely driven by a voltage signal output from the gate driving circuit
  • the source of the second LDNMOS M 2 is connected respectively with the drain of the third LDNMOS M 3 and the drain of the fifth LDNMOS M 5
  • the source of the third LDNMOS M 3 is connected respectively with the source of the first LDNMOS M 1 and one end of the first reference current source I 1
  • the gate of the fourth LDNMOS M 4 is connected with the gate of the fifth LDNMOS M 5
  • the source of the fourth LDNMOS M 4 is connected respectively with the source of the first PMOS M 6 and the source of the third PMOS M 8 in the full
  • the gate of the first PMOS M 6 is connected with the gate of the second PMOS M 7 , the drain of the first PMOS M 6 is connected with one end of the first resistor R 1 , the gate of the fourth PMOS M 9 and one end of the third reference current source I 3 ; the drain of the second PMOS M 7 is connected with one end of the second resistor R 2 , the gate of the third PMOS M 8 and one end of the fourth reference current source I 4 ; the drain of the third PMOS M 8 is connected with one end of the second reference current source I 2 ; the drain of the fourth PMOS M 9 is connected with the fifth reference current source I 5 ; the other end of the first resistor R 1 is connected respectively with the other end of the second resistor R 2 , the gate of the first PMOS M 6 and the gate of the second PMOS M 7 ; the other ends of the first reference current source the second reference current source I 2 , the third reference current source I 3 , the fourth reference current source I 4 and the fifth
  • the drain of the first LDNMOS M 1 is connected to the power supply V in .
  • the operation principle of the current sampling circuit is as follows.
  • the power device i.e., a first LDNMOS M 1 outputs I power to the proportional current output circuit 201
  • the proportional current output circuit 201 calculates the output current I power according to a preset proportion to obtain a first proportional current and a second proportional current and outputs them to the full differential common mode negative feedback circuit 202 .
  • the gate voltage of the transistors M 1 , M 2 , M 3 , M 4 , M 5 are driven by hdrv_in, thus these transistors operate in the linear region and are equivalent to resistors, and each of the transistors M 1 , M 2 , M 3 , M 4 , M 5 has a maximum withstanding voltage of 18 V since the voltage V in input by the power supply has a maximum value of 18 V.
  • G ⁇ ⁇ C ox ⁇ W L ⁇ ( V gs - V th - V ds ) ⁇ W L , where ⁇ C ox is a constant factor of the transistor, V gs is a gate-source voltage of the transistor, V th is a threshold voltage of the transistor, V ds is a drain-source voltage of the transistor, W is the width of the channel, L is the length of the channel; since the conductance of the transistor
  • the proportional current output circuit 201 firstly calculates the output current I power according to the preset proportion to obtain:
  • 1 G 1 , 1 G 2 , 1 G 3 are resistances of the transistors M 1 , M 2 , M 3 respectively;
  • the obtained current I s1 is output to drains of transistors M 3 , M 5 so as to obtain a first proportional current I J1 flowing through the transistor M 4 and a second proportional current I J2 flowing through the transistor M 5 , the first proportional current I J1 is output to sources of the transistors M 6 and M 8 in the full differential common mode negative feedback circuit 202 , and the second proportional current I J2 is output to sources of the transistors M 7 and M 9 in the full differential common mode negative feedback circuit 202 ; the transistors M 4 and M 5 have an effect of isolating a high voltage, thus it is possible to prevent breakdown of the full differential common mode negative circuit 202 by the high voltage.
  • the full differential common mode negative feedback circuit 202 is in the form of a full differential common mode negative feedback network consisting of transistors M 6 , M 7 , M 8 , M 9 , resistors R 1 , R 2 , the second reference current source I 2 , a third reference current source I 3 , a fourth reference current source I 4 , and a fifth reference current source I 5 , and the third reference current source and the fourth reference current source are used to provide the full differential common mode negative feedback network with a bias current I b in microamps; the first proportional current I J1 and the second proportional current I J2 are shunted respectively to obtain a first sampling current I sense+ and a second sampling current I sense ⁇ .
  • I J1 I sense+ +I 3
  • I J2 I sense ⁇ +I 4
  • I sense+ is a current flowing through the transistor M 8
  • I sense ⁇ is a current flowing through the transistor M 9
  • I 3 is a current flowing through the third reference current source
  • I 4 is a current flowing through the fourth reference current source
  • I b is a benchmark bias current providing the transistors M 6 , M 7 with a quiescent operating point and as low as 10 to 20 ⁇ A, thus compared to the current sampling circuit in related arts, the current sampling circuit according to the embodiment of the disclosure has a greatly-reduced power consumption.
  • the full differential common mode negative feedback network is equivalent to a negative feedback network including an operational amplifier, as shown in FIG. 4 ; wherein a circuit consisting of transistors M 6 , M 7 and resistors R 1 , R 2 is equivalent to an operational amplifier, points C and D are taken as inputs of the operational amplifier, and the two sampling currents are taken approximately as being connected to the input and output of the operational amplifier.
  • the current sampling circuit Due to the clamping effect of the operational amplifier, its inputs C and D have a same voltage, the first sampling current I sense+ from the output is fed back to the input C of the operational amplifier via the transistor M 8 , the second sampling current I sense ⁇ from the output is fed back to the input D of the operational amplifier via the transistor M 9 , thus an effect of an operational amplifier feedback network is resulted, and it is possible to provide the current sampling circuit with a stable gain, therefore, the current sampling circuit according to the embodiment of the disclosure occupies smaller pattern area, has a higher integration density and lower cost.
  • KVL Kirchhoff's Voltage Law
  • V sg6 is a gate-source voltage of the transistor M 6
  • V sg7 is a gate-source voltage of the transistor M 7 ; it can be obtained from equations (1), (2), (3) and (4):
  • the first sampling current I sense+ in the embodiment of the disclosure is only related to the width and length of a transistor and not affected by process variations, thus a sampling current with improved accuracy can be obtained.
  • the proportional current output circuit 201 and the full differential common mode negative feedback circuit 202 can be applied to a charger chip of a power supply management chip.
  • the current sampling circuit in the embodiment of the disclosure can also be of a folding structure, the folding current sampling circuit has a similar principle as that of the above current sampling circuit, and it has flexible applications, as shown in FIG. 5 , the current sampling circuit includes a proportional current output circuit 501 and a full differential common mode negative feedback circuit 502 ;
  • the proportional current output circuit 501 includes a second LDNMOS M 2 , a third LDNMOS M 3 , a fourth LDNMOS M 4 , a fifth LDNMOS M 5 , a sixth LDNMOS M 6 , a seventh LDNMOS M 7 , and a eighth LDNMOS M 8 ;
  • the full differential common mode negative feedback circuit 502 includes a first PMOS M 9 , a second PMOS M 10 , a third PMOS M 11 , a fourth PMOS M 12 , a fifth PMOS M 13 , a sixth PMOS M 14 , a first resistor R 1 , a second resistor R 2 , a second reference current source I 2 , a third reference current source I 3 , a fourth reference current source I 4 , a ninth NMOS M 19 , a tenth NMOS M 20 , a eleventh NMOS M 21 , a twelfth NMOS M 22 , a thirteenth NMOS M 23 , and a fourteenth NMOS M 24 ;
  • transistors M 2 , M 3 , M 4 , M 5 , M 6 , M 7 , M 8 in the proportional current output circuit 201 are implemented by an LDMOS transistor of the same type as that of power transistor M 1 , with a gate voltage being a gate driving voltage hdrv_in, thus respective transistors operate in the linear region and are equivalent to resistors, and each of the transistors is implemented by a transistor with the maximum withstanding voltage of 18 V.
  • voltages of transistors M 9 , M 10 , M 11 , M 12 , M 13 , M 14 in the full differential common mode negative feedback circuit are all maintained at a voltage of 20 V; voltages of transistors M 19 , M 20 , M 21 , M 22 , M 23 , M 24 can be adjusted appropriately to ensure a benchmark bias current I b desired in the full differential common mode negative feedback circuit 502 , and the benchmark bias current I b providing M 10 , M 11 with a quiescent operating point is as low as 10 to 20 ⁇ A.
  • transistors in the full differential common mode negative feedback circuit 502 can also be implemented, as required, by NMOS, NPN or PNP transistors.
  • connection relation of respective devices in the folding current sampling circuit according to the embodiment of the disclosure is elaborated below with reference to FIG. 5 .
  • the drain of the transistor M 2 is connected with a power supply V in
  • the gate of the transistor M 2 is connected with the gate of the transistor M 1 , the gate of the transistor M 3 , the gate of the transistor M 4 , the gate of the transistor M 5 and a driving voltage hdrv_in
  • the source of the transistor M 2 is connected with the drain of the transistor M 3 and the drain of the transistor M 6 in a current mirror circuit 502
  • the source of the transistor M 3 is connected with the source of the transistor M 4 and one end of the first reference current source I 1
  • the gate of the transistor M 6 is connected with the gate of the transistor M 7 and the gate of transistor M 8
  • the source of the transistor M 6 is connected with the source of the transistor M 9 and the source of the transistor M 13 in the full differential common mode negative feedback circuit 502
  • the source of the transistor M 7 is connected with the source of the transistor M 10 and the source of the transistor M 11 in the full differential common mode negative feedback circuit 502
  • the source of the transistor M 7 is connected with the
  • the drain of the transistor M 9 is connected with the source of the transistor M 21 and the drain of the transistor M 22 , the gate of the transistor M 9 is connected with the gate of the transistor M 10 , the gate of the transistor M 11 and the gate of the transistor M 12 ; the drain of the transistor M 10 is connected with the resistor R 1 and the drain of the transistor M 21 ; the drain of the transistor M 11 is connected with the resistor R 2 and the drain of the transistor M 23 ; the drain of the transistor M 12 is connected with the source of the transistor M 23 and the drain of the transistor M 24 ; the drain of the transistor M 13 is connected with one end of the second reference current source I 2 ; the drain of the transistor M 14 is connected with one end of the fourth reference current source I 4 , the gate of the transistor M 13 is connected with the drain of the transistor M 21 ; the gate of the transistor M 19 is connected with the gate of the transistor M 21 , the drain of the transistor M 19 is connected with the gate of the transistor M 21 , the drain of the transistor M 19 is connected with the gate of
  • the drain of the transistor M 1 is connected to the power supply
  • the current of the transistor M 1 in the folding current sampling circuit is scaled twice through the proportional current output circuit 501 , the output current becomes smaller than that of the above current sampling circuit, thus the power consumption is lowered further;
  • the transistors M 10 , M 11 , M 13 , M 14 , the first resistor R 1 and the second resistor constitute a full differential common mode negative feedback network;
  • the transistors M 9 , M 20 , M 21 , M 22 , M 23 , M 24 constitute a folding structure, and the folding current sampling circuit according to the embodiment of the disclosure can meet application demand in low voltage field.
  • current sampling circuits shown in FIG. 2, 3 or 5 can be applied in devices or apparatuses that need current sampling.
  • an embodiment of the disclosure further provides a current sampling method, since the principle of the method is similar to that of the current sampling circuit, for the implementation of the method and its principle, please refer to the implementation of the circuit and its corresponding principle, and duplicated content thereof will be omitted.
  • the current sampling method provided by the embodiment of the disclosure includes:
  • step S 601 a current output from a power device is calculated according to a preset proportion to obtain a first proportional current and a second proportional current;
  • I power is the current output from the power device
  • I s1 is the current value of the proportional branch
  • 2X is the preset proportion
  • Step S 602 the first proportional current and the second proportional current are shunted respectively using a full differential common mode negative feedback network and a bias current in microamps to obtain a first sampling current and a second sampling current, and the first sampling current and the second sampling current are output constantly.
  • I J1 is the first proportional current
  • I J2 is the second proportional current
  • I b is the bias current in microamps provided by the full differential common mode negative feedback network.
US14/773,758 2014-04-03 2014-11-10 Current sampling circuit and method Active 2035-02-08 US9766274B2 (en)

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CN201410134447.8A CN104977450B (zh) 2014-04-03 2014-04-03 一种电流采样电路及方法
CN201410134447.8 2014-04-03
PCT/CN2014/090733 WO2015149521A1 (fr) 2014-04-03 2014-11-10 Circuit et procédé d'échantillonnage de courant

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